CN106685461B - Digital talkback terminal - Google Patents
Digital talkback terminal Download PDFInfo
- Publication number
- CN106685461B CN106685461B CN201710073930.3A CN201710073930A CN106685461B CN 106685461 B CN106685461 B CN 106685461B CN 201710073930 A CN201710073930 A CN 201710073930A CN 106685461 B CN106685461 B CN 106685461B
- Authority
- CN
- China
- Prior art keywords
- digital
- voltage
- power
- unit
- gradually changed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/3827—Portable transceivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q5/00—Selecting arrangements wherein two or more subscriber stations are connected by the same line to the exchange
- H04Q5/24—Selecting arrangements wherein two or more subscriber stations are connected by the same line to the exchange for two-party-line systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transmitters (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a digital talkback terminal which comprises an integrated talkback chip with a zero intermediate frequency digital communication function, wherein the integrated talkback chip is used for generating voltage step waves with gradually changed rising edges and gradually changed falling edges according to a gradually changed voltage value stored in the integrated talkback chip, and outputting the voltage step waves as bias voltages of a power amplification unit; therefore, the digital interphone terminal generates the bias voltage by using the step wave and controls the amplification power of the power amplification unit root, and because the rising edge and the falling edge of the voltage step wave are gradually changed and the change of the corresponding bias voltage is also gradually changed, the amplification power of the power amplification unit is also slowly increased and decreased, the requirements that the transmitting power curve of the digital interphone meeting the DMR requirement needs to be slowly increased and decreased are met, and the scattering during time slot switching can be reduced.
Description
Technical Field
The invention relates to the field of digital talkback, in particular to a digital talkback terminal.
Background
In the field of the existing analog talkback, the amplification power needs to be controlled, specifically: the micro control unit MCU outputs square waves to the operation comparison unit, the operation comparison unit outputs bias voltage according to the square waves and the real-time amplification power of the power amplification unit, and the power amplification unit amplifies the power of the signal to be processed according to the bias voltage.
However, since the square wave is immediately performed and instantaneously completed when the level is reversed, the variation of the bias voltage is also abrupt, and thus the amplification power of the power amplifying unit is also transient. The digital wireless communication technology (DMR) is directed at a digital interphone, and when the transmission power of the digital interphone is required to rapidly increase and decrease, a power curve needs to slowly increase and decrease as required, which results in that the conventional analog interphone adopts a technology of controlling the power change of a power amplification unit by a square wave, and cannot meet the requirements of the digital interphone, and thus cannot be applied to the field of digital interphone.
Disclosure of Invention
The invention provides a digital talkback terminal, which meets the requirements of DMR.
The invention provides a digital intercommunication terminal, comprising: the system comprises a power supply, an integrated talkback chip with a zero intermediate frequency digital communication function and a power amplification unit; the power supply supplies power to the integrated talkback chip and the power amplification unit; the integrated talkback chip is used for generating voltage step waves with gradually changed rising edges and gradually changed falling edges according to the gradually changed voltage values stored in the integrated talkback chip, and the voltage step waves are used as bias voltages of the power amplification unit to be output; and the power amplification unit is used for carrying out power amplification on the signal to be processed according to the bias voltage.
Furthermore, the gradient time of the rising edge of the voltage step wave is more than 0.5 millisecond and less than 1.5 millisecond, and the gradient time of the falling edge of the voltage step wave is more than 0.5 millisecond and less than 1.5 millisecond.
Furthermore, the rising edge gradient time and the falling edge gradient time of the voltage step wave are both 1 millisecond.
Furthermore, the gradual change shape of the rising edge and the gradual change shape of the falling edge of the step wave are smooth curves or straight lines.
Furthermore, the gradual change voltage value comprises a rising gradual change voltage value and a falling gradual change voltage value, a plurality of voltage values of the rising gradual change voltage value are sequentially increased in an increasing mode, and a plurality of voltage values of the falling gradual change voltage value are sequentially decreased in a decreasing mode.
Furthermore, the number of the ascending gradient voltage value and the descending gradient voltage value respectively corresponds to the smoothness requirement of the gradient shape.
Further, the number of the rising ramp voltage value and the number of the falling ramp voltage value are respectively 128.
Furthermore, the integrated talkback chip comprises a micro-processing unit, a memory unit and a digital-to-analog conversion unit as peripheral equipment; the memory unit is used for storing the gradual change voltage value, the microprocessing unit is used for controlling the digital-to-analog conversion unit to sequentially acquire the gradual change voltage value, and the digital-to-analog conversion unit is used for generating a voltage step wave according to the gradual change voltage value.
Furthermore, the integrated talkback chip also comprises a direct memory access controller used as the peripheral, a memory register of the direct memory access controller is written with a first address of the memory unit, a peripheral register of the direct memory access controller is written with an address of a conversion value register in the digital-to-analog conversion unit, the direct memory access controller is in a transmission mode that the memory is transmitted to the peripheral and one word is transmitted each time, and a trigger source of the direct memory access controller is a timer.
Furthermore, the memory unit is a pseudo static random access memory, a voltage value table composed of 128 point voltage values is stored in the pseudo static random access memory in sequence, the microprocessing unit is used for taking out the voltage values from the voltage value table according to the set time and the ascending sequence when starting transmission and outputting the voltage values through the digital-to-analog conversion unit, and for taking out the voltage values from the voltage value table according to the set time and the descending sequence when closing transmission and outputting the voltage values through the digital-to-analog conversion unit.
The invention has the beneficial effects that:
the invention provides a novel digital talkback terminal, which comprises an integrated talkback chip with a zero intermediate frequency digital communication function, wherein the integrated talkback chip is used for generating voltage step waves with gradually changed rising edges and gradually changed falling edges according to a gradually changed voltage value stored in the integrated talkback chip, and outputting the voltage step waves as bias voltages of a power amplification unit; therefore, the digital intercom terminal realizes the purpose of generating the bias voltage by using the step wave and controlling the amplification power of the power amplification unit root, in the whole process, because the rising edge and the falling edge of the step wave are gradually changed, and the change of the correspondingly generated bias voltage is also gradually changed, on the basis, the amplification power of the power amplification unit is also slowly increased and decreased, when the digital intercom transmitting power meeting the DMR requirement is rapidly increased and decreased, the power curve needs to be slowly increased and decreased according to the requirement, meanwhile, the slow increase and decrease of the power curve can also reduce the scattering during time slot switching, and reduce the interference to other chips or devices.
Drawings
Fig. 1 is a schematic structural diagram of a digital intercom terminal according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a digital intercom chip according to a first embodiment of the present invention;
fig. 3 is a first schematic diagram of a voltage step wave according to a first embodiment of the present invention;
fig. 4 is a second schematic diagram of the voltage step wave according to the first embodiment of the present invention;
fig. 5 is a circuit connection diagram of a digital intercom terminal according to a second embodiment of the present invention;
fig. 6 is a circuit connection diagram of an integrated intercom chip according to a second embodiment of the present invention;
fig. 7 is a circuit connection diagram of an integrated intercom chip according to a second embodiment of the present invention.
Detailed Description
The invention will now be further explained by way of an example of an embodiment in conjunction with the accompanying drawings.
The first embodiment:
fig. 1 is a schematic structural diagram of a digital intercom terminal according to a first embodiment of the present invention, and as can be seen from fig. 1, in this embodiment, the digital intercom terminal according to the present invention includes: a power supply 11, an integrated talkback chip SOC (system on chip) 12 having a zero intermediate frequency digital communication function, and a power amplification unit 13; the power supply supplies power to the integrated talkback chip and the power amplification unit; the power supply 11 supplies power to the integrated talkback chip 12 and the power amplification unit 13; the integrated talkback chip 12 is configured to generate a voltage step wave with a gradually changing rising edge and a gradually changing falling edge according to a gradually changing voltage value stored therein by using a function algorithm, and output the voltage step wave as a bias voltage of the power amplification unit, as shown in the schematic diagram of fig. 1 and the specific schematic diagrams shown in fig. 3 and 4; the power amplification unit 13 performs power amplification on the signal to be processed according to the bias voltage. In practical applications, the power amplifying unit 13 obtains power from the power supply, and whether to operate and how to operate are controlled by whether or not there is a bias voltage and the magnitude of the bias voltage.
As shown in fig. 3 or 4, in some embodiments, the rising edge gradient time of the step wave in the above embodiments is greater than 0.5 ms and less than 1.5 ms, and the falling edge gradient time of the step wave is greater than 0.5 ms and less than 1.5 ms.
As shown in fig. 3 or 4, in some embodiments, the rising edge transition time and the falling edge transition time of the step wave in the above embodiments are both 1 ms.
As shown in fig. 3 or 4, in some embodiments, the high level duration of the step wave in the above embodiments is 27.5 milliseconds.
As shown in fig. 3, in some embodiments, the rising edge gradient shape and the falling edge gradient shape of the step wave in the above embodiments include at least 2 steps. In practical application, the larger the number of steps, the gentler the ascending and descending trends, and the better the effect.
As shown in fig. 4, in some embodiments, the ascending edge gradient shape and the descending edge gradient shape of the step wave in the above embodiments are smooth curves or straight lines.
As shown in fig. 2, in some embodiments, the integrated talk-back chip 12 in the above embodiments includes a micro-processing unit 121, a memory unit 122, and a digital-to-analog conversion unit 123 as a peripheral; the memory unit 122 is configured to store the gradual voltage value, the microprocessor unit 121 is configured to control the digital-to-analog conversion unit 123 to sequentially obtain the gradual voltage value, and the digital-to-analog conversion unit 123 is configured to generate a voltage step wave according to the gradual voltage value.
As shown in fig. 2, in some embodiments, the integrated intercom chip 12 in the above embodiments further includes a Direct Memory Access (DMA) 124 as an external device, the DMA is a data exchange mode that directly accesses data from the Memory without passing through the CPU, a Memory register of the DMA 124 is written with a first address of a Memory unit, an external register of the DMA is written with an address of a conversion value register in the digital-to-analog conversion unit, the DMA is transmitted in a manner that the Memory is transmitted to the external device and one word is transmitted each time, and a trigger source of the DMA is a timer.
In some embodiments, the memory unit in the above embodiments is a PSRAM (pseudo static random access memory), a voltage value table composed of 128-point voltage values is sequentially stored in the pseudo static random access memory, the microprocessor unit is configured to, when starting transmission, take out voltage values from the voltage value table in an increasing order by a set time (1 millisecond 128 points, each point interval 7.8us) and output through the digital-to-analog conversion unit, and when closing transmission, take out voltage values from the voltage value table in a decreasing order by a set time (1 millisecond 128 points, each point interval 7.8us) and output through the digital-to-analog conversion unit.
The embodiment provides a new digital talkback terminal, which comprises an integrated talkback chip with a zero intermediate frequency digital communication function, wherein the integrated talkback chip is used for generating voltage step waves with gradually changed rising edges and gradually changed falling edges according to a gradually changed voltage value stored in the integrated talkback chip, and outputting the voltage step waves as bias voltages of a power amplification unit; therefore, the digital intercom terminal realizes the purpose of generating the bias voltage by using the step wave and controlling the amplification power of the power amplification unit root, in the whole process, because the rising edge and the falling edge of the step wave are gradually changed, and the change of the correspondingly generated bias voltage is also gradually changed, on the basis, the amplification power of the power amplification unit is also slowly increased and decreased, when the digital intercom transmitting power meeting the DMR requirement is rapidly increased and decreased, the power curve needs to be slowly increased and decreased according to the requirement, meanwhile, the slow increase and decrease of the power curve can also reduce the scattering during time slot switching, and reduce the interference to other chips or devices.
The present invention will now be further explained with reference to specific application scenarios.
Second embodiment:
the present embodiment is described by taking a specific application of the voltage step wave as an example, and a circuit of the digital pair terminal related to the present embodiment is shown in fig. 5, and includes: an integrated talkback chip SOC (system on chip) 51 (as a micro control unit in the above embodiment) having a zero intermediate frequency digital communication function, a comparator 52 (as a comparison control circuit in the above embodiment), a differential comparison amplifier 53, a detection resistor 54 (3 resistors formed in parallel in fig. 5), 2-stage power amplifiers 55-1 and 55-2 (as power amplification units in the above embodiment), and a power supply not shown in fig. 5.
In practical applications, the power supply voltage of the 2-stage power amplifiers 55-1 and 55-2 is a stable voltage value U, which amplifies power P (real time) U × I (real time); the resistance R of the detection resistor 54 is constant, and the voltage difference U (voltage difference) between both ends thereof changes with the change of the power supply current I (real time) of the power supply 2 stages of power amplifiers 55-1 and 55-2, i.e., U (voltage difference) ═ R I (real time); therefore, U (differential pressure) ((R/U) × P (real time)), which are in a direct proportion relationship, i.e. the change of U (differential pressure) can reflect the change of P (real time), so that the present embodiment can realize the detection of P (real time) by detecting U (differential pressure).
The operation mechanism of the comparator 52 is a negative feedback mechanism, when the detected P (real time) is greater than the power threshold (optimal operating power), i.e. U (differential pressure) is greater than the voltage threshold (corresponding to the optimal operating power), the bias voltage U (bias) needs to be decreased to decrease P (real time) to make it close to and become the optimal operating power, correspondingly, when the detected P (real time) is less than the power threshold (optimal operating power), i.e. U (differential pressure) is less than the voltage threshold (corresponding to the optimal operating power), the bias voltage U (bias) needs to be increased to increase P (real time) to make it close to and become the optimal operating power, and the power amplification unit is made to operate at the optimal operating power as much as possible by the negative feedback mechanism.
The core of the embodiment is an integrated talkback chip SOC51, which is used for generating a step wave as shown in fig. 3 or fig. 4 by using a functional algorithm (most preferably, the rising edge and the falling edge are smooth curves as shown in fig. 4), thus, the digital intercom system realizes the purpose of generating the bias voltage by using the step wave and controlling the amplification power of the power amplification unit root, and in the whole process, because the rising edge and the falling edge of the step wave are gradually changed, the change of the correspondingly generated bias voltage is also gradual, on the basis, the amplification power of the power amplification unit is also slowly increased and decreased, when the transmission power of the digital interphone meeting the DMR requirement is rapidly increased and decreased, the power curve needs to be slowly increased and decreased according to the requirement, meanwhile, the slow rise and fall of the power curve can also reduce scattering during time slot switching, and reduce interference to other chips or devices.
Meanwhile, the embodiment also provides a specific schematic diagram of the integrated talkback chip SOC51, as shown in fig. 6, the integrated talkback chip SOC51 provided by the embodiment includes: a digital signal processing DSP unit 61, a 16-bit voice signal codec unit 62, an audio output power amplifier unit 63, a microphone amplification circuit unit 64, a 32-bit reduced instruction microprocessor unit 65, a power management PMU unit 66, a 16MB PSRAM memory unit 67, a 16MB FLASH memory unit 68, and a radio frequency mobile radio receiver transmitter unit 69, as well as some data interfaces not shown, etc.; wherein, the 16MB PSRAM memory unit 67 and the 16MB FLASH memory unit 68 may exist at the same time or only one; the radio frequency mobile radio receiver transmitter unit 69 is used for processing data by using low voltage (2.4V) broadband (100-.
Specifically, a circuit connection diagram of the integrated intercom chip related to this embodiment is shown in fig. 7, and is not described again.
In practical applications, the DMR protocol requires that a linear power increase be met for 1.25ms when starting the radio frequency transmission and a linear power decrease be met for 1.25ms when shutting down the transmission. The linear increment of the power is realized by controlling the PA circuit through the digital-to-analog conversion module DA, so that the DA is required to uniformly output 128 voltage points within 1.25ms from the moment of starting transmission, and the 128 voltage points are required to be linearly increased from 0-3.3V. 128 voltage points are uniformly output within 1.25ms from the moment of stopping transmitting, and the 128 points need to be linearly decreased from 3.3-0V.
If this function is implemented in software alone, it is required to operate the DA once every about 9.7us, which results in the cpu processing only the DA function and not other things within 1.25ms of the moment when the transmission is started and stopped. The integrated talkback chip provided by the embodiment realizes that software and hardware are mutually matched to complete the function, and the software only needs to configure hardware and then starts the hardware to work.
The principle of the embodiment is as follows:
the cpu stores 128 voltage values to be converted into the RAM, counts by a timer and triggers the DMA to place data in the RAM into a register to be converted of the DA. The voltage linear output can be realized within 1.25ms when the voltage linear output reaches the DMR requirement through DA conversion at 128 points automatically.
In practical application, the implementation steps include:
step 1, the cpu stores the calculated data (generally 2-system number) corresponding to 128 voltage values into the RAM;
step 2, configuring DMA;
the step comprises the following steps in detail:
a. putting the first address of the RAM with 128 points into a DMA memory register;
b. the address of the DA conversion value register is put into a DMA peripheral register;
c. setting DMA transmission mode to transmit memory to peripheral, and transmitting one word for each configuration;
d. setting a DMA trigger source, and setting the DMA trigger source as a TIMER TIMER;
step 3, starting TIMER;
and 4, starting DA.
Therefore, the DA can uniformly output 128 voltages through the DA PIN PIN within 1.25ms to control the PA circuit, so that the linear power control required by the DMR protocol is realized. The difference between the linear power control of the start transmission and the linear power control of the stop transmission is that the voltage of the start transmission is linearly increased and the voltage of the stop transmission is linearly decreased, so that the 128 point voltages of the start transmission are stored in the RAM in increments, and the 128 point voltages of the stop transmission are stored in the RAM in decrements.
In summary, the implementation of the present invention has at least the following advantages:
the invention provides a novel digital talkback terminal, which comprises an integrated talkback chip with a zero intermediate frequency digital communication function, wherein the integrated talkback chip is used for generating voltage step waves with gradually changed rising edges and gradually changed falling edges according to a gradually changed voltage value stored in the integrated talkback chip, and outputting the voltage step waves as bias voltages of a power amplification unit; therefore, the digital intercom terminal realizes the purpose of generating the bias voltage by using the step wave and controlling the amplification power of the power amplification unit root, in the whole process, because the rising edge and the falling edge of the step wave are gradually changed, and the change of the correspondingly generated bias voltage is also gradually changed, on the basis, the amplification power of the power amplification unit is also slowly increased and decreased, when the digital intercom transmitting power meeting the DMR requirement is rapidly increased and decreased, the power curve needs to be slowly increased and decreased according to the requirement, meanwhile, the slow increase and decrease of the power curve can also reduce the scattering during time slot switching, and reduce the interference to other chips or devices.
The above embodiments are only examples of the present invention, and are not intended to limit the present invention in any way, and any simple modification, equivalent change, combination or modification made by the technical essence of the present invention to the above embodiments still fall within the protection scope of the technical solution of the present invention.
Claims (9)
1. A digital intercom terminal, comprising: the system comprises a power supply, an integrated talkback chip with a zero intermediate frequency digital communication function, a power amplification unit and a comparison control unit; the power supply supplies power to the integrated talkback chip and the power amplification unit; the integrated talkback chip is used for generating voltage step waves with gradually changed rising edges and gradually changed falling edges according to the gradually changed voltage values stored in the integrated talkback chip, the gradually changed shape of the rising edges and the gradually changed shape of the falling edges of the step waves are smooth curves, and the voltage step waves are used as bias voltages of the power amplification unit to be output; the power amplification unit is used for carrying out power amplification on the signal to be processed according to the bias voltage; and the comparison control unit adjusts the bias voltage according to the comparison result of the real-time amplification power and the optimal working power.
2. The digital intercom terminal according to claim 1, wherein a rising edge ramp time of said voltage step wave is greater than 0.5 milliseconds and less than 1.5 milliseconds, and a falling edge ramp time of said voltage step wave is greater than 0.5 milliseconds and less than 1.5 milliseconds.
3. The digital intercom terminal according to claim 2, wherein a rising edge ramp time and a falling edge ramp time of said voltage step wave are both 1 millisecond.
4. The digital intercom terminal according to claim 1, wherein said ramp voltage values include a rising ramp voltage value and a falling ramp voltage value, a plurality of voltage values of said rising ramp voltage value being sequentially increasing, and a plurality of voltage values of said falling ramp voltage value being sequentially decreasing.
5. The digital intercom terminal according to claim 4, wherein the numbers of said rising gradation voltage value and said falling gradation voltage value correspond to smoothness requirements of gradation shapes thereof, respectively.
6. The digital intercom terminal according to claim 5, wherein the number of said rising gradation voltage values and said falling gradation voltage values is 128 respectively.
7. The digital intercom terminal according to any one of claims 1 to 6, wherein the integrated intercom chip comprises a micro-processing unit, a memory unit and a digital-to-analog conversion unit as peripheral equipment; the storage unit is used for storing the gradual change voltage value, the microprocessing unit is used for controlling the digital-to-analog conversion unit to sequentially acquire the gradual change voltage value, and the digital-to-analog conversion unit is used for generating the voltage step wave according to the gradual change voltage value.
8. The digital intercom terminal according to claim 7, wherein the integrated intercom chip further comprises a direct memory access controller as an external device, a memory register of the direct memory access controller is written with a first address of the memory unit, an external register of the direct memory access controller is written with an address of a conversion value register in the digital-to-analog conversion unit, the direct memory access controller is transmitted in a manner that a memory is transmitted to the external device and one word is transmitted at a time, and a trigger source of the direct memory access controller is a timer.
9. The digital intercom terminal according to claim 7, wherein said memory unit is a pseudo-static random access memory, a table of voltage values consisting of 128 point voltage values is sequentially stored in said pseudo-static random access memory, said microprocessor unit is adapted to take out voltage values from said table of voltage values at a set time in ascending order and output through a digital-to-analog conversion unit when transmission is started, and to take out voltage values from said table of voltage values at a set time in descending order and output through said digital-to-analog conversion unit when transmission is turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710073930.3A CN106685461B (en) | 2017-02-10 | 2017-02-10 | Digital talkback terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710073930.3A CN106685461B (en) | 2017-02-10 | 2017-02-10 | Digital talkback terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106685461A CN106685461A (en) | 2017-05-17 |
| CN106685461B true CN106685461B (en) | 2020-04-17 |
Family
ID=58860849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710073930.3A Active CN106685461B (en) | 2017-02-10 | 2017-02-10 | Digital talkback terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106685461B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546958A (en) * | 2007-04-27 | 2014-01-29 | 瑞萨电子株式会社 | Transmitter, RF transmitter signal processor and method for operation of transmitter |
| CN205029811U (en) * | 2015-09-29 | 2016-02-10 | 深圳市万博鑫科技有限公司 | Duplexing intercom of digit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1317064A1 (en) * | 2001-11-28 | 2003-06-04 | TTPCOM Limited | Transmitter RF power control |
| CN101394195B (en) * | 2008-10-17 | 2013-03-27 | 闻泰通讯股份有限公司 | Method for suppressing GSM stray |
| US8324967B2 (en) * | 2010-06-04 | 2012-12-04 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | System and method for controlling a power amplifier using a programmable ramp circuit |
| FR2964477B1 (en) * | 2010-09-08 | 2012-10-05 | St Microelectronics Grenoble 2 | REFERENCE VOLTAGE GENERATOR FOR POLARIZING AN AMPLIFIER |
-
2017
- 2017-02-10 CN CN201710073930.3A patent/CN106685461B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546958A (en) * | 2007-04-27 | 2014-01-29 | 瑞萨电子株式会社 | Transmitter, RF transmitter signal processor and method for operation of transmitter |
| CN205029811U (en) * | 2015-09-29 | 2016-02-10 | 深圳市万博鑫科技有限公司 | Duplexing intercom of digit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106685461A (en) | 2017-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI619328B (en) | Charging control method and charging system, power delivery unit, and power receiver control circuit using the method | |
| EP4235653A3 (en) | Electronic device and controlling method thereof | |
| CN104866067A (en) | Low power consumption control method and electronic device | |
| CN116389976B (en) | Method for improving external sound effect and related device | |
| US20210201894A1 (en) | N/a | |
| WO2023092782A1 (en) | Charging pile cooling method | |
| CN106125880A (en) | The method for controlling volume of a kind of intelligent terminal and device and storage medium | |
| EP4368458A3 (en) | Electrical power supply device and method of operating same | |
| WO2011116610A1 (en) | Method, system and device for initializing internet device | |
| CN106685461B (en) | Digital talkback terminal | |
| US20140195827A1 (en) | Electronic device with power control function | |
| CN101645697A (en) | System and method for controlling sound volume | |
| CN113096677B (en) | Intelligent noise reduction method and related equipment | |
| CN107155211A (en) | Adjusting method, device, mobile terminal and the storage medium of WiFi transmission powers | |
| CN105690407A (en) | Intelligent robot with expression display function | |
| CN204595492U (en) | Wireless instructions load voice controller | |
| CN206020961U (en) | Control circuit and electronic equipment | |
| KR20140006668A (en) | Hearing aid | |
| CN109582114A (en) | A kind of mobile terminal and its start-up control method | |
| CN206149367U (en) | Mobile phone motherboard with luminance and volume self -adaptation adjustment function | |
| CN116169758A (en) | Output power adjusting method and charger | |
| CN104331304A (en) | Standby waking-up method of external notebook computer of audio equipment | |
| CN205304747U (en) | Pronunciation collection system's automatic gain control ware control circuit | |
| Quinones | Applying acceleration and deceleration profiles to bipolar stepper motors | |
| EP4180917A3 (en) | Operating method for memory system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |