CN106611789B - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN106611789B CN106611789B CN201510702090.3A CN201510702090A CN106611789B CN 106611789 B CN106611789 B CN 106611789B CN 201510702090 A CN201510702090 A CN 201510702090A CN 106611789 B CN106611789 B CN 106611789B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
A kind of fin formula field effect transistor and forming method thereof, wherein method includes: offer semiconductor substrate, and the semiconductor substrate surface has fin；Semiconductor substrate surface in the fin two sides forms the first isolation structure, and the whole surface of first isolation structure is lower than the top surface of the fin；Ion is injected in first isolation structure, and the ion diffuses into the fin of the first isolation structure side, form channel barrier layer in the fin；After injecting ion, protective layer is formed in the top surface and side wall of fin；Using the protective layer as exposure mask, the first isolation structure of etched portions thickness, to expose the side wall on the channel barrier layer；After the side wall on the channel barrier layer exposed forms diffusion barrier layer, the protective layer is removed；After removing the protective layer, the second isolation structure for covering the diffusion barrier layer is formed on first isolation structure surface.The method improves the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of fin formula field effect transistor and forming method thereof.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source region and position positioned at the gate structure of semiconductor substrate surface, in the semiconductor substrate of gate structure side
Drain region in the semiconductor substrate of the gate structure other side.MOS transistor adjusts by applying voltage in grid and passes through grid knot
The electric current of structure bottom channel generates switching signal.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of side wall described in covering part are located at grid knot
Source region in the fin of structure side and the drain region in the fin of the gate structure other side.
The method for forming fin formula field effect transistor includes: offer semiconductor substrate, and the semiconductor substrate surface has
The fin and gate structure across the fin of protrusion, the top surface of fin described in the gate structure covering part and side
Wall；Side wall is formed in gate structure two sides side wall；It is carried out using side wall and gate structure as fin of the exposure mask to gate structure two sides
Ion implanting forms source region and the drain region of heavy doping.
However, the performance of the fin formula field effect transistor formed in the prior art is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of fin formula field effect transistor and forming method thereof, prevents channel barrier layer
In ion diffuse in the second isolation structure, to improve the performance of fin formula field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: offer is partly led
Body substrate, the semiconductor substrate surface have fin；Semiconductor substrate surface in the fin two sides forms the first isolation
Structure, the whole surface of first isolation structure are lower than the top surface of the fin；It is infused in first isolation structure
Enter ion, and the ion diffuses into the fin of the first isolation structure side, forms channel barrier layer in the fin；Injection
After ion, protective layer is formed in the top surface and side wall of fin；Using the protective layer as exposure mask, the first of etched portions thickness
Isolation structure, to expose the side wall on the channel barrier layer；Side wall on the channel barrier layer exposed forms diffusion
Behind barrier layer, the protective layer is removed；After removing the protective layer, is formed on first isolation structure surface and cover the expansion
Dissipate second isolation structure on barrier layer.
Optionally, the width of the diffusion barrier layer is 20 angstroms~40 angstroms.
Optionally, the technique for forming the diffusion barrier layer is selective epitaxial growth process or carbon ion implantation work
Skill.
Optionally, using selective epitaxial growth process formed diffusion barrier layer the step of are as follows: with the protective layer be hide
Block material, the sidewall growth diffusion barrier layer on the channel barrier layer exposed.
Optionally, the design parameter of the selective epitaxial growth process are as follows: the gas used is HCl, SiH3CH3With
SiH2Cl2, the flow of HCl is 80sccm~160sccm, SiH3CH3Flow be 60sccm~120sccm, SiH2Cl2Flow
For 400sccm~600sccm, chamber pressure is 500torr~700torr, and temperature is 600 degrees Celsius~850 degrees Celsius.
Optionally, when forming the diffusion barrier layer using selective epitaxial growth process, the diffusion barrier layer
Material is carbon silicon, and the atom percentage concentration of carbon is 0.5%~3% in the carbon silicon.
Optionally, the step of diffusion barrier layer being formed using carbon ion implantation technique are as follows: the channel resistance that Xiang Suoshu exposes
The sidewall surfaces of barrier inject carbon ion.
Optionally, the Implantation Energy of the carbon ion is 5KeV~20KeV, implantation dosage 1.0E14atom/cm2~
8.0E15atom/cm2, implant angle is 10 degree~20 degree.
Optionally, when forming the diffusion barrier layer using carbon ion implantation technique, the material of the diffusion barrier layer
For the silicon for adulterating carbon ion.
Optionally, the class of the type of the ion being injected into the first isolation structure and the fin formula field effect transistor
Type is opposite.
Optionally, the material of the protective layer is silicon nitride, carbonitride of silicium or silicon oxynitride.
The present invention also provides a kind of fin formula field effect transistors, comprising: semiconductor substrate；Fin is located at the semiconductor
Substrate surface；First isolation structure, the semiconductor substrate surface positioned at the fin two sides；Second isolation structure is located at described
First isolation structure surface, the top surface of the fin are higher than the surface of second isolation structure, it is described be higher than second every
Fin from body structure surface is as channel region；Channel barrier layer, in the fin below the channel region, and the channel hinders
The top surface of barrier is higher than the surface of the first isolation structure；Diffusion barrier layer is located at channel barrier layer side wall, and described
Second isolation structure covers the diffusion barrier layer.
Compared with prior art, technical solution of the present invention has the advantage that
(1) since the side wall on the channel barrier layer forms diffusion barrier layer, the diffusion barrier layer forms the ditch
The barrier of road barrier layer intermediate ion, the ion in the channel barrier layer cannot pass through diffusion barrier layer into the second isolation structure
In, so that the diffusion barrier layer can stop channel to stop during the subsequent progress high annealing to diffusion barrier layer
Ion in layer enters in the second isolation structure, to reduce the agent that the ion is needed when injecting in the first isolation structure
Amount thereby reduces the probability that the ion in the channel barrier layer to be formed enters in channel, reduces because the ion enters channel
Caused by difference fin channel described in ion distribution otherness, reduce the difference of the corresponding threshold voltage of different fins
The opposite sex, to improve the performance of fin formula field effect transistor.
(2) further, in the sidewall selectivity epitaxial growth carbon silicon for exposing the channel barrier layer, or to exposure
The side wall on channel barrier layer out injects carbon ion, since the atomic radius of the carbon ion is smaller, the carbon ion be easy into
Between the lattice for entering the interstitial void on channel barrier layer, and then the ion in channel barrier layer effectively being stopped to pass through channel barrier layer
Gap diffuses in the second isolation structure.
Detailed description of the invention
Fig. 1 to Fig. 3 is the structural schematic diagram of fin formula field effect transistor forming process in the prior art；
Fig. 4 to Figure 15 is the structural schematic diagram of fin formula field effect transistor forming process in first embodiment of the invention；
Figure 16 to Figure 21 is the structural schematic diagram of fin formula field effect transistor forming process in second embodiment of the invention.
Specific embodiment
As described in background, the performance for the fin formula field effect transistor that the prior art is formed is poor.
Fig. 1 to Fig. 3 is the structural schematic diagram of fin formula field effect transistor forming process in the prior art.
With reference to Fig. 1, semiconductor substrate 100 is provided, 100 surface of semiconductor substrate has fin 110；In the fin
100 surface of semiconductor substrate of 110 two sides forms isolation structure 120, and the whole surface of the isolation structure 120 is lower than the fin
The top surface in portion 110.The top surface of the fin 110 has mask layer 111.
With reference to Fig. 2, ion is injected in the isolation structure 120, and the ion is made to diffuse into isolation structure side
In the fin 110 in portion, channel barrier layer 130 is formed in fin 110.
With reference to Fig. 3, the ion in the channel barrier layer 130 is made annealing treatment, to activate the ion.
The study found that the poor reason of the performance of the fin formula field effect transistor formed in the prior art is:
During being made annealing treatment to the ion in the channel barrier layer, since the ion is in isolation structure
In solid solubility be greater than the solid solubility of the ion in the fin, so the ion is easy in annealing process to the isolation
It is spread in structure, to reduce the concentration of channel barrier layer intermediate ion, in order to enable preceding described with annealing after annealing
The concentration of channel barrier layer intermediate ion is almost the same, needs to increase the dosage that ion is injected in the isolation structure, so that
Foregoing description channel barrier layer intermediate ion concentration of annealing is higher than the channel barrier layer intermediate ion concentration after annealing, due to moving back
Fiery foregoing description channel barrier layer intermediate ion concentration is higher, and the probability for causing the ion to enter channel increases, and leads to different fins
The otherness of ion distribution described in the channel in portion increases, and then the otherness of threshold voltage in different fins is caused to increase, from
And reduce the performance of fin formula field effect transistor.
On this basis, one embodiment of the invention provides a kind of forming method of fin formula field effect transistor, by fin
Channel barrier layer side wall in portion forms diffusion barrier layer, and the ion in the channel barrier layer is stopped to diffuse into the second isolation
In structure, to reduce ion dosage for needing in injection, thereby reduce the ion enter it is several in channel
Rate reduces the otherness of threshold voltage in different fins.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
First embodiment
Fig. 4 to Figure 15 is the structural schematic diagram of fin formula field effect transistor forming process in first embodiment of the invention.
With reference to Fig. 4, semiconductor lining 200 is provided, 200 surface of semiconductor substrate has fin 210.
The semiconductor substrate 200 provides technique platform to be subsequently formed fin formula field effect transistor.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe, GaAs；The semiconductor substrate 200 can also be other semiconductor materials, here no longer
It illustrates one by one.In the present embodiment, the material of the semiconductor substrate 200 is silicon.
Doped with P-type ion forming p-well region in the semiconductor substrate 200, or doped with N-type ion to shape
At N well region.
The width W of the fin 210 is 8nm~20nm, the width W refer to perpendicular to 210 extending direction of fin and
The size being directed toward on 210 direction of fin, when the number of the fin 210 is multiple, the distance between adjacent fin 210 is
20nm~50nm.
The step of forming fin 210 are as follows: patterned mask layer 211 is formed on 200 surface of semiconductor substrate, it is described
Patterned mask layer 211 defines the position of fin 210；With the patterned mask layer 211 for mask etching segment thickness
Semiconductor substrate 200, formed fin 210.
It should be noted that after forming fin 210, not removing the mask layer for defining 210 position of fin in the present embodiment
211, retain the mask layer 211 in 210 top surface of fin, mask layer 211 can protect the top table of the fin 210
Face.In other embodiments, after forming fin 210, the mask layer 211 for defining 210 position of fin can be removed.
In the present embodiment, further includes: after forming fin 210, form the boundary layer of covering fin 210 top surface and side wall
(not shown), the boundary layer is repairing etching injury caused by during forming fin 210, and is blocked in subsequent in shape
Enter in fin 210 at the intermediate product (such as aqueous vapor, oxygen) generated during the first isolation structure.In one embodiment,
The material of the boundary layer is silica, and in other embodiments, the material of the boundary layer can be other materials.Form institute
The technique for stating boundary layer is liner oxidation technique.The boundary layer with a thickness of 10 angstroms~50 angstroms.
With reference to Fig. 5, the first isolation structure 220 is formed on 200 surface of semiconductor substrate of 210 two sides of fin, it is described
The whole surface of first isolation structure 220 is lower than the top surface of the fin 210.
The effect of first isolation structure 220 are as follows: it is subsequent to inject ion in the first isolation structure 220, and make institute
It states ion to diffuse into the fin 210 of 220 side of the first isolation structure, thus the fin in 220 side of the first isolation structure
Doped with ion in 210, to form channel barrier layer.
The step of forming the first isolation structure 220 are as follows: form covering semiconductor substrate 200, fin 210 and mask layer 211
The first isolation structure material layer (not shown), the whole surface of the first isolation structure material layer is higher than the fin 210
Top surface；The first isolation structure material layer is planarized using flatening process until exposing the table of mask layer 211
Face；After planarizing the first isolation structure material layer, be etched back to removal the first isolation structure of part material layer, formed first every
From structure 220.
The technique for forming the first isolation structure material layer is depositing operation, such as plasma activated chemical vapour deposition technique or low
Pressure chemical vapor deposition technique, fluid chemistry vapor deposition (FCVD) technique.The technique for planarizing the first isolation structure material layer
For chemical mechanical milling tech；The technique for being etched back to the first isolation structure material layer is anisotropy dry carving technology.
The material of first isolation structure 220 is silica, silicon oxynitride or silicon oxide carbide, and described first is isolated
The material of structure 220 is different with the material for the protective layer being subsequently formed.In the present embodiment, the material of the first isolation structure 220 is
Silica.
The height of first isolation structure 220 is 650 angstroms~1300 angstroms.The height refers to serving as a contrast perpendicular to semiconductor
Size in 200 surface direction of bottom.
With reference to Fig. 6, inject ion in first isolation structure 220, and make the ion diffuse into first every
In fin 210 from 220 side of structure.
After injecting ion in the first isolation structure 220, the ion forms peak concentration in the first isolation structure 220
Region, the peak concentration region refers to concentration highest region of the ion in the first isolation structure 220, described
The phenomenon that ion is presented Gaussian Profile centered on the peak concentration region, the Gaussian Profile is since the ion is being infused
Caused by being spread during entering the first isolation structure 220, using the ion during injecting the first isolation structure 220
Diffusion, so that the ion enters in the fin 210 of 220 side of the first isolation structure.
Due to the width dimensions very little of fin 210, after injecting ion in first isolation structure 220, the ion
Can be from the fin 210 that the first isolation structure 220 diffuses into 220 side of the first isolation structure, and the ion is in fin
210 width direction is distributed, to form channel barrier layer 230 in fin 210.It should be noted that the ion
It is diffused mainly along the direction perpendicular to 210 extending direction of fin and direction fin 210.
In the present embodiment, thickness of the ion implanting to depth and channel barrier layer 230 in the first isolation structure 220
Unanimously.In actual technique, since the ion is in addition to along perpendicular to fin 210 extending direction and being directed toward fin 210
Direction is diffused, and is also diffused into fin 210 from other directions, therefore the thickness on channel barrier layer 230 is greater than ion implanting
To the depth in the first isolation structure 220.
In the present embodiment, the channel barrier layer 230 of formation with a thickness of 40 angstroms~200 angstroms, the channel barrier layer 230
Thickness refers to the size perpendicular to 200 surface direction of semiconductor substrate.
The type for being injected into the ion in the first isolation structure 220 is opposite with the type of the fin formula field effect transistor.
When the fin formula field effect transistor of formation is N-type fin formula field effect transistor, the ion that is injected into the first isolation structure 220
For P-type ion, including B or In；When the fin formula field effect transistor of formation is p-type fin formula field effect transistor, it is injected into the
Ion in one isolation structure 220 is N-type ion, P (phosphorus) or As.
In one embodiment, fin formula field effect transistor to be formed is p-type fin formula field effect transistor, the ion
For As ion, Implantation Energy range is 20KeV~50KeV, and implantation dosage range is 1.0E12atom/cm2~1.0E14atom/
cm2, implant angle is 0 degree.The implant angle is the angle between 200 normal direction of semiconductor substrate.
In another embodiment, fin formula field effect transistor to be formed be N-type fin formula field effect transistor, it is described from
Son is B ion, and Implantation Energy range is 5KeV~10KeV, and implantation dosage range is 1.0E12atom/cm2~1.0E14atom/
cm2, implant angle is 0 degree.The implant angle is the angle between 200 normal direction of semiconductor substrate.
In the present embodiment, during injecting the ion, since the top surface of fin 210 has mask layer 211,
So will not be injected into fin 210 from the top surface of fin 210, avoid the threshold voltage of fin formula field effect transistor by
It influences.
With reference to Fig. 7, after injecting the ion, protective layer is formed in the top surface and side wall of fin 210.
For the convenience of description, the protective layer is divided into: the first protective layer, the fin 210 after injecting the ion
Top surface；Second protective layer, the side wall of the fin 210 after injecting the ion.
The material of the protective layer is silicon nitride, silicon oxynitride or fire sand.In the present embodiment, the material of the protective layer
Material is silicon nitride.
In the present embodiment, due to not having to remove mask layer 211, the mask layer 211 is used as the first protective layer, meanwhile,
The side wall of the fin 210 after injecting ion is only needed to form the second protective layer 240.In other embodiments, in injection ion
The top surface and side wall of fin 210 afterwards form protective layer, and the protective layer can cover the mask layer 211.
In the present embodiment, formed the second protective layer 240 the step of are as follows: formed covering the first isolation structure 220, fin 210
With the second protected material bed of material (not shown) of mask layer 211；Second protection materials are etched using anisotropy dry carving technology
Layer forms the second protective layer 240 up to exposing the surface of the first isolation structure 220 and the surface of mask layer 211.
With reference to Fig. 8, using the protective layer as exposure mask, the first isolation structure 220 of etched portions thickness is described to expose
The side wall on channel barrier layer 230.
The technique for etching first isolation structure 220 is dry carving technology or wet-etching technique.In the present embodiment, using dry etching
Technique etches the first isolation structure 220.
In the present embodiment, the thickness of the first isolation structure 220 of the etching is equal to the thickness on the channel barrier layer 230；
In other embodiments, the thickness for etching the first isolation structure 220 can be greater than the thickness on the channel barrier layer 230.
With reference to Fig. 9, the side wall on the channel barrier layer 230 exposed forms diffusion barrier layer 250.
In the present embodiment, diffusion barrier layer 250, specific step are as follows: with institute are formed using selective epitaxial growth process
Stating protective layer is shelter, the sidewall growth diffusion barrier layer 250 on the channel barrier layer 230 exposed.
The diffusion barrier layer 250 of formation is located at the side wall on channel barrier layer 230 and covers the side wall on channel barrier layer 230,
And the diffusion barrier layer 250 is located at outside fin 210.
In the present embodiment, the material for the diffusion barrier layer 250 for using selective epitaxial growth process to be formed is carbon silicon, if institute
The atomic mass percent concentration of carbon atom in diffusion barrier layer 250 is stated lower than 0.5%, cause in channel barrier layer 230 from
The blocking capability of son diffusion reduces；If the atomic mass percent concentration of carbon atom is more than 3% in the diffusion barrier layer 250,
The difficulty for increasing process costs, and realizing in technique is caused to increase.Therefore in the present embodiment, carbon in the diffusion barrier layer 250
The atomic mass percent concentration of atom is 0.5%~3%.
The width of the diffusion barrier layer 250 needs to select suitable range, and the width is referred to perpendicular to fin 210
Extending direction and the size being directed toward on 210 direction of fin.If the width of the diffusion barrier layer 250 is too small, to channel barrier layer
The blocking capability of 230 intermediate ions diffusion reduces, if the width of the diffusion barrier layer 250 is larger, increases process costs, and make
It obtains too small positioned at the distance between adjacent diffusion barrier layer 250 of adjacent fin 210 and makes the adjacent diffusion barrier layer 250
It is readily attached together.Therefore in the present embodiment, select the width of diffusion barrier layer 250 for 20 angstroms~40 angstroms.
In the present embodiment, the technique for forming the diffusion barrier layer 250 is selective epitaxial growth process, the gas of use
For HCl, SiH3CH3And SiH2Cl2, the flow of HCl is 80sccm~160sccm, SiH3CH3Flow be 60sccm~
120sccm, SiH2Cl2Flow be 400sccm~600sccm, chamber pressure is 500torr~700torr, and temperature is 600 to take the photograph
Family name degree~850 degree Celsius.
If the chamber pressure that the selective epitaxial growth process uses is more than 700torr, the diffusion to be formed resistance will lead to
The uniformity of barrier 250 is deteriorated；If the chamber pressure that the selective epitaxial growth process uses is less than 500torr, will lead to
The speed of growth is excessively slow.Therefore in the present embodiment, chamber pressure that the selective epitaxial growth process uses for 500torr~
700torr。
If the temperature that the selective epitaxial growth process uses is more than 850 degrees Celsius, the diffusion barrier layer resulted in
250 film quality decline, is easy to happen cracking, weakens to the blocking capability of 230 intermediate ion of channel barrier layer diffusion；If
The temperature that the selective epitaxial growth process uses is less than 600 degrees Celsius, the defects of diffusion barrier layer 250 resulted in
It is more, and the concentration of the carbon atom in diffusion barrier layer 250 can reduce, the resistance to 230 intermediate ion of channel barrier layer diffusion
Keep off reduced capability.Therefore in the present embodiment, the temperature that the selective epitaxial growth process uses is Celsius for 600 degrees Celsius~850
Degree.
In this implementation, the diffusion barrier layer 250 is subsequently formed to stop channel barrier layer 230 intermediate ion to diffuse to
In second isolation structure, principle are as follows: on the one hand, part carbon atom is located at diffusion barrier layer 250 in the diffusion barrier layer 250
Interstitial void in, on the other hand, the part carbon atom in the diffusion barrier layer 250 diffuses into channel barrier layer 230
In interstitial void, so that the ion in channel barrier layer 230 be avoided to enter subsequent shape by the interstitial void of diffusion barrier layer 250
At the second isolation structure.
The protective layer is removed after forming diffusion barrier layer 250 with reference to Figure 10.
The technique for removing the protective layer is dry carving technology or wet-etching technique.In the present embodiment, the protective layer is removed
Technique is wet-etching technique, and for the solution used for phosphoric acid solution, the concentration of phosphoric acid is 90%~100%, temperature is 150 degrees Celsius~
180 degrees Celsius.
In the present embodiment, also the mask layer 211 is removed while removing the protective layer, saves technique step
Suddenly；In other embodiments, the mask layer 211 can be removed after being subsequently formed the second isolation structure.
With reference to Figure 11, after removing the protective layer, is formed and cover 210 top surface of fin and side wall and diffusion
The second isolation structure material layer 260 on barrier layer 250 and the first isolation structure 220.
The material of the second isolation structure material layer 260 is silicon oxide or silicon nitride.
The technique 260 for forming the second isolation structure material layer is depositing operation, such as plasma activated chemical vapour deposition
Technique, atom layer deposition process or low-pressure chemical vapor deposition process.
With reference to Figure 12, the sacrificial material layer 270 of the second isolation structure material layer 260 of covering, the sacrificial material layer are formed
270 whole surface is higher than the top surface of fin 210.
In the present embodiment, the material of the sacrificial material layer 270 is DUO (Light Absorbing Oxide), and DUO is
Gamma-amino propyl-triethoxysilicane oxygen alkane (APTEOS), NH4OH and HNO3Mixture.
The technique for forming the sacrificial material layer 270 are as follows: it is coated with DUO on 260 surface of the second isolation structure material layer, it is described
The whole surface of DUO is higher than the top surface of fin 210, since DUO is fluid state at normal temperature, therefore the table for the DUO being coated with
The flat DUO of the step of face flushes everywhere, saves flatening process, then solidifies DUO.
With reference to Figure 13, after solidifying the sacrificial material layer 270, it is etched back to the removal part sacrificial material layer 270, is formed
Sacrificial layer 271.
The technique for being etched back to the sacrificial material layer 270 is anisotropy dry carving technology.
The sacrificial layer 271 is located parallel to the table of the second isolation structure material layer 260 on 200 surface of semiconductor substrate
Face, the surface of the sacrificial layer 271 are lower than the top surface of the fin 210.
The sacrificial layer 271 with a thickness of 100 angstroms~300 angstroms.
In the present embodiment, the effect of the sacrificial layer 271 are as follows: cover be parallel to the second of 200 surface of semiconductor substrate every
The side wall on surface and the second isolation structure of covering part material layer 260 from structural material 260.
It is exposure mask with the sacrificial layer 271 with reference to Figure 14, etches the second of 210 top of removal fin using dry carving technology
Side wall is not sacrificed the covering of layer 271 in second isolation structure material layer 260 of 210 side wall of isolation structure material layer 260 and fin
Part, to form the second isolation structure 261 for covering the diffusion barrier layer 250 on 220 surface of the first isolation structure.
With reference to Figure 15, after forming the second isolation structure 261, remove the sacrificial layer 271 (with reference to Figure 14).
The technique for removing the sacrificial layer 271 is dry carving technology or wet-etching technique.
After forming the second isolation structure 261, channel barrier layer 230 is made annealing treatment, to activate channel barrier layer 230
In ion, and the lattice for having repaired the channel barrier layer 230 due to caused by injecting the ion on channel barrier layer 230 is abnormal
Become.
During being made annealing treatment to channel barrier layer 230, due to the side wall shape on the channel barrier layer 230
At there is diffusion barrier layer 250, the diffusion barrier layer 250 forms the barrier of 230 intermediate ion of channel barrier layer, so that described
Ion in channel barrier layer 230 cannot pass through diffusion barrier layer 250 and enter in the second isolation structure 261, to reduce institute
State ion dosage for needing when injecting in the first isolation structure 220, thereby reduce in the channel barrier layer 230 to be formed from
Son enters the probability in channel, reduces the ion described in the channel of different fins 210 because caused by the ion enters channel
The otherness of distribution, reduces the otherness of the corresponding threshold voltage of different fins 210, to improve fin field effect crystal
The performance of pipe.
In the present embodiment, the fin formula field effect transistor of formation, with reference to Figure 15, comprising: semiconductor substrate 200；Fin
210, it is located at 200 surface of semiconductor substrate；First isolation structure 220, the semiconductor substrate positioned at 210 two sides of fin
200 surfaces；Second isolation structure 261, is located at 220 surface of the first isolation structure, and the top surface of the fin 210 is higher than
The surface of second isolation structure 261, the fin 210 for being higher than 261 surface of the second isolation structure are used as channel region；Channel
Barrier layer 230, in the fin 210 below the channel region, and the top surface on the channel barrier layer 230 is higher than first
The surface of isolation structure 220；Diffusion barrier layer 250 is located at 230 side wall of channel barrier layer, and second isolation structure
The 261 covering diffusion barrier layers 250.
The diffusion barrier layer 250 is located at 210 surface of fin outside 230 side wall of channel barrier layer.
Second embodiment
Figure 16 to Figure 21 is the structural schematic diagram of fin formula field effect transistor forming process in second embodiment of the invention.
The difference of second embodiment and first embodiment is: being stopped using carbon ion implantation technique in the channel exposed
The side wall of layer injects carbon ion, and the side wall on channel barrier layer forms diffusion barrier layer, and the diffusion barrier layer is located at fin
It is interior.About part identical with first embodiment in second embodiment, no longer it is described in detail.
With reference to Figure 16, Figure 16 is the schematic diagram formed on the basis of Fig. 8, on the channel barrier layer 230 exposed
Side wall forms diffusion barrier layer 350.
In the present embodiment, using carbon ion implantation technique formed diffusion barrier layer 350 the step of are as follows: in the channel exposed
The sidewall surfaces on barrier layer 230 inject carbon ion, and the side wall on the channel barrier layer 230 exposed forms diffusion barrier layer
350, and the diffusion barrier layer 350 is located in fin 210.
In the present embodiment, the material for the diffusion barrier layer 350 for using carbon ion implantation technique to be formed is doping carbon ion
Silicon.
If the Implantation Energy of the carbon ion is excessive, protective layer can be passed through and be injected into the fin 210 of protective layer covering,
Influence the threshold voltage of fin formula field effect transistor；If the Implantation Energy of the carbon ion is too small, be injected into expose it is described
The depth of the side wall on channel barrier layer 230 is smaller, poor to the blocking capability of 230 intermediate ion of channel barrier layer diffusion.Therefore this implementation
In example, the Implantation Energy of the carbon ion is 5KeV~20KeV.
The carbon ion needs to select suitable implant angle, and the implant angle refers to and 200 method of semiconductor substrate
Angle between line.If the implant angle of the carbon ion is too small, from channel barrier layer, 230 side wall is injected into channel barrier layer
230 depth is too small, and 230 intermediate ion of channel barrier layer cannot effectively be stopped to spread；If the injector angle of the carbon ion is spent
Greatly, the injection direction will receive the blocking of adjacent fin 210, cause to be injected into channel barrier layer 230.Therefore this implementation
In example, the implant angle of the carbon ion is 10 degree~20 degree.
If the implantation dosage of the carbon ion is too small, carbon ion is caused to enter the atom of 230 interstitial void of channel barrier layer
It is very few, the blocking capability of 230 intermediate ion of channel barrier layer diffusion is reduced；If the implantation dosage of the carbon ion is excessive, cause
The difficulty for increasing process costs, and realizing in technique increases.Therefore in the present embodiment, the implantation dosage of the carbon ion is
1.0E14atom/cm2~8.0E15atom/cm2。
In the present embodiment, the diffusion barrier layer 350 is subsequently formed for stopping 230 intermediate ion of channel barrier layer to diffuse to
The second isolation structure in, principle are as follows: it is brilliant to occupy channel barrier layer 230 into channel barrier layer 230 for the carbon ion implantation
The position of compartment gap, so that it is subsequent to stop the ion in channel barrier layer 230 to diffuse to from the interstitial void on channel barrier layer 230
In the second isolation structure formed.
The protective layer is removed after forming diffusion barrier layer 350 with reference to Figure 17.
The method of the protective layer is removed referring to the method for removing protective layer in first embodiment, is no longer described in detail.
With reference to Figure 18, after removing the protective layer, is formed and cover 210 top surface of fin and side wall and diffusion
The second isolation structure material layer 360 on barrier layer 350 and the first isolation structure 220.
The method of the second isolation structure material layer 360 is formed referring to forming the second isolation structure material in first embodiment
The method of the bed of material 260, is no longer described in detail.
With reference to Figure 19, is formed and sacrificed on 360 surface of the second isolation structure material layer for being parallel to 200 surface of semiconductor substrate
Layer 371.
The method of the sacrificial layer 371 is formed referring to the method for forming sacrificial layer 271 in first embodiment, is no longer described in detail.
It is exposure mask with the sacrificial layer 371 with reference to Figure 20, the second isolation structure material layer at 210 top of removal fin
360 and 210 side wall of fin the second isolation structure material layer 360 in side wall be not sacrificed layer 371 covering part, thus
First isolation structure, 220 surface forms the second isolation structure 361 for covering the diffusion barrier layer 350.
The method of the second isolation structure 361 is formed referring to the method for forming the second isolation structure 261 in first embodiment.
With reference to Figure 21, after forming the second isolation structure 361, remove the sacrificial layer 371 (with reference to Figure 20).
The method of sacrificial layer 371 is removed referring to the method for removing sacrificial layer 271 in first embodiment, is no longer described in detail.
After forming the second isolation structure 361, channel barrier layer 230 is made annealing treatment, to activate channel barrier layer 230
In ion, and the lattice for having repaired the channel barrier layer 230 due to caused by injecting the ion on channel barrier layer 230 is abnormal
Become.
In the present embodiment, during being made annealing treatment to channel barrier layer 230, repair due to carbon ion implantation
The distortion of lattice of diffusion barrier layer 350 caused by and.
During being made annealing treatment to channel barrier layer 230, due to the side wall shape on the channel barrier layer 230
At there is diffusion barrier layer 350, the diffusion barrier layer 350 forms the barrier of 230 intermediate ion of channel barrier layer, so that described
Ion in channel barrier layer 230 cannot pass through diffusion barrier layer 350 and enter in the second isolation structure 361, to reduce institute
State ion dosage for needing when injecting in the first isolation structure 220, thereby reduce in the channel barrier layer 230 to be formed from
Son enters the probability in channel, reduces the ion described in the channel of different fins 210 because caused by the ion enters channel
The otherness of distribution, reduces the otherness of the corresponding threshold voltage of different fins 210, to improve fin field effect crystal
The performance of pipe.
In the present embodiment, the fin formula field effect transistor of formation, with reference to Figure 21, comprising: semiconductor substrate 200；Fin
210, it is located at 200 surface of semiconductor substrate；First isolation structure 220, the semiconductor substrate positioned at 210 two sides of fin
200 surfaces；Second isolation structure 361, is located at 220 surface of the first isolation structure, and the top surface of the fin 210 is higher than
The surface of second isolation structure 361, the fin 210 for being higher than 361 surface of the second isolation structure are used as channel region；Channel
Barrier layer 230, in the fin 210 below the channel region, and the top surface on the channel barrier layer 230 is higher than first
The surface of isolation structure 220；Diffusion barrier layer 350 is located at 230 side wall of channel barrier layer, and second isolation structure
The 361 covering diffusion barrier layers 350.
The diffusion barrier layer 350 is located in fin 210.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate surface has fin；
Semiconductor substrate surface in the fin two sides forms the first isolation structure, the whole surface of first isolation structure
Lower than the top surface of the fin；
Ion is injected in first isolation structure, and the ion diffuses into the fin of the first isolation structure side,
Channel barrier layer is formed in the fin；
After injecting ion, protective layer is formed in the top surface and side wall of fin；
Using the protective layer as exposure mask, the first isolation structure of etched portions thickness, to expose the side on the channel barrier layer
Wall；
After the side wall on the channel barrier layer exposed forms diffusion barrier layer, the protective layer is removed；
After removing the protective layer, the second isolation junction for covering the diffusion barrier layer is formed on first isolation structure surface
Structure.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that for channel barrier layer
Unilateral diffusion barrier layer, the width of the diffusion barrier layer are 20 angstroms~40 angstroms.
3. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that form the diffusion resistance
The technique of barrier is selective epitaxial growth process or carbon ion implantation technique.
4. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that use selective epitaxial
Growth technique forms the step of diffusion barrier layer are as follows: using the protective layer as shelter, on the channel barrier layer exposed
Sidewall growth diffusion barrier layer.
5. the forming method of fin formula field effect transistor according to claim 4, which is characterized in that the selective epitaxial
The design parameter of growth technique are as follows: the gas used is HCl, SiH3CH3And SiH2Cl2, the flow of HCl be 80sccm~
160sccm, SiH3CH3Flow be 60sccm~120sccm, SiH2Cl2Flow be 400sccm~600sccm, chamber pressure
It is by force 500torr~700torr, temperature is 600 degrees Celsius~850 degrees Celsius.
6. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that when outer using selectivity
When growth process forms the diffusion barrier layer, the material of the diffusion barrier layer is carbon silicon, the atom of carbon in the carbon silicon
Percent concentration is 0.5%~3%.
7. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that use carbon ion implantation
Technique forms the step of diffusion barrier layer are as follows: the sidewall surfaces on the channel barrier layer that Xiang Suoshu exposes inject carbon ion.
8. the forming method of fin formula field effect transistor according to claim 7, which is characterized in that the note of the carbon ion
Entering energy is 5KeV~20KeV, implantation dosage 1.0E14atom/cm2~8.0E15atom/cm2, implant angle be 10 degree~
20 degree.
9. the forming method of fin formula field effect transistor according to claim 3, which is characterized in that infused when using carbon ion
When entering technique and forming the diffusion barrier layer, the material of the diffusion barrier layer is the silicon for adulterating carbon ion.
10. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that described to be injected into
The type of ion in one isolation structure is opposite with the type of the fin formula field effect transistor.
11. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the protective layer
Material is silicon nitride, carbonitride of silicium or silicon oxynitride.
12. the fin formula field effect transistor formed according to claim 1 to any one of 11, comprising:
Semiconductor substrate；
Fin is located at the semiconductor substrate surface；
First isolation structure, the semiconductor substrate surface positioned at the fin two sides；
Second isolation structure, is located at first isolation structure surface, and the top surface of the fin is higher than second isolation
The surface of structure, the fin for being higher than the second isolation structure surface is as channel region；
It is characterized by further comprising:
Channel barrier layer, in the fin below the channel region, and the top surface on the channel barrier layer is higher than first
The surface of isolation structure；
Diffusion barrier layer is located at channel barrier layer side wall, and second isolation structure covers the diffusion barrier layer.
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