CN106602215A - Method for preparing SiGe-based plasma pin diode for reconstructing holographic antennas - Google Patents
Method for preparing SiGe-based plasma pin diode for reconstructing holographic antennas Download PDFInfo
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- CN106602215A CN106602215A CN201611185622.1A CN201611185622A CN106602215A CN 106602215 A CN106602215 A CN 106602215A CN 201611185622 A CN201611185622 A CN 201611185622A CN 106602215 A CN106602215 A CN 106602215A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000002360 preparation method Methods 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 85
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 57
- 239000007787 solid Substances 0.000 claims description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 30
- 239000000377 silicon dioxide Substances 0.000 claims description 28
- 238000001259 photo etching Methods 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 13
- 238000011049 filling Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract 3
- 210000002381 plasma Anatomy 0.000 description 85
- 150000002500 ions Chemical class 0.000 description 20
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001093 holography Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036470 plasma concentration Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000011514 reflex Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q5/00—Arrangements for simultaneous operation of antennas on two or more different wavebands, e.g. dual-band or multi-band arrangements
- H01Q5/30—Arrangements for providing operation on different wavebands
- H01Q5/307—Individual or coupled radiating elements, each element being fed in an unspecified way
- H01Q5/314—Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors
- H01Q5/321—Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors within a radiating element or between connected radiating elements
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention relates to a method for preparing SiGe-based plasma pin diode for reconstructing holographic antennas. The method comprises: selecting a SiGeOI substrate of a crystal orientation; arranging an isolation region on the SiGeOI substrate; etching the substrate to form a P-type groove and an N-type groove wherein the depths of the P-type groove and the N-type groove are smaller than the thickness at the top SiGe layer of the substrate; forming a first P-type active region and a first N-type active region in the P-type groove and the N-type groove by ion implantation; filling the P-type groove and the N-type groove; forming a second P-type active region and a second N-type active region in the top SiGe layer of the substrate by ion implantation; and forming lead wires on the substrate to complete the preparation of the SiGe-based plasma pin diode. The embodiments of the present invention are capable of preparing and providing a high performance SiGe-based plasma pin diode suitable for forming a solid-state plasma antenna using a deep trench isolation technique and an ion implantation process.
Description
Technical field
The present invention relates to semiconductor device processing technology field, more particularly to a kind of SiGe for restructural holographic antenna
The preparation method of base plasma pin diodes.
Background technology
Holographic antenna is made up of source antenna and holographic structure.With reference to actual demand, appropriate antenna is selected as source antenna,
Change the radiation of feed by loading holographic structure, with the radiation characteristic of the target antenna needed for obtaining, by the electricity for giving
The interference pattern of electromagnetic wave radiation further calculates antenna structure.Compared with traditional reflector antenna, holographic structure has flexible structure
Form is built, is easy to and applied environment Integral design, be of wide application general.
Wireless communication system requires that antenna can change its electrical characteristics according to practical service environment, that is, realize antenna performance
" restructural ".Reconfigurable antenna has the function of multiple antennas, reduces the quantity of antenna in system.Plasma antenna is one
The radio-frequency antenna that plasma is oriented to medium as electromagnetic radiation is planted, it can change antenna by changing plasma density
Instant bandwidth, and with big dynamic range；Can also be by changing plasma resonance, impedance and density etc., adjustment
The frequency of antenna, beam angle, power, gain and directionality dynamic parameter, greatly cause the pass of domestic and international researcher
Note, becomes the focus of antenna research field.
At present, domestic and international application is in the material that the solid plasma pin diode of plasma reconfigurable antenna is adopted
Body silicon materials, this material has that intrinsic region carrier mobility is relatively low, affects pin diodes intrinsic region carrier concentration,
And then affect its solid plasma bulk concentration；And the P areas of the structure and N areas are formed using injection technology mostly, the method will
Ask implantation dosage and energy larger, it is high to equipment requirement and incompatible with existing process；And adopt diffusion technique, though junction depth compared with
It is deep, but while P areas are larger with the area in N areas, integrated level is low, and doping content is uneven, the electric property of impact pin diodes,
Cause the poor controllability of solid plasma bulk concentration and distribution.
Therefore, it is complete to be applied to solid plasma to make a kind of plasma pin diodes to select which kind of material and technique
Breath antenna just becomes particularly important.
The content of the invention
Therefore, it is to solve technological deficiency and the deficiency that prior art is present, the present invention proposes a kind of holographic for restructural
The preparation method of the SiGe base plasma pin diodes of antenna.
Specifically, the embodiment of the present invention proposes a kind of SiGe base plasma pin diodes for restructural holographic antenna
Preparation method, the SiGe bases plasma pin diodes be used for make restructural holographic antenna, the restructural holographic antenna
Including：SiGeOI semiconductor chips (1)；Be produced on first antenna arm (2) on the SiGeOI semiconductor chips (1), second
Antenna arm (3), coaxial feeder (4) and holographic annulus (14)；Wherein, the first antenna arm (2) and second antenna arm (3)
Including being distributed in the coaxial feeder (4) both sides and isometric SiGe base plasma pin diode strings, the holographic annulus (14)
Including multiple SiGe bases plasmas pin diode strings (w7)；The preparation method includes step：
A () chooses the SiGeOI substrates of a certain crystal orientation, on SiGeOI substrates isolated area is arranged；
B () forms the second protective layer in the substrate surface；Is formed on second protective layer using photoetching process
Two isolated area figures；Protected using specified location etching described second of the dry etch process in the second isolated area figure
Layer and the substrate are forming p-type groove and N-type groove；
C () forms the first p-type active area and the first N-type in the p-type groove and the N-type groove using ion implanting
Active area；
D () fills the p-type groove and the N-type groove, and using ion implanting in top layer Si Ge of the substrate
Form the second p-type active area and the second N-type active area；
E () generates over the substrate silica, the impurity in active area is activated using annealing process, in the p-type
, to form lead, Passivation Treatment and photoetching PAD are forming the plasma for contact zone and N-type contact zone lithography fair lead
Pin diodes.
On the basis of above-described embodiment, isolated area is set on SiGeOI substrates, including：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the substrate are to form isolation channel, and the depth of the isolation channel is more than or equal to the thickness of top layer Si Ge of the substrate；
(a4) fill the isolation channel to form the isolated area of the plasma pin diodes.
On the basis of above-described embodiment, first protective layer includes the first silicon dioxide layer and the first silicon nitride layer；
Correspondingly, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
On the basis of above-described embodiment, second protective layer includes the second silicon dioxide layer and the second silicon nitride layer；
Correspondingly, it is described to include in the substrate surface the second protective layer of formation：
(b1) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b2) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
On the basis of above-described embodiment, step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall shape of the p-type groove and the N-type groove
Into oxide layer；
(c2) using wet-etching technology the oxide layer of the p-type groove and the N-type trench wall is etched to complete
State the planarizing of p-type groove and the N-type trench wall；
(c3) the p-type groove and the N-type groove are carried out ion implanting to form the first p-type active area and institute
The first N-type active area is stated, the first N-type active area is away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron, the first p-type active area is away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron.
On the basis of above-described embodiment, step (c3) includes：
(c31) p-type groove described in photoetching and the N-type groove；
(c32) p type impurity is injected separately into the p-type groove and the N-type groove using the method with glue ion implanting
With N-type impurity forming the first p-type active area and the first N-type active area；
(c33) photoresist is removed.
On the basis of above-described embodiment, step (d) includes：
(d1) the p-type groove and the N-type groove are filled using polysilicon；
(d2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type ditch
Groove position is injected separately into p type impurity and N-type impurity to form the second p-type active area and the second N-type active area and while shape
Into p-type contact zone and N-type contact zone；
(d4) photoresist is removed；
(d5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
On the basis of above-described embodiment, the holographic annulus (14) is formed by eight sections of isometric SiGe base plasma pin diode arrangements
Octagon structure, wherein, the length of side of the octagon is long with the first antenna arm (2) and second antenna arm (3)
Degree sum is identical.
On the basis of above-described embodiment, the restructural holographic antenna is also semiconductor-based including the SiGeOI is made in
The direct current biasing line (5,6,7,8,9,10,11,12) of piece (1)；Direct current biasing line (5,6,7,8,9,10, the 11,12) interval
Property is electrically connected to SiGe bases plasma pin diode string (w1, w2, w3, w4, the w5, w6) two ends, and adopts chemical gaseous phase
The method of deposit is made on the SiGeOI semiconductor chips (1), and its material is copper, aluminium or passes through in the polysilicon for adulterating
Any one, wherein, the first antenna arm (2) includes solid plasma pin diode string (w1, w2, w3), described second day
Line arm (3) includes solid plasma pin diode string (w4, w5, w6).
On the basis of above-described embodiment, the SiGe bases plasma pin diodes include P+ areas (27), N+ areas (26) and
Intrinsic region (22), and also include the first metal contact zone (23) and the second metal contact zone (24)；Wherein, first metal connects
Tactile area (23) is electrically connected the P+ areas (27) and positive voltage, and the second metal contact zone (24) is electrically connected the N+
Area (26) and negative voltage, so that correspondence SiGe base plasma pin diode strings two ends are applied in its all SiGe base etc. after voltage
Ion pin diodes are in forward conduction state.
From the foregoing, it will be observed that the embodiment of the present invention is employed by the P areas to SiGe base plasma pin diodes with N areas being based on
The polysilicon damascene technique of the deep etching of etching, the technique can provide abrupt junction pi and tie with ni, and can effectively carry
High pi knots, the junction depth of ni knots, strengthen the concentration of solid state plasma and the controllability of distribution.Also, due to sige material tool
There is high carrier mobility, therefore high carrier concentration can be formed so as to improve the performance of diode in I areas.In addition, conventional
In making the P areas of solid plasma pin diode and the preparation technology in N areas, formed using injection technology, the method requires note
Enter dosage and energy is larger, it is high to equipment requirement and incompatible with existing process；And diffusion technique is adopted, though junction depth is deeper,
Simultaneously P areas are larger with the area in N areas, and integrated level is low, and doping content is uneven, affect the electricity of solid plasma pin diode
Performance, causes the poor controllability of solid plasma bulk concentration and distribution.
Become obvious by the other side and feature below with reference to the detailed description of accompanying drawing, the present invention.But should know
Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept
Ground explanation structure described herein and flow process.
Description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is a kind of structural representation of restructural holographic antenna of the embodiment of the present invention；
Fig. 2 is a kind of preparation method flow chart of SiGe bases plasma pin diodes of the embodiment of the present invention；
Fig. 3 is a kind of structural representation of SiGe bases plasma pin diodes provided in an embodiment of the present invention；
Fig. 4 is a kind of structural representation of SiGe bases plasma pin diode strings provided in an embodiment of the present invention；
Fig. 5 a- Fig. 5 s are the preparation method schematic diagram of another kind of SiGe bases plasma pin diodes of the embodiment of the present invention；
Fig. 6 is the device architecture schematic diagram of another kind of SiGe bases plasma pin diodes of the embodiment of the present invention.
Specific embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The present invention proposes a kind of preparation method of the SiGe base plasma pin diodes for restructural holographic antenna.
The SiGe base plasma pin diodes are to form horizontal pin diodes based on the SiGe in dielectric substrate, and it is adding Dc bias
When, DC current can form the solid state plasma of free carrier (electronics and hole) composition, the plasma on its surface
With metalloid characteristic, i.e., there is reflex to electromagnetic wave, the microwave transmission characteristic of its reflection characteristic and surface plasma,
Concentration and distribution are closely related.
Laterally solid plasma pin diode plasma reconfigurable antenna can be by the pole of horizontal solid plasma pin bis-
Pipe is arranged in a combination by array, is turned on using the solid plasma pin diode selecting in external control array, makes the battle array
Row form dynamic solid state plasma striped, possess the function of antenna, have transmitting and receive capabilities to specific electromagnetic wave, and
The antenna can pass through array in solid plasma pin diode selectivity conducting, change solid state plasma shape of stripes and
Distribution, so as to realize the reconstruct of antenna, has important application prospect in terms of national defence communication with Radar Technology.
Hereinafter, the technological process of the SiGe base solid plasma pin diodes prepared to the present invention is made further in detail
Description.In figure, for convenience of explanation, the thickness in layer and region is zoomed in or out, shown size does not represent actual size.
Embodiment one
The present embodiment provides a kind of preparation method of the SiGe base plasma pin diodes for restructural holographic antenna,
The SiGe bases plasma pin diodes are used to make restructural holographic antenna.Fig. 1 is referred to, Fig. 1 is the embodiment of the present invention
A kind of structural representation of restructural holographic antenna, the restructural holographic antenna includes：SiGeOI semiconductor chips (1)；System
Make first antenna arm (2) on the SiGeOI semiconductor chips (1), the second antenna arm (3), coaxial feeder (4) and holography
Annulus (14)；Wherein, the first antenna arm (2) and second antenna arm (3) are including being distributed in the coaxial feeder (4) two
Side and isometric SiGe base plasma pin diode strings, the holographic annulus (14) includes multiple poles of SiGe bases plasma pin bis-
Pipe string (w7).
The antenna arm of restructural holographic antenna provided in an embodiment of the present invention is by SiGe base plasma pin diode string groups
Into, and SiGe base plasma pin diodes are the characteristics of have selective conducting, under the control of outside control, SiGe bases etc. from
The conducting length flexibly changing of sub- pin diodes, therefore antenna arm effective active length operationally also can change, it is holographic
The electrology characteristic of antenna also can change therewith, and the operating frequency of antenna can meet more actual demands, so as to realize antenna
Frequency reconfiguration.
Fig. 2 is referred to, Fig. 2 is a kind of preparation method flow process of SiGe bases plasma pin diodes of the embodiment of the present invention
Figure；The preparation method includes step：
A () chooses the SiGeOI substrates of a certain crystal orientation, on SiGeOI substrates isolated area is arranged；
In this step, using SiGeOI substrates the reason for, is, for solid plasma antenna because its needs is good
Microwave property, and solid plasma pin diode needs to have good isolation characteristic and current-carrying to meet this demand
Son is the restriction ability of solid state plasma, and SiGeOI substrates due to its have can with isolation channel be conveniently formed pin every
From region, silica (SiO2) also can be that solid state plasma is limited in top layer silicon by carrier, it is advantageous to using
Substrates of the SiGeOI as solid plasma pin diode.And the carrier mobility of sige material is than larger, therefore device can be improved
Part performance.
B () forms the second protective layer in the substrate surface；Is formed on second protective layer using photoetching process
Two isolated area figures；Protected using specified location etching described second of the dry etch process in the second isolated area figure
Layer and the substrate are forming p-type groove and N-type groove；
Wherein, the depth of p-type groove and N-type groove is more than the second protective layer thickness and less than the second protective layer and substrate top
Layer SiGe thickness sums.Preferably, distance of the bottom of the p-type groove and N-type groove away from the top layer Si Ge bottom of substrate is 0.5
Micron～30 microns, forms the deep trouth being generally acknowledged that, so can form Impurity Distribution when p-type and N-type active area is formed equal
Even and high-dopant concentration P, N area and tie with precipitous Pi and Ni, be beneficial to raising i areas plasma density.
C () forms the first p-type active area and the first N-type in the p-type groove and the N-type groove using ion implanting
Active area；
D () fills the p-type groove and the N-type groove, and using ion implanting in top layer Si Ge of the substrate
Form the second p-type active area and the second N-type active area；
E () generates over the substrate silica, the impurity in active area is activated using annealing process, in the p-type
, to form lead, Passivation Treatment and photoetching PAD are forming the plasma for contact zone and N-type contact zone lithography fair lead
Pin diodes.
Further, on the basis of above-described embodiment, isolated area is set on SiGeOI substrates, including：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the substrate are to form isolation channel, and the depth of the isolation channel is more than or equal to the thickness of top layer Si Ge of the substrate；
(a4) fill the isolation channel to form the isolated area of the plasma pin diodes.
Further, on the basis of above-described embodiment, first protective layer includes the first silicon dioxide layer and first
Silicon nitride layer；Correspondingly, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
This have the advantage that, using silica (SiO2) loose nature, by the stress of silicon nitride (SiN) every
From so as to can not conduct into top layer Si Ge, it is ensured that top layer Si Ge performance is stablized；Based on silicon nitride (SiN) and SiGe dry
High selectivity when method is etched, film is sheltered by the use of silicon nitride (SiN) as dry etching, it is easy to which technique is realized.Of course, it is possible to
It is understood by, the number of plies of protective layer and the material of protective layer are not limited herein, as long as protective layer can be formed.
Further, on the basis of above-described embodiment, second protective layer includes the second silicon dioxide layer and second
Silicon nitride layer；Correspondingly, it is described to include in the substrate surface the second protective layer of formation：
(b1) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b2) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
, similar to the effect of the first protective layer, here is omitted for the benefit of do so.
Further, on the basis of above-described embodiment, step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall shape of the p-type groove and the N-type groove
Into oxide layer；
(c2) using wet-etching technology the oxide layer of the p-type groove and the N-type trench wall is etched to complete
State the planarizing of p-type groove and the N-type trench wall；This have the advantage that：The projection shape of trenched side-wall can be prevented
Into electric field concentrated area, Pi and Ni junction breakdowns are caused.
(c3) the p-type groove and the N-type groove are carried out ion implanting to form the first p-type active area and institute
The first N-type active area is stated, the first N-type active area is away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron, the first p-type active area is away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron.
Further, on the basis of above-described embodiment, step (c3) includes：
(c31) p-type groove described in photoetching and the N-type groove；
(c32) p type impurity is injected separately into the p-type groove and the N-type groove using the method with glue ion implanting
With N-type impurity forming the first p-type active area and the first N-type active area；
(c33) photoresist is removed.
Wherein, the purpose of the first active area of formation is：One layer of uniform heavily doped region is formed in the side wall of groove, should
Region is the heavily doped region in Pi and Ni knots, and the formation of the first active area has following several benefits, many to insert in groove
Crystal silicon illustrates as a example by electrode, first, avoid hetero-junctions between polysilicon and SiGe and tie with Pi and Ni and overlap, it is caused
The uncertainty of performance；Secondth, the diffusion velocity of impurity in polysilicon can be utilized than characteristic faster, further to P and N areas
Diffusion, further improves the doping content in P and N areas；3rd, this prevents during polysilicon process, polysilicon life
Cavity is formed between polysilicon that long inequality is caused and cell wall, the cavity can cause polysilicon bad with the contact of side wall,
Affect device performance.
Further, on the basis of above-described embodiment, step (d) includes：
(d1) the p-type groove and the N-type groove are filled using polysilicon；Wherein, the material for filling groove can also
For metal, heavily doped polysilicon germanium or heavily doped silicon, preferably polysilicon herein.
(d2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type ditch
Groove position is injected separately into p type impurity and N-type impurity to form the second p-type active area and the second N-type active area and while shape
Into p-type contact zone and N-type contact zone；
(d4) photoresist is removed；
(d5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
Further, on the basis of above-described embodiment, the holographic annulus (14) by eight sections of isometric SiGe bases etc. from
Sub- pin diode arrangements form octagon structure, wherein, the length of side of the octagon and the first antenna arm (2) and
Second antenna arm (3) the length sum is identical.
Further, on the basis of above-described embodiment, the restructural holographic antenna is also described including being made in
The direct current biasing line (5,6,7,8,9,10,11,12) of SiGeOI semiconductor chips (1)；The direct current biasing line (5,6,7,8,9,
, 10th, 11 12) intermittent is electrically connected to SiGe bases plasma pin diode string (w1, w2, w3, w4, the w5, w6) two ends,
And the method using chemical vapor deposition is made on the SiGeOI semiconductor chips (1), its material is that copper, aluminium or process are mixed
Any one in miscellaneous polysilicon, wherein, the first antenna arm (2) including solid plasma pin diode string (w1, w2,
W3), second antenna arm (3) is including solid plasma pin diode string (w4, w5, w6).
Further, on the basis of above-described embodiment, it is provided in an embodiment of the present invention to refer to Fig. 3 and Fig. 4, Fig. 3
A kind of structural representation of SiGe bases plasma pin diodes；Fig. 4 is a kind of SiGe bases plasma provided in an embodiment of the present invention
The structural representation of pin diode strings.The SiGe bases plasma pin diodes include P+ areas (27), N+ areas (26) and intrinsic
Area (22), and also include the first metal contact zone (23) and the second metal contact zone (24)；Wherein, the first metal contact zone
(23) the P+ areas (27) and positive voltage are electrically connected, the second metal contact zone (24) is electrically connected the N+ areas
(26) and negative voltage, so that correspondence SiGe base plasma pin diode strings two ends be applied in after voltage its all SiGe base etc. from
Sub- pin diodes are in forward conduction state.
Provided by the present invention for the SiGe base plasma pin diodes of restructural holographic antenna preparation method possess as
Lower advantage：
(1) sige material that pin diodes are used, due to its high mobility and the characteristic of big carrier lifetime, can have
Effect improves the solid plasma bulk concentration of pin diodes；
(2) the P areas of pin diodes employ the polysilicon damascene technique of the deep etching based on etching, the technique with N areas
Abrupt junction pi can be provided to tie with ni, and pi knots, the junction depth of ni knots can be effectively improved, make the concentration of solid state plasma
With the good controllability of realization of distribution；
(3) pin diodes employ a kind of Deep trench isolation technique based on etching, are effectively improved hitting for device
Wear voltage, it is suppressed that impact of the leakage current to device performance.
Embodiment two
Fig. 5 a- Fig. 5 s are referred to, Fig. 5 a- Fig. 5 s are another kind of SiGe bases plasma pin diodes of the embodiment of the present invention
Preparation method schematic diagram, on the basis of above-described embodiment one, to prepare channel length, as 22nm, (solid plasma region is long
Spend for 100 microns) SiGe base solid plasma pin diodes as a example by be described in detail, comprise the following steps that：
Step 1, backing material preparation process：
(1a) as shown in Figure 5 a, the SiGeOI substrate slices 101 of (100) crystal orientation are chosen, doping type is p-type, doping content
For 1014cm-3, the thickness of top layer Si Ge is 50 μm；
(1b) as shown in Figure 5 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits a SiO of one layer of 40nm thickness on SiGe2Layer 201；
(1c) using the method for chemical vapor deposition, a Si of one layer of 2 μ m thick is deposited on substrate3N4/ SiN layer
202；
Step 2, isolates preparation process：
(2a) as shown in Figure 5 c, isolated area, wet etching isolated area are formed on above-mentioned protective layer by photoetching process
One Si3N4/ SiN layer 202, forms isolated area figure；Using dry etching, form wide 5 μm in isolated area, depth be 50 μm it is deep every
From groove 301；
(2b) as fig 5d, after photoetching isolated area, using the method for CVD, SiO is deposited2401 by the deep isolation trench
Fill up；
(2c) as depicted in fig. 5e, using chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation
CMP) method, removes the Si of surface the3N4The SiO of/SiN layer 202 and the2Layer 201, makes substrate surface smooth；
Step 3, P, N area deep trouth preparation process：
(3a) as shown in figure 5f, using CVD method, consecutive deposition prolongs two layer materials on substrate, and ground floor is that 300nm is thick
2nd SiO of degree2Layer 601, the second layer is the 2nd Si of 500nm thickness3N4/ SiN layer 602；
(3b) as shown in fig. 5g, photoetching P, N areas deep trouth, the Si of wet etching P, N areas the 2nd3N4The SiO of/SiN layer 602 and the 2nd2
Layer 601, forms P, N area figure；Using dry etching, form wide 4 μm in P, N area, deep 5 μm deep trouth 701, the length of P, N area groove
Degree determines according to the applicable cases in prepared antenna；
(3c) as shown in figure 5h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801, so that
P, N area groove inwall is smooth；
(3d) as shown in figure 5i, the oxide layer 801 of P, N area groove inwall is removed using wet-etching technology.
Step 4, P, N contact zone preparation process：
(4a) as shown in figure 5j, photoetching P areas deep trouth, p is carried out using the method with glue ion implanting to P areas groove sidewall+Note
Enter, make to form thin p on the wall of side+Active area 1001, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4b) photoetching N areas deep trouth, n is carried out using the method with glue ion implanting to N areas groove sidewall+Injection, makes on the wall of side
Form thin n+Active area 1002, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4c) as shown in figure 5k, using the method for CVD, the depositing polysilicon 1101 in P, N area groove, and groove is filled up；
(4d) as shown in Fig. 5 l, using CMP, the Si of surface polysilicon 1101 and the 2nd is removed3N4/ SiN layer 602, puts down surface
It is whole；
(4e) as shown in figure 5m, using the method for CVD, in one layer of polysilicon 1301 of surface deposition, thickness is 200～
500nm；
(4f) as shown in figure 5n, photoetching P areas active area, using band glue ion injection method p is carried out+Injection, makes P areas active
Area's doping content reaches 0.5 × 1020cm-3, photoresist is removed, form P contacts 1401；
(4g) photoetching N areas active area, using band glue ion injection method n is carried out+Injection, makes N areas active area doping content
For 0.5 × 1020cm-3, photoresist is removed, form N contacts 1402；
(4h) as shown in Fig. 5 o, using wet etching, the polysilicon 1301 beyond P, N contact zone is etched away, forms P, N and connect
Tactile area；
(4i) as shown in Fig. 5 p, using the method for CVD, in surface deposition SiO21601, thickness is 800nm；
(4j) at 1000 DEG C, anneal 1 minute, make the impurity activation of ion implanting and advance impurity in polysilicon；
Step 5, constitutes PIN diode step：
(5a) as shown in Fig. 5 q, the lithography fair lead 1701 in P, N contact zone；
(5b) as shown in Fig. 5 r, substrate surface splash-proofing sputtering metal forms metal silicide 1801 in 750 DEG C of alloys, and etches
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) as shown in Fig. 5 s, Si is deposited3N4/ SiN forms passivation layer 1901, and photoetching PAD forms PIN diode, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are illustration, according to the conventional meanses of those skilled in the art
The conversion done is the protection domain of the application.
Prepared by the present invention is applied to the pin diodes of solid plasma reconfigurable antenna, first, the SiGe materials for being used
Material, due to its high mobility and the characteristic of big carrier lifetime, improves the solid plasma bulk concentration of pin diodes；In addition,
The P areas of pin diodes employ the polysilicon damascene technique of the deep etching based on etching with N areas, and the technique can provide prominent
Become knot pi and ni to tie, and pi knots, the junction depth of ni knots can be effectively improved, make solid state plasma concentration and distribution can
Control property strengthens, and is conducive to preparing high performance plasma antenna；Again, what prepared by the present invention is applied to solid plasma can weigh
The pin diodes of structure antenna employ a kind of Deep trench isolation technique based on etching, are effectively improved puncturing for device
Voltage, it is suppressed that impact of the leakage current to device performance.
Embodiment three
Fig. 6 is refer to, Fig. 6 shows for the device architecture of another kind of SiGe bases plasma pin diodes of the embodiment of the present invention
It is intended to.Plasma pin diodes are made using above-mentioned preparation method as shown in Figure 2, specifically, the poles of plasma pin bis-
Pipe prepares formation on SiGeOI substrates 301, and the P areas 305 of pin diodes, N areas 306 and is laterally positioned in the P areas 305 and
I areas between the N areas 306 are respectively positioned in top layer Si Ge302 of substrate.Wherein, the pin diodes can using STI deep trouths every
From that is, the P areas 305 and the outside of N areas 306 are each provided with an isolation channel 303, and the depth of the isolation channel 303 more than or equal to top
The thickness of layer SiGe.In addition, the P areas 305 and the N areas 306 include that a thin layer p-type is active can correspond to respectively along substrate direction
Area 307 and a thin layer N-type active area 304.
In sum, specific case used herein is to solid plasma pin diode of the present invention and preparation method thereof
Principle and embodiment be set forth, the explanation of above example is only intended to help and understands the method for the present invention and its core
Thought is thought；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, in specific embodiment and model is applied
Place and will change, in sum, this specification content should not be construed as limiting the invention, the protection of the present invention
Scope should be defined by appended claim.
Claims (10)
1. a kind of preparation method of the SiGe base plasma pin diodes for restructural holographic antenna, it is characterised in that described
SiGe base plasma pin diodes are used to make restructural holographic antenna, and the restructural holographic antenna includes：SiGeOI partly leads
Body substrate (1)；First antenna arm (2), the second antenna arm (3), the coaxial feed being produced on the SiGeOI semiconductor chips (1)
Line (4) and holographic annulus (14)；Wherein, the first antenna arm (2) and second antenna arm (3) are described same including being distributed in
Feeder shaft (4) both sides and isometric SiGe base plasma pin diode strings, the holographic annulus (14) is including multiple SiGe bases etc.
Ion pin diode strings (w7)；The preparation method includes step：
A () chooses the SiGeOI substrates of a certain crystal orientation, on SiGeOI substrates isolated area is arranged；
B () forms the second protective layer in the substrate surface；Using photoetching process formed on second protective layer second every
From area's figure；Using dry etch process the specified location of the second isolated area figure etch second protective layer and
The substrate is forming p-type groove and N-type groove；
C () forms the first p-type active area using ion implanting in the p-type groove and the N-type groove and the first N-type is active
Area；
D () fills the p-type groove and the N-type groove, and formed in top layer Si Ge of the substrate using ion implanting
Second p-type active area and the second N-type active area；
E () generates over the substrate silica, using annealing process the impurity in active area is activated, in p-type contact
, to form lead, Passivation Treatment and photoetching PAD are forming the plasma pin bis- for area and N-type contact zone lithography fair lead
Pole pipe.
2. preparation method as claimed in claim 1, it is characterised in that isolated area is set on SiGeOI substrates, including：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) using dry etch process the specified location of the first isolated area figure etch first protective layer and
The substrate is to form isolation channel, and the depth of the isolation channel is more than or equal to the thickness of top layer Si Ge of the substrate；
(a4) fill the isolation channel to form the isolated area of the plasma pin diodes.
3. preparation method as claimed in claim 2, it is characterised in that first protective layer include the first silicon dioxide layer and
First silicon nitride layer；Correspondingly, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
4. preparation method as claimed in claim 1, it is characterised in that second protective layer include the second silicon dioxide layer and
Second silicon nitride layer；Correspondingly, it is described to include in the substrate surface the second protective layer of formation：
(b1) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b2) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
5. preparation method as claimed in claim 1, it is characterised in that step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall of the p-type groove and the N-type groove forms oxygen
Change layer；
(c2) etch the oxide layer of the p-type groove and the N-type trench wall to complete the p-type using wet-etching technology
The planarizing of groove and the N-type trench wall；
(c3) carry out ion implanting to the p-type groove and the N-type groove to form the first p-type active area and described
One N-type active area, the first N-type active area is to be less than 1 away from the N-type trenched side-wall and bottom depth along ion dispersal direction
The region of micron, the first p-type active area is to be less than 1 away from the p-type trenched side-wall and bottom depth along ion dispersal direction
The region of micron.
6. preparation method as claimed in claim 5, it is characterised in that step (c3) includes：
(c31) p-type groove described in photoetching and the N-type groove；
(c32) p type impurity and N-type are injected separately into the p-type groove and the N-type groove using the method with glue ion implanting
Impurity is forming the first p-type active area and the first N-type active area；
(c33) photoresist is removed.
7. preparation method as claimed in claim 1, it is characterised in that step (d) includes：
(d1) the p-type groove and the N-type groove are filled using polysilicon；
(d2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type groove institute
P type impurity and N-type impurity are injected separately in position to form the second p-type active area and the second N-type active area and while form p-type
Contact zone and N-type contact zone；
(d4) photoresist is removed；
(d5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
8. preparation method as claimed in claim 1, it is characterised in that the holographic annulus (14) is by eight sections of isometric SiGe bases
Plasma pin diode arrangements form octagon structure, wherein, the length of side of the octagon and the first antenna arm
(2) it is identical with the second antenna arm (3) length sum.
9. preparation method as claimed in claim 1, it is characterised in that the restructural holographic antenna also includes being made in described
The direct current biasing line (5,6,7,8,9,10,11,12) of SiGeOI semiconductor chips (1)；The direct current biasing line (5,6,7,8,9,
, 10th, 11 12) intermittent is electrically connected to SiGe bases plasma pin diode string (w1, w2, w3, w4, the w5, w6) two ends,
And the method using chemical vapor deposition is made on the SiGeOI semiconductor chips (1), its material is that copper, aluminium or process are mixed
Any one in miscellaneous polysilicon, wherein, the first antenna arm (2) including solid plasma pin diode string (w1, w2,
W3), second antenna arm (3) is including solid plasma pin diode string (w4, w5, w6).
10. preparation method as claimed in claim 1, it is characterised in that the SiGe bases plasma pin diodes include P+ areas
(27), N+ areas (26) and intrinsic region (22), and also include the first metal contact zone (23) and the second metal contact zone (24)；Its
In, the first metal contact zone (23) is electrically connected the P+ areas (27) and positive voltage, the second metal contact zone
(24) the N+ areas (26) and negative voltage are electrically connected, so that correspondence SiGe base plasma pin diode strings two ends are applied in
Its all SiGe bases plasma pin diode is in forward conduction state after voltage.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111929646A (en) * | 2020-08-14 | 2020-11-13 | 中国地质大学（北京） | Beam scanning ground penetrating radar system and intelligent beam scanning detection method |
| CN113314835A (en) * | 2021-05-26 | 2021-08-27 | 北京京东方技术开发有限公司 | Solid-state plasmon antenna and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN102903736A (en) * | 2011-07-27 | 2013-01-30 | 中国科学院微电子研究所 | Diode and manufacturing method thereof |
| US20130025785A1 (en) * | 2009-01-07 | 2013-01-31 | Lam Research Corporation | Profile and cd uniformity control by plasma oxidation treatment |
| CN103871900A (en) * | 2014-03-06 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Groove field effect transistor and forming method thereof |
| CN104992942A (en) * | 2015-07-03 | 2015-10-21 | 西安电子科技大学 | Vertically-stacked strain Si/SiGe heterojunction CMOS device structure and preparation method thereof |
| US20160300738A1 (en) * | 2015-04-07 | 2016-10-13 | Tokyo Electron Limited | Plasma Generation and Control Using a DC Ring |
-
2016
- 2016-12-20 CN CN201611185622.1A patent/CN106602215A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130025785A1 (en) * | 2009-01-07 | 2013-01-31 | Lam Research Corporation | Profile and cd uniformity control by plasma oxidation treatment |
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN102903736A (en) * | 2011-07-27 | 2013-01-30 | 中国科学院微电子研究所 | Diode and manufacturing method thereof |
| CN103871900A (en) * | 2014-03-06 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Groove field effect transistor and forming method thereof |
| US20160300738A1 (en) * | 2015-04-07 | 2016-10-13 | Tokyo Electron Limited | Plasma Generation and Control Using a DC Ring |
| CN104992942A (en) * | 2015-07-03 | 2015-10-21 | 西安电子科技大学 | Vertically-stacked strain Si/SiGe heterojunction CMOS device structure and preparation method thereof |
Non-Patent Citations (3)
| Title |
|---|
| ALY E. FATHY等: "Silicon-Based Reconfigurable Antennas—Concepts, Analysis, Implementation, and Feasibility", 《IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES》 * |
| DA-JIN KIM等: "Optomization of the Intrinsic Length of a PIN Diode for a Reconfigurable Antenna", 《2016 INTERNATIONAL CONFERENCE ON ELECTRONICS，INFORMATION，AND COMMUNICATIONS》 * |
| 莫瑞明: "全息天线的理论和实验研究", 《中国优秀硕士学位论文全文数据库基础科学辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111929646A (en) * | 2020-08-14 | 2020-11-13 | 中国地质大学（北京） | Beam scanning ground penetrating radar system and intelligent beam scanning detection method |
| CN113314835A (en) * | 2021-05-26 | 2021-08-27 | 北京京东方技术开发有限公司 | Solid-state plasmon antenna and preparation method thereof |
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