CN106575957B

CN106575957B - Integrated circuit provided with a crystal acoustic resonator device

Info

Publication number: CN106575957B
Application number: CN201580042442.5A
Authority: CN
Inventors: 杰弗里·B·希利
Original assignee: Akoustis Inc
Current assignee: Akoustis Inc
Priority date: 2014-06-06
Filing date: 2015-06-05
Publication date: 2019-12-17
Anticipated expiration: 2035-06-05
Also published as: CN110912529A; CN110912529B; KR20220108210A; WO2015188147A1; KR102427297B1; KR20170026459A; CN106575957A

Abstract

a configurable Single Crystal Acoustic Resonator (SCAR) device integrated circuit. The circuit comprises a plurality of SCAR devices numbered from 1 to N, where N is 2 and an integer greater than 2. Each SCAR device has a thickness of single crystal piezoelectric material formed to cover a surface region of a substrate member. The single crystal piezoelectric material is characterized by less than 10¹²Defect/cm²the dislocation density of (a).

Description

Integrated circuit provided with a crystal acoustic resonator device

Cross Reference to Related Applications

This application claims priority from U.S. application No.14/298,057, filed 6/2014 and U.S. application No.14/298,100, filed 6/2014.

Background

The present invention generally relates to electronic devices. More specifically, the present invention provides technology relating to single crystal acoustic resonators. Merely by way of example, the invention has been applied to resonator devices, in particular for communication devices, mobile devices, computing devices.

Mobile telecommunications devices have been successfully deployed throughout the world. Over a billion mobile devices (including cellular handsets and smart phones) are manufactured within a year, and the unit volume continues to grow year by year. Due to the mass production of 4G/LTE hill climbs in approximately 2012, and the proliferation of mobile data services, data-rich content drives the growth of the smartphone domain — expected to reach 2B per year in the coming years. The coexistence of new and legacy standards and the desire for higher data rate requirements drives RF complexity in smartphones. Unfortunately, there are limitations in conventional RF technology that are problematic and may cause defects in the future.

From the foregoing, techniques for improving electronic devices are highly desirable.

Disclosure of Invention

In accordance with the present invention, techniques are provided that generally relate to electronic devices. More specifically, the present invention provides techniques related to single crystal acoustic resonators. Merely by way of example, the invention has been applied to resonator devices, in particular for communication devices, mobile devices, computing devices.

In an example, the present invention provides a single crystal capacitor dielectric material disposed on a substrate by limited area epitaxy. The material is coupled between a pair of electrodes, which in an example are disposed from the upper and back sides of the substrate member. In an example, the single crystal capacitor dielectric material is provided using a metal organic chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition, chemical vapor deposition, or wafer bonding process. In an example, the limited area epitaxy is stripped (lifted-off) the substrate and transferred to another substrate. In an example, the material is characterized by a defect density of less than 1E +11 defects per square centimeter. In an example, the single crystal capacitor material is selected from at least one of AlN, AlGaN, InN, BN, or other group iii nitrides. In an example, the single crystal capacitor material is selected from at least one of a single crystal oxide including a high K dielectric, ZnO, or MgO.

In an example, a single crystal acoustoelectric device is provided. The apparatus has a substrate having a surface region. The apparatus has a first electrode material coupled to a portion of the substrate and a single crystal capacitor dielectric material having a thickness greater than 0.4 microns and covering an exposed portion of the surface region and coupled to the first electrode material. In an example, the single crystal capacitor dielectric material is characterized by less than 10¹²Defect/cm²The dislocation density of (a). The second electrode material overlies the single crystal capacitor dielectric material.

In an example, the invention provides a configurable single crystal acoustic resonator (SC)AR) device integrated circuits. The circuit comprises a plurality of SCAR devices numbered from 1 to N, where N is 2 and an integer greater than 2. Each SCAR device has a thickness of single crystal piezoelectric material formed to cover a surface region of a substrate member. The single crystal piezoelectric material is characterized by less than 10¹²Defect/cm²the dislocation density of (a).

One or more benefits are realized using the present invention over the prior art. In particular, the invention enables a cost-effective resonator device for communication applications. In particular embodiments, the present apparatus may be manufactured in a relatively simple and cost-effective manner. Depending on the embodiment, the present apparatus and method may be fabricated according to one of ordinary skill in the art using conventional materials and/or methods. The apparatus uses a material comprising gallium and nitrogen, which is monocrystalline. Depending on the implementation, one or more of these benefits may be achieved. Of course, there can be other variations, modifications, and alternatives.

A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.

Drawings

For a more complete understanding of the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered as limiting the scope of the invention, the presently described embodiments and the presently understood best mode of the invention are described in more detail through the use of the accompanying drawings, in which:

Fig. 1 is a simplified diagram illustrating a surface single crystal acoustic resonator according to an example of the present invention.

Figure 2 is a simplified diagram illustrating a bulk single crystal acoustic resonator according to an example of the present invention.

Figure 3 is a simplified diagram illustrating features of a bulk single crystal acoustic resonator according to an example of the present invention.

Fig. 4 is a simplified diagram illustrating an exemplary piezoelectric structure according to the present invention.

Fig. 5 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention.

Fig. 6 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention.

Fig. 7 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention.

Fig. 8 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention.

Fig. 9 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention.

Fig. 10 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention.

Fig. 11 is a simplified diagram of a substrate member according to an example of the invention.

Fig. 12 is a simplified diagram of a substrate member according to an example of the invention.

fig. 13 is a simplified table showing characteristics of the present example compared to a conventional filter according to an example of the present invention.

Fig. 14 to 22 show a method of manufacturing a single crystal acoustic resonator device used in an example of the present invention.

Fig. 23 shows a circuit diagram of a single crystal acoustic resonator device in an example of the present invention.

Fig. 24 to 32 show a method of manufacturing a single crystal acoustic resonator device used in an example of the present invention.

Fig. 33 shows a circuit diagram of a single crystal acoustic resonator device in an example of the invention.

Fig. 34 and 35 show a reflector structure provided on a single crystal acoustic resonator device in an example of the present invention.

Fig. 36 shows a circuit diagram of a reflector structure integrated with the single crystal acoustic resonator device in the above figures.

Fig. 37 and 38 show a reflector structure provided on a single crystal acoustic resonator device in an example of the present invention.

Fig. 39 shows a circuit diagram of a reflector structure integrated with the single crystal acoustic resonator device in the above figures.

fig. 40 shows a simplified diagram of the bottom surface region and the top surface region of a single crystal acoustic resonator device in an example of the invention.

Fig. 41 and 44 show simplified examples of single crystal acoustic resonator devices configured in a filter ladder network in an example of the invention.

Fig. 45-52 show simplified examples of a two-element single crystal acoustic resonator device and a three-element single crystal acoustic resonator device according to examples of the present invention.

Detailed Description

as additional background, the number of frequency bands supported by smartphones is estimated to increase by a factor of 7 compared to conventional techniques. Therefore, more frequency bands mean that highly selective filtering performance is increasingly becoming a differentiator in the RF front-end of the smartphone. Unfortunately, conventional techniques have severe limitations.

That is, conventional filter technology is based on amorphous materials with poor electromechanical coupling efficiency (only 7.5% for lead-free materials), which results in nearly half of the emitted power dissipating in a highly selective filter. In addition, the single crystal acoustic wave device is expected to realize improvement of adjacent channel suppression. Since there are twenty (20) or more filters in current smartphones and these filters are inserted between the power amplifier and antenna scheme, there is an opportunity to improve the RF front-end and maximize spectral efficiency within the system by reducing heat dissipation, the size of the power amplifier while increasing the signal quality of the smartphone receiver.

with single crystal acoustic wave devices (hereinafter "SAW" devices) and filter schemes, one or more of the following benefits may be achieved: (1) large diameter silicon wafers (up to 200mm) are expected to achieve cost-effective high performance solutions, (2) with newly designed strained piezoelectric materials, the electromechanical coupling efficiency is expected to be over three times, and (3) the filter insertion loss is expected to be reduced by 1dB, thus enabling longer battery life, improved thermal management with smaller RF packaging, and improved signal quality and user experience. These benefits and others may be realized by the apparatus and methods of the present invention as further provided throughout the present specification and more particularly below.

Fig. 1 is a simplified diagram illustrating a surface single crystal acoustic resonator according to an example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. A surface single crystal acoustic resonator device 100 is shown with a crystalline piezoelectric material 120 of the present invention overlying a substrate 110. As shown, the acoustic wave propagates from the first spatial region to the second spatial region along a lateral direction substantially parallel to the pair of electrical ports 140, which forms an interdigital transducer configuration 130, the interdigital transducer configuration 130 having a plurality of metal lines 131 spatially arranged between the pair of electrical ports 140. In an example, the electrical ports on the left side may be designated for signal input, while the electrical ports on the right side are designated for signal output. In an example, a pair of electrode regions is configured and routed to be proximate to a plane parallel to a contact region coupled to the second electrode material.

In the SAW device example, surface acoustic waves produce resonant behavior over a narrow band near the 880MHz to 915MHz band, which is the designated pass band for european, middle east and african (EMEA) LTE enabled mobile smartphones. Variations may exist depending on the area of operation of the communication device. For example, in the transmission band in north america, the resonator may be designed such that the resonant behavior is in the frequency passband near 777MHz to 787 MHz. Other transmit bands found in other regions may be higher in frequency, such as the asian transmit band in the 2570MHz to 2620MHz passband. Additionally, the examples provided herein are for multiple transmit bands. In a similar manner, a similar implementation of a resonator filter is also required for the pass band on the receiver side of the radio front end. Of course, there can be variations, modifications, and alternatives.

Other features of surface acoustic wave devices include the fundamental frequency of the SAW device, which is determined by the surface propagation velocity (determined by the crystal mass of the piezoelectric material selected for the resonator) divided by the wavelength (determined by the fingers in the interdigitated layout in fig. 1). Measured propagation velocities (also called SAW velocities) in GaN close to 5800m/s have been recorded, with similar values expected for AlN. Thus, the higher SAW velocity of such III-nitrides enables the resonator to handle higher frequency signals for a given device geometry.

Resonators made of group III nitrides are desirable because such materials operate at high power (with their high critical electric field), high temperature (low intrinsic carrier concentration from their large band gap), and high frequency (high saturated electron velocity). Such high power devices (greater than 10 watts) are utilized in wireless infrastructure as well as commercial and military radar systems, to name a few. In addition, the stability, survivability and reliability of such devices are critical to field deployment.

Further details of the various elements provided in the present apparatus may be found throughout the present specification and more particularly below.

Figure 2 is a simplified diagram illustrating a bulk single crystal acoustic resonator according to an example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. A bulk single crystal acoustic resonator device 200 of the present invention having a crystalline piezoelectric material is shown. As shown, the acoustic wave propagates from the first spatial region to the second spatial region in the vertical direction between the upper electrode material 231 and the substrate member 210. As shown, the crystalline piezoelectric material 220 is disposed between an upper electrode material 231 and a lower electrode material 232. Upper electrode material 231 is disposed under a plurality of optional reflective layers formed overlying upper electrode 231 to form acoustic reflector region 240.

In the bulk acoustic wave (hereinafter "BAW") device example, the acoustic wave produces resonant behavior over a narrow frequency band, close to the 3600MHz to 3800MHz frequency band, which is a specified passband for an LTE enabled mobile smartphone. Variations may exist depending on the area of operation of the communication device. For example, in the transmission band in north america, the resonators may be designed such that the resonant behavior is in the frequency passband near 2000MHz to 2020 MHz. Other transmit bands are found in other regions, such as asian transmit bands in the 2500 to 2570MHz passband. Additionally, the examples provided herein are for multiple transmit bands. In a similar manner, a similar implementation of a resonator filter is also required for the pass band on the receiver side of the radio front end. Of course, there can be variations, modifications, and alternatives.

Other features of single crystal BAW devices include electromechanical acoustic coupling in the device, which is proportional to the piezoelectric constant (influenced by the design and strain of the single crystal piezoelectric layer) divided by the acoustic velocity (influenced by scattering and reflection in the piezoelectric material). Sonic velocities in GaN in excess of 5300m/s have been observed. Thus, the high acoustic velocity of such III-nitrides enables the resonator to handle higher frequency signals for a given device geometry.

Like SAW devices, resonators made of group III nitrides are desirable because these materials operate at high power (with their high critical electric field), high temperature (low intrinsic carrier concentration from their large band gap), and high frequency (high saturated electron velocity). Such high power devices (greater than 10 watts) are utilized in wireless infrastructure as well as commercial and military radar systems, to name a few. In addition, the stability, survivability and reliability of such devices are critical to field deployment.

Further details of the various materials provided in the present apparatus may be found throughout the present specification and more particularly below.

In an example, the apparatus has a substrate having a surface region. In an example, the substrate may be a thickness of material, composite, or other structure. In an example, the substrate may be selected from a dielectric material, a conductive material, a semiconductor material, or any combination of these materials. In an example, the substrate may also be a polymer member or the like. In a preferred example, the substrate is selected from materials provided in silicon, gallium arsenide, aluminum oxide, and the like, and combinations thereof.

In an example, the substrate is silicon. The substrate has a surface area, which may be an offset configuration or a trimmed configuration. In an example, the surface region is configured at an offset angle ranging from 0.5 degrees to 1.0 degrees. In an example, a substrate has<111>Oriented and has high resistivity (greater than 10)³ohm-cm). Of course, there can be other variations, modifications, and alternatives.

in an example, an apparatus has a first electrode material coupled to a portion of a substrateand a single crystal capacitor dielectric material having a thickness greater than 0.4 microns. In an example, the single crystal capacitor dielectric material has a suitable dislocation density. The dislocation density is less than 10¹²Defect/cm²And is greater than 10⁴Defect/cm²and variations thereof. The device has a second electrode material overlying the single crystal capacitor dielectric material. Further details of each of these materials may be found throughout the present specification and more particularly below.

In an example, the single crystal capacitor material is a suitable single crystal material having desired electrical properties. In an example, the single crystal capacitor material is typically a material containing gallium and nitrogen, such as AlN, AlGaN, or GaN, including InN, InGaN, BN, or other group III nitrides. In an example, the single crystal capacitor material is selected from at least one single crystal oxide of a single crystal oxide (an alloy of ZnO, MgO, or MgZnGaInO) including a high K dielectric. In an example, the high K is characterized by less than 10¹²Defect/cm²And is greater than 10⁴Defect/cm²The defect density of (2). Of course, there can be other variations, modifications, and alternatives.

In an example, the single crystal capacitor dielectric material is characterized by a surface area of at least 50 microns by 50 microns, and variations. In an example, the surface area may be 200 micrometers by 200 μm or up to 1000 μm by 1000 μm. Of course, there can be variations, modifications, and alternatives.

In an example, a single crystal capacitor dielectric material is configured in a first strained state to compensate for a substrate. That is, the single crystal material is in a state of compressive strain or a state of tensile strain associated with the overlying substrate material. In an example, the strained state of GaN when deposited on silicon is tensile strain, while the AlN layer is compressive strain relative to the silicon substrate.

In a preferred example, a single crystal capacitor dielectric material is deposited to cover the exposed portion of the substrate. In an example, the single crystal capacitor dielectric is lattice mismatched to the crystal structure of the substrate and may be strain compensated using a compressively strained piezoelectric nucleation layer (such as AlN or SiN).

In an example, a device has a first electrode material disposed with a backside of a substrate. In an example, the first electrode material is configured with the backside of the substrate. The arrangement includes a via structure arranged within a thickness of the substrate.

In an example, the electrode material may be made of a suitable material or materials. In an example, each of the first electrode material and the second electrode material is selected from a refractory metal or other noble metal. In an example, each of the first and second electrode materials is selected from one of tantalum, molybdenum, platinum, titanium, gold, aluminum, tungsten, or platinum, combinations thereof, or the like.

In an example, the first electrode material and the single crystal capacitor dielectric material comprise a first interface region that is substantially free of an oxide-containing material. In an example, the first electrode material and the single crystal capacitor dielectric material comprise a second interface region that is substantially free of oxide-containing material. In an example, the apparatus can include a first contact coupled to the first electrode material and a second contact coupled to the second electrode material such that each of the first and second contacts are configured in a coplanar arrangement.

in an example, the device has a reflector region disposed on the first electrode material. In an example, the device also has a reflector region disposed on the second electrode material. The reflector regions are made of alternating low impedance reflector layers (e.g. dielectric) and high impedance reflector layers (e.g. metal), where the thickness of each layer targets a quarter wavelength, but variations are possible.

In an example, the device has a nucleation material disposed between the single crystal capacitor dielectric material and the first electrode material. The nucleation material is typically AlN or SiN.

In an example, the device has a capping material disposed between the single crystal capacitor dielectric material and the second electrode material. In an example, the capping material is GaN.

In an example, the single crystal capacitor dielectric material preferably has other properties. That is, the single crystal capacitor dielectric material is characterized by a FWHM of less than 1 degree.

In an example, the single crystal capacitor dielectric is configured to propagate longitudinal signals at an acoustic speed of 5000 meters per second and greater. In other embodiments designed with strain, the signal may be higher than 6000m/s and lower than 12000 m/s. Of course, there can be variations, modifications, and alternatives.

The device also has the desired resonant behavior when tested using a two-port network analyzer. The resonant behavior is characterized by two resonance frequencies (so-called series and parallel), whereby one resonance frequency exhibits an infinite electrical impedance and the other resonance frequency exhibits an impedance of zero. Between such frequencies, the device operates inductively. In an example, the device has an s-parameter derived from a two-port analysis, which can be converted to an impedance. From the s11 parameter, the real and imaginary impedances of the device can be extracted. From the s21 parameter, the transmission gain of the resonator can be calculated. Using the parallel resonant frequency along a known piezoelectric layer thickness, the speed of sound for the device can be calculated.

Figure 3 is a simplified diagram illustrating features of a bulk single crystal acoustic resonator according to an example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. As shown, 300 illustrates the present invention applied as a band pass filter for RF signals. A particular frequency range is allowed to pass through the filter as indicated by the black box rising from the RF spectrum below the wavelength plot. This block is matched to the signal allowed to pass through the filter in the above illustration. The single crystal device may provide better sound quality relative to BAW devices and ease the specification requirements for power amplifiers due to lower filter losses. These may result in benefits for utilizing the devices of the present invention, such as extended batteries, efficient spectrum usage, uninterrupted caller experience, and the like.

Fig. 4 is a simplified diagram illustrating an exemplary piezoelectric structure according to the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the structure 400 is configured on a bulk substrate member 410 that includes a surface region. In an example, a growth process is used to form the single crystal piezoelectric material epitaxy 420. The growth process may include chemical vapor deposition, molecular beam epitaxy, or other techniques to cover the surface of the substrate. In an example, the single crystal piezoelectric material may include a single crystal gallium nitride (GaN) material, a single crystal Al (x) Ga (1-x) N (where 0< x <1.0(x ═ Al mole fraction ")) material, a single crystal aluminum nitride (AlN) material, or any combination of the above-mentioned substances with each other. Of course, there may be modifications, alternatives, and variations. Further details of the substrate may be found throughout the present specification and more particularly below.

Fig. 5 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the structure 500 is configured to cover a nucleation region 530, the nucleation region 530 covering a surface of the substrate 510. In an example, the nucleation region 530 is a layer or may be multiple layers. The nucleation region is made of a piezoelectric material to enable acoustic coupling in the resonator circuit. In an example, the nucleation region is a thin piezoelectric nucleation layer, which may range from about 0nm to 100nm in thickness, that may be used to initiate growth of the single crystal piezoelectric material 520 covering the surface of the substrate. In an example, the nucleation region may be made using a thin SiN or AlN material, but can include variations. In an example, the thickness of the single crystal piezoelectric material may range from 0.2 μm to 20 μm, but variations can exist. In an example, piezoelectric material having a thickness of about 2 μm is commonly used for 2GHz acoustic resonator devices. Further details of the substrate may be found throughout the present specification and more particularly below.

fig. 6 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. In an example, structure 600 is configured using GaN piezoelectric material 620. In an example, the respective regions are single crystalline or substantially single crystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 630, which nucleation region 630 may be one or more layers. In an example, the region is unintentionally doped (UID) and is disposed to strain compensate GaN on the surface region of the substrate 610. In an example, the nucleation region has an overlying GaN single crystal piezoelectric region (with Nd-Na: at 10)¹⁴/cm³And 10¹⁸/cm³In between) and a thickness rangeBetween 1.0 μm and 10 μm, but variations are possible. Further details of the substrate may be found throughout the present specification and more particularly below.

Fig. 7 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. As shown, structure 700 is configured using AlN piezoelectric material 720. Each region is monocrystalline or substantially monocrystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 730, which nucleation region 730 may be one or more layers. In an example, the region is unintentionally doped (UID) and is provided with AlN on a surface region of the strain-compensated substrate 710. In an example, the nucleation region has an overlying AlN single crystal piezoelectric region (with Nd-Na: at 10)¹⁴/cm³And 10¹⁸/cm³in between) and has a thickness in the range of between 1.0 μm and 10 μm, but variations are possible. Further details of the substrate may be found throughout the present specification and more particularly below.

fig. 8 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. As shown, structure 800 is configured using AlGaN piezoelectric material 820. Each region is monocrystalline or substantially monocrystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 830, which nucleation region 830 may be one or more layers. In an example, the region is unintentionally doped (UID) and is provided with AlN on a surface region of the strain-compensated substrate 810. In an example, among other features, an AlGaN single crystal piezoelectric layer, wherein Al (x) Ga (1-x) N has an Al molar composition of 0<x<1.0 (Nd-Na: at 10)¹⁴/cm³And 10¹⁸/cm³In between) with a thickness in the range between 1 μm and 10 μm. Further details of the substrate may be found throughout the present specification and more particularly below.

Fig. 9 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. Structure 900 is configured using AlN/AlGaN piezoelectric material 920. Each region being a single crystal or a basethe crystal is a single crystal. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 930, which nucleation region 930 may be one or more layers. In an example, the region is unintentionally doped (UID) and is provided to strain compensate AlN on the surface region of the substrate 910. In an example, one or more alternating stacks are formed to cover the nucleation region. In an example, the stack includes an AlGaN/AlN single crystal piezoelectric layer, wherein Al (x) Ga (1-x) N has an Al molar composition of 0<x<1.0; (Nd-Na: at 10)¹⁴/cm³And 10¹⁸/cm³in between) with a thickness ranging between 1.0 μm and 10 μm; AlN (1 nm)<Thickness of<30nm) for strain compensating the lattice and allowing a thicker AlGaN piezoelectric layer. In an example, the last single crystal piezoelectric layer is AlGaN. In an example, in particular, the total stack thickness of the structure is at least 1 μm and less than 10 μm. Further details of the substrate may be found throughout the present specification and more particularly below.

Fig. 10 is a simplified diagram illustrating a piezoelectric structure according to an alternative example of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. As shown, structure 1000 has an optional one or more GaN piezoelectric cap layers 1040. In an example, among other things, cap layer 1040 or region may be configured on any of the foregoing examples. In an example, the cap region may include at least one or more benefits. Such benefits include, among others, improved electro-acoustic coupling from the upper side metal (electrode 1) into the piezoelectric material, reduced surface oxidation, improved manufacturing, etc. In an example, the GaN cap region has a thickness ranging between 1nm to 10nm, and has a Nd-Na: at 10¹⁴/cm³And 10¹⁸/cm³Although variations are possible. Further details of the substrate may be found throughout the present specification and more particularly below.

Fig. 11 is a simplified diagram of a substrate member according to an example of the invention. This diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the single crystal acoustic resonator material 1120 may be a single crystal piezoelectric material epitaxy grown (using CVD or MBE techniques) on the substrate 1110. The substrate 1110 may be a bulk substrate, composite, or other member. Bulk substrate 1110 is preferably gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al2O3), aluminum nitride (AlN), combinations thereof, or the like.

Fig. 12 is a simplified diagram of a substrate member according to an example of the invention. This diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the single crystal acoustic resonator material 1220 can be a single crystal piezoelectric material epitaxy grown (using CVD or MBE techniques) on a substrate 1210. Substrate 1210 may be a bulk substrate, composite, or other member. Bulk substrate 1210 is preferably gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al2O3), aluminum nitride (AlN), combinations thereof, or the like. In an example, the surface region of the substrate is bare and exposed crystalline material.

Fig. 13 is a simplified table showing characteristics of the present example compared to a conventional filter according to an example of the present invention. As shown, the specifications of the "present example" and "conventional" implementations are shown with respect to the standard under the "filter scheme".

In the examples, GaN, SiC and Al₂O₃Oriented in the c-axis in order to improve or even maximize the polarization field in the piezoelectric material. In an example, for the same or similar reasons, the silicon substrate is<111>Orientation, in an example, the substrate may be cut or offset. Although c-axis or<111>Nominal orientation, but a cutting angle between +/-1.5 degrees may be selected for one or more of the following reasons: (1) controllability of the process; (2) maximization of K2 for acoustic resonators, and other reasons. In an example, a substrate is grown on one face (such as a growth face). Ga-face is the preferred growth surface (due to more mature processes). In an example, the substrate has a substrate resistivity greater than 104ohm-cm, although variations may exist. In an example, the substrate thickness ranges from 100 μm to 1mm when a single crystal piezoelectric deposition material is grown. Of course, there can be other variations, modifications, and alternatives.

As used herein, the terms "first", "second", "third" and "nth" should be understood in a generic sense. Such terms (alone or together) do not necessarily imply an order unless understood by one of ordinary skill in the art to do so. In addition, the terms "top" and "bottom" may not have meanings with reference to the direction of gravity, but should be understood in a common meaning. These terms should not unduly limit the scope of the claims.

As used herein, the term substrate is associated with group III nitride based materials including GaN, InGaN, AlGaN, or other group III containing alloys or compositions used as raw materials, or AlN, or the like. Such starting materials include polar GaN substrates (i.e., substrates having a maximum area nominally in the (hk l) plane, where h k 0 and l are non-zero), non-polar GaN substrates (i.e., substrate materials having a maximum area oriented at an angle ranging from about 80 degrees to 100 degrees from the aforementioned polar orientation toward the (hk l) plane, where l 0 and at least one of h and k is non-zero), or semi-polar GaN substrates (i.e., substrate materials having a maximum area oriented at an angle ranging from about +0.1 degrees to 80 degrees or 110 degrees to 179.9 degrees from the aforementioned polar orientation toward the (hk l) plane, where l 0 and at least one of h and k is non-zero).

The present device may be enclosed in a suitable package as shown. As an example, a packaged device may include any combination of the elements described above, as well as elements outside of this specification. As used herein, the term "substrate" may refer to a bulk substrate or may include overlying growth structures, such as epitaxial or functional regions containing gallium and nitrogen, combinations, and the like.

In an example, the present disclosure provides for step-by-step fabrication of a Single Crystal Acoustic Resonator (SCAR) device. Additionally, the present disclosure provides, among other devices, a manufacturing process for manufacturing two or more resonators together to provide a SCAR filter. In an example, the present process may be implemented using a conventional high-volume wafer fabrication facility for efficient operation and competitive costs. Of course, there can be other variations, modifications, and alternatives.

Fig. 14 to 22 show a method of manufacturing a single crystal acoustic resonator device used in an example of the present invention. These illustrations are merely examples, and should not unduly limit the scope of the claims.

An example of a manufacturing process may be briefly described as follows, with reference to the accompanying drawings:

1. Starting;

2. providing a substrate member having a surface area, for example a material having a diameter of 150mm or 200 mm;

3. Treating the surface region;

4. Forming an epitaxial material comprising a single crystal piezoelectric material covering a surface region to a desired thickness;

5. Patterning the epitaxial material using a mask and an etch process to form a trench region by causing formation of an exposed portion of the surface region by means of a pattern provided in the epitaxial material;

6. forming an upper side bond pad metal, which may include a stack having a metal layer that slowly reacts with an etchant in a backside substrate etching process, as defined below;

7. forming an upper electrode member including a first electrode member covering a portion of the epitaxial material and a second electrode member covering the upper bonding pad metal;

8. Masking and removing (by etching) a portion of the substrate from the backside to form a first trench region exposing a backside of the epitaxial material covering the first electrode member and a second trench region exposing a backside of the bond pad metal;

9. Forming a backside resonator metal material for covering the second electrode of the exposed portion of the epitaxial material (or the piezoelectric film) to form a connection from the epitaxial material to a backside of the bond pad metal coupled to the second electrode member covering the upper side bond pad metal;

10. Forming a resonator active region using a mask and etching process while electrically and spatially isolating the first electrode member from the second electrode member on the upper side while also trimming the resonant capacitor;

11. Forming a protective dielectric material (e.g., SiO) covering the upper surface region on the upper surface₂SiN); and

12. Other steps are performed as needed.

The above mentioned steps are provided for forming a resonator device using a single crystal capacitor dielectric. As shown, a pair of electrode members is configured to provide contact from one side of the device. One of the electrode members uses a backside contact that is coupled to the metal stack to configure the pair of electrodes. Of course, depending on the implementation, one or more steps may be added, removed, combined, rearranged, or replaced, or have other variations, alternatives, and modifications. Further details of the present manufacturing method can be found throughout the present specification and more particularly below.

As shown in fig. 14, the method begins by providing a substrate member 1410. The substrate member has a surface area, in an example the substrate member thickness (t) is 400 μm, which may have a diameter of 150mm or 200mm diameter material, but variations from 50mm to 300mm may exist.

In an example, a surface region of a substrate member is processed. The treatment typically includes cleaning and/or conditioning. In an example, the treatment takes place in a MOCVD or LPCVD reactor having ammonia gas flowing at high temperature (e.g., in the range from 940 ℃ to 1100 ℃) and at pressures ranging from one tenth of atmospheric pressure to one atmosphere. Other processes may also be used depending on the implementation.

In an example, the method includes forming an epitaxial material, which as shown includes a single crystal piezoelectric material 1420 covering a surface region to a desired thickness. Trimethyl gallium (TMG), trimethyl aluminum (TMA), ammonia (NH) gas are used₃) And hydrogen (H)₂) The epitaxial material is grown to a thickness in the range of 0.4 μm to 7.0 μm at a high temperature in the range of 940 ℃ to 1100 ℃ in an atmosphere controlled environment using an MOCVD or LPCVD growth apparatus, depending on the target resonance frequency of the capacitor device. The material also has a thickness of 10 per square centimeter⁴To 10¹²although variations may exist.

In an example, epitaxial material 1521 is patternedPatterning (fig. 15). Patterning involves masking and etching processes. The mask is typically 1 μm to 3 μm photoresist. Chlorine-based chemical reactions (gases may include BCl) in RIE or ICP etching tools under controlled temperature and pressure conditions₃、Cl₂And/or argon) to adjust the etch rate and sidewall profile. The patterning forms the trench regions (or via structures) by causing the formation of exposed portions of the surface region by means of a pattern provided in the epitaxial material.

In an example, the method forms an upper side bond pad metal 1630 (fig. 16), which may include a stack with a metal layer that reacts slowly with the etchant during the backside substrate etching process, as defined below. In examples, the metal is a refractory metal (such as tantalum, molybdenum, tungsten) or other metal (such as gold, aluminum, titanium, or platinum). As can be noted, this metal is then used as a stop region for the backside etch process.

In an example, the method forms an upper side metal structure (fig. 17). As shown, the structure has an upper electrode member that includes a first electrode member 1741 covering a portion of the epitaxial material and a second electrode member 1742 covering the upper bond pad metal. The metal structure is made using a refractory metal (such as tantalum, molybdenum, tungsten) and has a thickness of 300nm, selected to define the resonant frequency of the capacitor device.

In an example, the method performs backside processing by flipping the substrate upside down (fig. 18). In an example, the method includes a patterning process of a backside of the substrate. The process uses a masking and removal process by etching a portion of the substrate 1811 from the backside to form a first trench region exposing the backside of the epitaxial material covering the first electrode member and a second trench region exposing the backside of the bond pad metal. In an example, a chlorine-based gas is used in a RIE or ICP reactor and etching is performed at a temperature and pressure defined to control the etch rate, selectivity, and sidewall slope.

next, the method includes forming a backside resonator metal material 1943 (fig. 19) for covering the second electrode of the exposed portion of the epitaxial material (or piezoelectric film) to form a connection from the epitaxial material to a backside of the bond pad metal coupled to the second electrode member covering the upper side bond pad metal.

As shown, the piezoelectric film 1921 is sandwiched between the pair of electrodes disposed from the upper side and the back side of the substrate member 1911. The member is a <111> oriented silicon substrate having a resistivity greater than 10 ohm-cm.

In an example, the method forms or patterns the resonator active region 2022 using a mask and etch process (fig. 20). The ultimate goal is to electrically and spatially isolate the first electrode member from the second electrode member on the upper side while also trimming the resonant capacitor. In the example, the resonator active area is 200 μm × 200 μm. Patterning uses a chlorine-based RIE or ICP etching technique.

The process forms a thickness of protective material 2150 (fig. 21). In an example, the method forms a combination of silicon dioxide (which forms a specification compliant structure) and an overlying silicon nitride cap material. Silicon dioxide and silicon nitride materials are formed using a combination of silane, nitrogen, and oxygen sources and are deposited using a PECVD chamber.

The method forms first and second electrodes 2261 and 2262 (fig. 22) electrically coupled to first and second upper electrodes 2241 and 2242, respectively. The intrinsic device is labeled 2201. As desired, in examples, the method may also include other steps or other materials.

In an example, the method may further comprise one or more of these processes for forming the upper electrode structure, the passivation material and the backside treatment. In an example, a substrate including a capping structure can include a surface cleaner that uses HCl: h₂O (1:1) for a predetermined amount of time, then rinsed and placed in the sputtering tool.

In a sputtering tool for forming electrode metallization, the method includes using molybdenum (Mo) metal of a sputtering technique on an exposed upper side of a single crystal piezoelectric materialAnd depositing a covering layer.In an example, if desired, a thin titanium bond metal may be deposited prior to forming the Mo metalAmong other features, such titanium metals are used as adhesion layers. In an example, the method performs a masking and patterning process to etch away Mo in the field region (leaving Mo in the probe pad, coplanar waveguide (CPW) interconnect, top plate/first electrode, via bond pad/second electrode, and alignment mask regions). In an example, titanium-aluminumIs deposited on the Mo metal in the probe disk and CPW areas. In an example, Ti/Al is formed on the bond pads for subsequent deposition of copper-tin metal posts-CuSn posts and die cuts for wafer level flip chip packaging are deposited. In an example, the method forms a dielectric passivation of the upper surface (25 μm spin polymer photo-dielectric (ELECTRA WLP SH32-1-1)), or alternatively, a combination of SiN or SiO2 is formed to cover the upper surface.

In an example, the method includes patterning by exposing photo-dielectric and developing dielectric material on the pads to open the pads and probe the pads. The patterning process completes the upper region of the substrate structure before performing the backside processing. Further details of the present method can be found throughout the present specification and more particularly below.

In an example, a substrate is disposed on a flip-chip wafer and mounted (using photoresist) to a carrier wafer to begin a backside process. In an example, the backside processing uses a multi-step (e.g., two-step) process. In an example, the wafer is thinned from about 500 μm to about 300 μm and less using a backside grinding process, which may further include polishing and cleaning. In an example, the backside is coated with a masking material (such as photoresist) and patterned to open trench regions and bond pad regions for the piezoelectric material. In an example, the method includes a shallow etch process that etches into a substrate (which may be silicon, for example). In an example, the method coats the backside with photoresist to open and expose a backside region of the piezoelectric material, which exposes an entire film region including the enclosed piezoelectric material and the bond pad region. In an example, the method also performs etching until the piezoelectric material and the bond pad are exposed. In an example, as described further below, a "rib" support is a feature that results from a two-step process, although variations may exist.

In an example, the backside is patterned with photoresist to align the backside pad metal (electrode #2), interconnects, and bond pads. In the examples, H is used with diluted HCl₂A cleaning process of O (1:1) or other suitable process to treat the backside. In an example, if the backside of the wafer is patterned with metal in an alternative manner rather than a large area layered deposition, the method further includes depositing about 3000A of Mo metal in selected areas. In an example, metal is formed to reduce parasitic capacitance and enable backside routing for circuit implementation, which is beneficial for different circuit node interconnects. In an example, if desired, a thin titanium bond metal may be deposited as a bond material before Mo

In an example, the method further includes, for mechanical stability, forming a dielectric passivation (25 μm spin polymer photo-dielectric (e.g., ELECTRA WLP SH32-1-1)) of the backside surface. In an example, in an alternative example, the method comprises depositing SiN and/or SiO₂to fill the backside trench regions to provide suitable protection, isolation, and to provide other features, if desired.

In an example, the method then separates and/or unloads the completed substrate for transfer into a wafer carrier. The completed substrate has a plurality of devices and an overlying protective material. In an example, the substrate is now ready for sawing and severing as well as other back end processes, such as wafer level packaging, or other techniques. Of course, there can be other variations, modifications, and alternatives.

Fig. 23 shows a circuit diagram of a single crystal acoustic resonator device in an example of the present invention. This diagram is merely an example, and should not unduly limit the scope of the claims herein. The circuit 2301 shows a block diagram with a piezoelectric film 2322, the piezoelectric film 2322 being sandwiched between a first upper electrode 2361 and a second upper electrode 2362. The connection region 2303 of the block diagram 2301 is shown in a circuit diagram 2302, which shows an equivalent circuit configuration.

Fig. 24 to 32 show a manufacturing method for a single crystal acoustic resonator device in an example of the present invention. This diagram is merely an example, and should not unduly limit the scope of the claims herein.

An example of an alternative manufacturing process can be briefly described as follows:

1. starting;

3. Treating the surface region in preparation for epitaxial growth;

5. Patterning the epitaxial material using a mask and an etch process to form a trench region by causing formation of an exposed portion of the surface region by means of a pattern provided in the epitaxial material; alternatively, patterning of the epitaxial material may also occur using laser drilling techniques;

8. Masking and removing (by etching) a portion of the substrate from the backside to form a single trench region exposing a backside of the epitaxial material covering the first electrode member and exposing a backside of the bond pad metal; a two-step masking and etching process may be used to form shallow "rib" structures with the goal of providing mechanical support for the epitaxial material;

10. Forming a resonator active region having a low surface leakage current using a passivation process that electrically and spatially isolates the first electrode member from the upper second electrode member while also trimming the resonant capacitor; dielectric passivation layer (such as SiN or SiO) is deposited by PECVD technique in controlled temperature and pressure environment using silane gas₂) To control the refractive dielectric index;

11. Forming a protective dielectric material (options include SiO) covering the upper surface region on the upper surface₂SiN, or spin-on polymer coating); and

12. Other steps are performed as needed.

As shown in fig. 24, the method begins by providing a substrate member 2410. The backing member has a surface area, in an example 400 μm thick, which may have a diameter of 150mm or 200mm diameter material, although variations from 50mm to 300mm may exist.

In an example, a surface region of a substrate member is processed. The treatment typically includes cleaning and/or conditioning. In an example, the treatment takes place in a MOCVD or LPCVD reactor having ammonia gas flowing at high temperature (e.g., in the range from 940 ℃ to 1100 ℃) and at pressures ranging from one tenth of atmospheric pressure to one atmosphere.

In an example, the method includes forming an epitaxial material, which as shown includes a single crystal piezoelectric material 2420 covering a surface region to a desired thickness (t). Trimethyl gallium (TMG), trimethyl aluminum (TMA), ammonia (NH) gas are used₃) And hydrogen (H)₂) The epitaxial material is grown to a thickness in the range of 0.4 μm to 7.0 μm at a high temperature in the range of 940 ℃ to 1100 ℃ in an atmosphere controlled environment using an MOCVD or LPCVD growth apparatus, depending on the target resonance frequency of the capacitor device. The material also has a thickness of 10 per square centimeter⁴To 10¹²The defect density of (2).

In an example, the epitaxial material 2521 is patterned (fig. 25). Patterning involves masking and etching processes. The mask is typically 1 μm to 3 μm photoresist. Chlorine-based chemical reactions (gases may include BCl) in RIE or ICP etching tools under controlled temperature and pressure conditions₃、Cl₂And/or argon) to adjust the etch rate and sidewall profile. The patterning forms the trench regions (or via structures) by causing the formation of exposed portions of the surface region by means of a pattern provided in the epitaxial material.

In an example, the method forms an upper side bond pad metal 2630 (fig. 26), which may include a stack with a metal layer that reacts slowly with an etchant in a backside substrate etching process, as defined below. In examples, the metal is a refractory metal (such as tantalum, molybdenum, tungsten) or other metal (such as gold, aluminum, titanium, or platinum). As noted, this metal is then used as a stop region for the backside etch process.

in an example, the method forms an upper side metal structure (fig. 27). As shown, the structure has an upper electrode member that includes a first electrode member 2741 covering a portion of the epitaxial material and a second electrode member 2742 covering the upper bond pad metal. The metal structure is made using a refractory metal (such as tantalum, molybdenum, tungsten) and has a thickness of 300nm, selected to define the resonant frequency of the capacitor device.

In an example, the method performs backside processing by flipping the substrate upside down (fig. 28). In an example, the method includes a patterning process of a backside of the substrate 2811. The process uses a masking and removal process by etching a portion of the substrate from the backside to form a first trench region exposing the backside of the epitaxial material covering the first electrode member and a second trench region exposing the backside of the bond pad metal. Support member 2821 may be disposed between two trench regions. In an example, the support member may be recessed from the bottom surface area, although variations may exist. In an example, a chlorine-based gas is used in a RIE or ICP reactor and etching is performed at a temperature and pressure defined to control the etch rate, selectivity, and sidewall slope.

next, the method includes forming a backside resonator metal material 2943 (fig. 29) for the second electrode overlying the exposed portion of the epitaxial material (or piezoelectric film) to form a connection from the epitaxial material to the backside of the bond pad metal coupled to the second electrode member overlying the upper side bond pad metal.

as shown in the figure, the piezoelectric film 2921 is sandwiched between the pair of electrodes arranged from the upper side and the back side of the substrate member. The member is a <111> oriented silicon substrate having a resistivity greater than 10 ohm-cm.

In an example, the method forms or patterns the resonator active region using a mask and etch process. The ultimate goal is to electrically and spatially isolate the first electrode member from the second electrode member on the upper side while also trimming the resonant capacitor. In the example, the resonator active area is 200 μm × 200 μm. Patterning uses a chlorine-based RIE or ICP etching technique.

The method forms a passivation layer 3050 (fig. 30) and a thickness of protective material 3170 (fig. 31). In an example, the method forms a combination of silicon dioxide (which forms a specification compliant structure) and an overlying silicon nitride cap material. Silicon dioxide and silicon nitride materials are formed using a combination of silane, nitrogen, and oxygen sources and are deposited using a PECVD chamber.

The method forms a first electrode 3261 and a second electrode 3262 electrically coupled to the first upper electrode 3241 and the second upper electrode 3242, respectively (fig. 32). The intrinsic device is labeled 3201. In an example, the method may also include other steps or other materials, as desired.

In an example, the method may further comprise one or more of these processes for forming the upper electrode structure, the passivation material and the backside treatment. In an example, the present substrate including the capping structure can include a surface cleaner that uses HCl: h₂O (1:1) for a predetermined amount of time, then rinsed and placed in the sputtering tool.

In a sputtering tool for forming electrode metallization, the method includes using molybdenum (Mo) metal of a sputtering technique on an exposed upper side of a single crystal piezoelectric materialand depositing a covering layer. In an example, if desired, a thin titanium bond metal may be deposited prior to forming the Mo metalAmong other features, such titanium metals are used as adhesion layers. In an example, the method performs a masking and patterning process to etch away Mo in the field region (leaving Mo in the probe pad, coplanar waveguide (CPW) interconnect, top plate/first electrode, via bond pad/second electrode, and alignment mask regions). In an example, titanium-aluminumIs deposited on the Mo metal in the probe disk and CPW areas. In an example, Ti/Al is formed on the bond pads for subsequent deposition of copper-tin metal posts-CuSn posts and die cuts for wafer level flip chip packaging are deposited. In an example, the method forms a dielectric passivation of the upper side surface (25 μm spin polymer photo-dielectric (ELECTRA WLP SH32-1-1)), or alternatively, SiN or SiO₂Is formed to cover the upper surface.

In an example, a substrate is disposed on a flip-chip wafer and mounted (using photoresist) to a carrier wafer to begin a backside process. In an example, the backside processing uses a multi-step (e.g., two-step) process. In an example, the wafer is thinned from about 500 μm to about 300 μm and less using a backside grinding process, which may further include polishing and cleaning. In an example, the backside is coated with a masking material (such as photoresist) and patterned to open trench regions and bond pad regions for the piezoelectric material. In an example, the method includes a shallow etch process that etches into a substrate (which may be silicon, for example). In an example, the method coats the backside with photoresist to open and expose a backside region of the piezoelectric material, which exposes an entire film region including the enclosed piezoelectric material and the bond pad region. In an example, the method also performs etching until the piezoelectric material and the bond pad are exposed. In an example, the "rib" support is a feature derived from a two-step process, although variations may exist.

Fig. 33 shows a circuit diagram of a single crystal acoustic resonator device in an example of the invention. This diagram is merely an example, and should not unduly limit the scope of the claims herein. Circuit 3301 shows a block diagram with a piezoelectric film 3322, the piezoelectric film 3322 being sandwiched between a first upper electrode 3361 and a second upper electrode 3362. The connection region 3303 of the block diagram 3301 is shown in the circuit diagram 3302, which circuit diagram 3302 shows an equivalent circuit configuration.

In an example, the present disclosure shows an acoustic reflector structure, which may be added only if needed or desired. In an example, an acoustic reflector on a Single Crystal Acoustic Resonator (SCAR) device may provide improved acoustic coupling, so-called K². In conventional BAW devices, the acoustic resonator is inserted into the substrate/carrier material, which, although used, can be bulky and ineffective. In an example, because a portion of the substrate is removed from the back side of the single crystal piezoelectric material of the device, an acoustic reflector may not be needed or desired on either side of the acoustic resonator. However, in contrast to conventional bulk acoustic wave devices in which the reflector is integrated in the substrate, the acoustic reflector is integrated on the upper side of the device, which may serve two functions, among others: (i) reduce humidity sensitivity to SCAR equipment, and (ii) provideAcoustic isolation of the filter device from the surrounding environment (similar to a faraday cage). These and further features may be found throughout the present specification and more particularly below.

Fig. 34 and 35 show reflector structures 3400, 3500 configured on a single crystal acoustic resonator device in an example of the invention. As shown, the device has similar features to the device of the previous examples (fig. 14-22). In addition, the device is configured with a reflector structure comprising alternating quarter wave layers of high acoustic impedance material 3452, 3552 (e.g. metal such as Mo, W, Cu, Ta) and low impedance material 3451, 3551 (e.g. dielectric such as to form an acoustic reflector over the acoustic resonator device). Fig. 35 also shows a first electrode 3561 coupled horizontally to the first upper electrode 3541 and a second electrode 3562 coupled vertically to the second upper electrode 3542. The intrinsic device is labeled 3501. Of course, there can be other variations, modifications, and alternatives.

Fig. 36 shows a circuit diagram of a reflector structure integrated with the single crystal acoustic resonator device in the above figures. This diagram is merely an example, which should not unduly limit the scope of the claims herein. As shown, circuit 3601 is a block diagram having a piezoelectric film 3622, the piezoelectric film 3622 being sandwiched between a first upper electrode 3661 and a second upper electrode 3662. The connection region 3603 of the block diagram 3601 is shown in a circuit diagram 3602, which circuit diagram 3602 shows an equivalent circuit configuration.

In an example, the present invention may provide an acoustic resonator device that includes a bulk substrate member and has a surface region and a thickness of material. In an example, a bulk substrate has a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region.

In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface region. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region, and a contact region configured with a second recessed region. The apparatus has a first electrode member formed to cover an upper portion of the thickness of the single crystal piezoelectric material, and a second electrode member formed to cover a lower portion of the thickness of the single crystal piezoelectric material so as to sandwich the thickness of the single crystal piezoelectric material with the first electrode member and the second electrode member. In an example, the second electrode member extends from a lower portion including the exposed backside region to the contact region. In an example, the device has a second electrode structure configured with a contact area and a first electrode structure configured with a first electrode member.

As shown, the device also has a dielectric material covering an upper surface region of a forming structure that covers the bulk substrate member. The apparatus has an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member. As shown, the acoustic reflector structure has a plurality of quarter-wave layers spatially disposed within a dielectric material.

Fig. 37 and 38 show reflector structures 3700, 3800 configured on a single crystal acoustic resonator device in an example of the invention. This diagram is merely an example, and should not unduly limit the scope of the claims herein. As shown, the device has similar features to the device of the previous example (fig. 24-32). In addition, the device is configured with a reflector structure comprising alternating quarter wave layers of high acoustic impedance material 3752, 3852 (e.g. metal such as Mo, W, Cu, Ta) and low impedance material 3751, 3752 (e.g. dielectric such as to form an acoustic reflector over the acoustic resonator device). Fig. 38 also shows a first electrode 3861 coupled horizontally to the first upper electrode 3841 and a second electrode 3862 coupled vertically to the second upper electrode 3842. The intrinsic device is labeled 3801. Of course, there can be other variations, modifications, and alternatives.

fig. 39 shows a circuit diagram of a reflector structure integrated with the single crystal acoustic resonator device of the above figures. This diagram is merely an example, and should not unduly limit the scope of the claims herein. As shown, the circuit 3901 is a block diagram having a piezoelectric film 3922, the piezoelectric film 3922 being sandwiched between a first upper electrode 3961 and a second upper electrode 3962. The connection region 3903 of the block diagram 3901 is shown in a circuit diagram 3902, which circuit diagram 3902 shows an equivalent circuit configuration.

In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface region. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region, and a contact region configured with a second recessed region. The device has a first electrode member formed to cover an upper portion of the thickness of the single crystal piezoelectric material and a second electrode member formed to cover a lower portion of the thickness of the single crystal piezoelectric material so as to sandwich the thickness of the single crystal piezoelectric material with the first electrode member and the second electrode member. In an example, the second electrode member extends from a lower portion including the exposed backside region to the contact region. In an example, the device has a second electrode structure configured with a contact area and a first electrode structure configured with a first electrode member.

Fig. 40 shows a simplified diagram of the bottom surface region and the top surface region of a single crystal acoustic resonator device in an example of the invention. As shown, fig. 40 includes a top view 4001 and a bottom view 4003, each having a corresponding cross-sectional view 4002 and 4004, respectively. These views show a resonator device similar to the one described before. A piezoelectric film 4020 is disposed so as to cover the substrate 4010. The upper side of the device includes a first upper electrode 4041 and a second lower electrode 4042. The etched underside of the substrate includes a lower electrode 4043. Of course, there can be variations, modifications, and alternatives.

Fig. 41 and 44 show simplified examples of single crystal acoustic resonator devices configured in a filter ladder network in an example of the invention. This diagram is merely an example, and should not unduly limit the scope of the claims herein. In an example, the following description provides illustrations and manufacturing processes for manufacturing together, two or more resonators to create a SCAR filter, among other elements.

referring to fig. 41, as shown, the method begins with taking a physical implementation for the SCAR device 4100 (details found in fig. 22) and converting to circuit elements 4102. The circuit element comprises a first electrode 4161, a second electrode 4162, and a resonant circuit device 4101 between the two electrodes. In an example, each acoustic resonator device includes a bulk substrate structure having a surface region, and a thickness of material. In an example, a bulk substrate structure has first and second recessed regions and a support member disposed between the first and second recessed regions. Of course, variations are possible.

In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface region. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region, and a contact region configured with a second recessed region. In an example, the single crystal piezoelectric material has a thickness greater than 0.4 microns, although variations may exist. In an example, the single crystal piezoelectric material is characterized by less than 10¹²Defect/cm²Although variations may exist.

In an example, the device has a first electrode member formed to cover an upper portion of the thickness of single crystal piezoelectric material, and a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from a lower portion including the exposed backside region to the contact region. In an example, the second electrode structure is configured with a contact area and the first electrode structure is configured with a first electrode member. In an example, the device also has a dielectric material covering an upper surface region of a forming structure covering the substrate member and an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member.

Alternatively, the apparatus may include any of the other aforementioned features and others. Of course, there can be other variations, modifications, and alternatives. Further details of this example may be found throughout the present specification and more particularly below.

Referring to fig. 42, a series-shunt configuration 4200 of circuit elements R1, R2, R3, R4, R5, R6, and R7 is shown, although variations and modifications may exist. That is, the configuration may include a greater number of resonators or fewer resonators, depending on the example. As shown, the illustrated configuration is a ladder network of filters for use in an acoustic filter comprised of a series shunt configuration SCAR.

Referring now to fig. 43, a monolithic filter ladder network has a plurality of single crystal acoustic resonator devices designated R1, R2, R3, R4, R5, R6, and R7 disposed on a common substrate member. The circuit diagram 4300 corresponds to the device configuration 4301. Of course, there may be a greater number or fewer devices that have been configured together.

In an example, each acoustic resonator device includes a bulk substrate structure having a surface region, and a thickness of material. In an example, a bulk substrate structure has first and second recessed regions, and a support member disposed between the first and second recessed regions. Of course, variations are possible.

In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface region. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region and a contact region configured with a second recessed region. In an example, the single crystal piezoelectric material has a thickness greater than 0.4 microns, although variations may exist. In an example, a single crystal piezoelectric materialIs characterized by being less than 10¹²Defect/cm²although variations may exist.

In an example, the device has a first electrode member formed to cover an upper portion of the thickness of single crystal piezoelectric material, and a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from a lower portion including the exposed backside region to the contact region. In an example, the second electrode structure is configured with a contact area and the first electrode structure is configured with a first electrode member. In an example, the device also has a dielectric material covering an upper surface region of a forming structure covering the substrate member and an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member. Alternatively, the apparatus may comprise any of the other aforementioned features or others.

As shown, R1, R3, R5, and R7 are configured in a series manner such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, and the second electrode structure of R5 is coupled to the first electrode structure of R7. The circuit also includes a first node disposed between the second electrode structure of R2 and the first electrode structure of R3, a second node disposed between the second electrode structure of R3 and the first electrode structure of R5, and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7.

In an example, R2 is configured between the first node and the lower common electrode such that the first electrode structure of R2 is connected to the first node and the second electrode structure of R2 is connected to the lower common electrode. In an example, R4 is configured between the second node and the lower common electrode such that the first electrode structure is connected to the second node and the second electrode structure is connected to the lower common electrode. In an example, R6 is configured between the third node and the lower common electrode such that the first electrode structure of R6 is connected to the third node and the second electrode structure of R6 is connected to the lower common electrode.

In the example, assuming that a single device has two electrodes on the upper surface (or common side) due to the use of backside vias (from the backside electrode 2 to the upper side electrode 2), the present circuit is routed accordingly to each SCAR device having backside vias, as shown at the upper right. In an example, 7 backside vias are included, which can consume a larger portion of the substrate structure. Further examples of the present circuit arrangement may be found throughout the present specification and more particularly below.

Referring to fig. 44, the following illustration shows a filter configuration with reduced or even minimal use of vias to save substrate area. Circuit diagram 4400 corresponds to device configuration 4401. In the example, the value range for the filter configuration is from 7 down to 1, or a single via (shown on the right). In an example, the present illustration uses the following boundary conditions: (1) the input of R1 and the output of R7 are arranged such that they are both upper side node 1; (2) maximizing the number of internal nodes, which use common nodes; and (3) the common node (bottom of R2, R4, R6) is combined at the upper surface of the substrate. As shown, only a single via is included, which results in cost, process, and substrate area savings. Of course, there are a number of examples that may range from a single via to 7 vias or more.

In an example, the second electrode is shared on a common internal node using backside connections and metallization. In an example, the first electrodes are shared using an upper side connection that couples the respective first electrodes together. In an example, only R4 has a via structure that is coupled to the lower common electrode member. Of course, there can be variations, modifications, and alternatives. In an example, fewer vias result in less parasitic capacitance or other loading, and reduce processing, as well as improve substrate utilization, which is beneficial for manufacturing highly integrated devices.

Fig. 45-52 show simplified examples of a two-element single crystal acoustic resonator device and a three-element single crystal acoustic resonator device according to examples of the present invention. This diagram is merely an example, and should not unduly limit the scope of the claims herein. In an example, the following description provides illustrations of two-element or three-element SCAR devices that are used at the circuit level to implement filters. In an example, some devices do not include a via structure, which is beneficial and more efficient.

Referring to fig. 45, a diagram illustrates a filter ladder structure 4500 as previously discussed, which filter ladder structure 4500 may be configured by a two-element device, R1, R2, R3, R4, R5, R6, and R7 in an example. As shown, in an example, R1 and R2 can be configured to form a series-shunted two-element device 4501. As shown, in an example, R6 and R7 can be configured to form a series-shunted two-element device 4502. Of course, other variations are possible.

Referring to fig. 46, a diagram shows the same filter ladder structure 4600 previously discussed, in an example, the filter ladder structure 4600 can be configured as a three-element "Y" device and a "Pi" device. In an example, R1, R2, and R3 may be configured to make up a series-shunt-series "Y" element SCAR device 4601. In an example, R4, R5, and R6 may be configured to constitute a split-series-split three-element "Pi" SCAR device 4602. In an example, other three-element "Y" and "Pi" SCAR devices may be constructed from the network, e.g., R5-R6-R7 make up the "Y" device and R2-R3-R4 make up the "Pi" device. Of course, there may be other alternatives, modifications, and variations. In the example with reference to fig. 47, the vias or any desired count that may provide the lowest count in the SCAR filter is illustrated, depending on the implementation. Fig. 47 may show a configuration (4700/4701) similar to the configuration (4400/4401) shown in fig. 44. Further details of this example may be found throughout the present specification and more particularly below.

In an example, the description shows a series-shunt two-element three-terminal scarr device by way of fig. 48. In an example, R1 and R2 as noted may be configured by two simple SCAR structures, among other combinations. In an example, such a two-element device 4801 has no through-hole, but two terminals (including T1, T2) on the upper side of the substrate member, and a third terminal (T3) on the back side of the substrate. In an example, the description shows a shunt-series two-element three-terminal scarr device 4800. In the example, referring from left to right to R1 to R2, a series-shunt device is shown. From right to left, a shunt-series device is shown and has the same physical structure as the previous devices. Of course, there can be other variations, modifications, and alternatives.

Referring now to fig. 49, this description shows a "Y" three terminal scarr device without a via structure, which reduces the size of the device. As shown and described, in an example, among other combinations, R1, R2, and R3 form a three-element three-terminal "Y" configured SCAR device 4900. Examples of this type have significant features such as a through-hole-less structure, T1, T2, T3 being connections for bonding wires arranged on the upper side of the substrate member. In an example, the device also has node two (2), which is common to R1, R2, and R3 and is configured "internally" and connected on the backside of the substrate member. In an example, the plant is in a series split series configuration and has three separate SCAR regions corresponding to the three plants making up the "Y" configuration plant.

Referring now to fig. 50, this description shows a "Y" three terminal scarr device with a single via structure, which reduces the size of the device. As shown and described, in an example, among other combinations, R3, R4, and R5 form a three-element, three-terminal "Y" configured SCAR device 5000. Such examples have significant features, such as a single via on the back side that connects to the front or upper side of the substrate member. In an example, the device also has T1 and T2 contacts configured to and accessible to the back side of the substrate. The T3 is configured to and accessible to the front side of the substrate. Node one (1), common to R3, R4, and R5, is disposed "internally" and connected on the front side of the substrate member. In an example, the plant is in a series split series configuration and has three separate SCAR regions corresponding to the three plants making up the "Y" configuration plant.

Referring to fig. 51, in an example, the description shows a "Pi" three-terminal SCAR device having a single via structure. As shown, among other combinations, R2, R3, and R4 form a three-element three-terminal "Pi" configuration SCAR device 5100. Such devices have significant features such as a single backside via structure for routing backside connections to the front side of the substrate. In an example, node two (2) for each of device R2 and device R3 are connected to each other on the backside and form terminal 1 (T1). In an example, terminal 3 (which is T3) is a contact accessible to the front side of the substrate. In an example, node one (1) for each of devices R3 and R4 is configured to and connected on the front side and forms terminal 2 (T2). In an example, the apparatus is a split-flow, series-split configuration. In an example, the apparatus includes three separate scarr regions corresponding to three apparatuses forming three (3) elements forming and making up a "Pi" configuration. Shown is a simplified illustration of a split series split three (3) element three terminal "Pi" SCAR device having a single through hole configuration on the R4 split branch or member. Of course, there may be variations, alternatives, and modifications.

Referring to fig. 52, in an example, the description shows a "Pi" three terminal SCAR device having two (2) backside via structures. As shown, the device has been described in the previous example, however, in this example, the present device has an additional via on terminal 1(T1), which terminal 1 is configured to the contact area from the back side to the front side. In an example, the device has significant features, such as two (2) backside via structures for routing the backside contact area to connect to the front side of the substrate. In an example, the device has a node two (2) for each device element R2 and R3, the nodes two (2) being connected to each other on the back side and then routed to the front side of the substrate using a via structure to form terminal 1 (T1). In an example, terminal 3(T3) is configured to be accessible to a contact on the front side of the submount substrate. In the example, the node 1(1) for each device element R3 and R4 is configured to and connected on the front side and forms the terminal 2 (T2). In an example, the apparatus provides a split series split configuration. In addition, the apparatus includes the use of three separate SCAR regions associated with the apparatuses that form and constitute a "Pi" configuration. In the example shown is a shunt series shunt three-element three-terminal "Pi" SCAR device 5200, the SCAR device 5200 having a single via on the R4 shunt branch and a single via structure 1, the single via structure 1 connecting the internal node two (2) for the configured R2 and R3 and having the T1 connected to the front side of the substrate.

While the above is a complete description of the specific embodiments, various modifications, alternative constructions, and equivalents may be used. Accordingly, the above description and drawings should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A monolithic filter ladder network, comprising:

A plurality of single crystal acoustic resonator devices, numbered from R1 to RN, disposed on a common substrate member, wherein N is an integer greater than 1, each said acoustic resonator device comprising:

a bulk substrate structure having a surface region and a thickness of material, the bulk substrate structure having a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region;

A thickness of single crystal piezoelectric material formed to cover the surface region, the thickness of single crystal piezoelectric material having an exposed backside region configured with the first recessed region and a contact region configured with the second recessed region, the single crystal piezoelectric material having a thickness greater than 0.4 microns, the single crystal piezoelectric material characterized by less than 10¹²Defect/cm²dislocation density of (a);

A first electrode member formed to cover an upper portion of the thickness of the single crystal piezoelectric material;

a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region;

A second electrode structure provided with the contact area;

a first electrode structure provided with the first electrode member;

A dielectric material covering an upper surface region of a forming structure, the forming structure covering the bulk substrate structure; and

An acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member.

2. The monolithic filter ladder network of claim 1, wherein the support members are arranged in a plane coincident with a bottom surface region of the bulk substrate structure.

3. the monolithic filter ladder network of claim 1, wherein the support members are arranged in planes that are offset and recessed relative to a bottom surface region of the bulk substrate structure.

4. the monolithic filter ladder network of claim 1, wherein the single crystal piezoelectric material is characterized by X-ray diffraction with a sharp peak at a detector angle associated with the single crystal film, and a full width at half maximum (FWHM) of the single crystal piezoelectric material is measured to be less than 1.0 °.

5. The monolithic filter ladder network of claim 1, wherein N is at least equal to 7, R1, R3, R5, and R7 are configured in a series manner such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, the second electrode structure of R5 is coupled to the first electrode structure of R7; the apparatus further comprises: a first node disposed between the second electrode structure of R2 and the first electrode structure of R3; a second node disposed between the second electrode structure of R3 and the first electrode structure of R5; and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7.

6. The monolithic filter ladder network of claim 1, wherein N is at least equal to 7, R1, R3, R5, and R7 are configured in a series manner such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, the second electrode structure of R5 is coupled to the first electrode structure of R7; the apparatus further comprises: a first node disposed between the second electrode structure of R2 and the first electrode structure of R3; a second node disposed between the second electrode structure of R3 and the first electrode structure of R5; and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7; wherein R2 is disposed between the first node and a lower common electrode; r4 is disposed between the second node and the lower common electrode; and R6 is disposed between the third node and the lower common electrode.

7. The monolithic filter ladder network of claim 1, wherein N is at least equal to 7, R1, R3, R5, and R7 are configured in a series manner such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, and the second electrode structure of R5 is coupled to the first electrode structure of R7; the apparatus further comprises: a first node disposed between the second electrode structure of R2 and the first electrode structure of R3; a second node disposed between the second electrode structure of R3 and the first electrode structure of R5; and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7; wherein R2 is configured between the first node and a lower common electrode such that the first electrode structure of R2 is connected to the first node and the second electrode structure of R2 is connected to the lower common electrode; r4 is configured between the second node and the lower common electrode such that the first electrode structure is connected to the second node and the second electrode structure is connected to the lower common electrode; and R6 is configured between the third node and the lower common electrode such that the first electrode structure of R6 is connected to the third node and the second electrode structure of R6 is connected to the lower common electrode.

8. The monolithic filter ladder network of claim 1, wherein N is at least equal to 7, and R1, R2, and R3 are configured to share a first common node; wherein R5, R6, and R7 are configured to share the first common node; wherein R1, R2, and R3 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a second common node; and R4 is configured to share the first common node.

9. The monolithic filter ladder network of claim 1, wherein at least one of the plurality of acoustic resonator devices comprising R1, R2, R3, R4, R5, R6, or R7 comprises a via structure for a contact structure.

10. The monolithic filter ladder network of claim 1, wherein N is at least equal to 7, and R1, R2, and R3 are configured to share a first common node; wherein R5, R6, and R7 are configured to share the first common node; wherein R1, R2, and R3 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a second common node; r4 is configured to share the first common node; and R4 is configured with a via structure coupled to the first common node.

11. The monolithic filter ladder network of claim 1, wherein the thickness of single crystal piezoelectric material is selected from at least one of AlN, AlGaN, InN, BN, and other group iii-nitrides.

12. The monolithic filter ladder network of claim 1, wherein the thickness of single crystal piezoelectric material is selected from at least one of single crystal oxides including high-K dielectrics, ZnO, and MgO.

13. The monolithic filter ladder network of claim 1, wherein each of the first and second electrode structures is selected from one of tantalum and molybdenum; wherein the bulk substrate structure is selected from silicon, gallium arsenide, gallium nitride, aluminum nitride, and aluminum oxide.

14. A configurable monolithic filter ladder network, comprising:

A plurality of Single Crystal Acoustic Resonator (SCAR) devices numbered from R1 to RN disposed on a common substrate member, wherein N is an integer greater than 1, each of said acoustic resonator devices comprising:

a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region; and

A second electrode structure provided with the contact area;

A first electrode structure provided with the first electrode member;

a dielectric material covering an upper surface region of a forming structure, the forming structure covering the bulk substrate structure.

15. the configurable monolithic filter ladder network of claim 14 wherein N is at least equal to 7; wherein R1 and R2 are configured to form a series split first two-element device; and R6 and R7 are configured to form a series split second two-element device.

16. The configurable monolithic filter ladder network of claim 14 wherein N is at least equal to 7; and wherein R1, R2 and R3 are configured to constitute a first series-shunt-series Y-element SCAR apparatus; and R4, R5, and R6 are configured as a component shunt-series-shunt three-element Pi SCAR device.

17. The configurable monolithic filter ladder network of claim 14 wherein the thickness of single crystal piezoelectric material is selected from at least one of AlN, AlGaN, InN, BN, and other group iii-nitrides.

18. The configurable monolithic filter ladder network of claim 14, wherein the thickness of single crystal piezoelectric material is selected from at least one of single crystal oxides including high-K dielectrics, ZnO, and MgO.

19. The configurable monolithic filter ladder network of claim 14, wherein each of the first and second electrode structures is selected from one of tantalum and molybdenum; wherein the bulk substrate structure is selected from silicon, gallium arsenide, gallium nitride, aluminum nitride, and aluminum oxide.

20. A single crystal acousto-electronic device comprising:

A substrate having a surface region;

A first electrode material coupled to a portion of the substrate;

A single crystal capacitor dielectric material having a thickness greater than 0.4 micronsAnd covering the exposed portion of the surface region and coupled to the first electrode material, the single crystal capacitor dielectric material characterized by less than 10¹²Defect/cm²Dislocation density of (a); and

A second electrode material overlying the single crystal capacitor dielectric material,

Wherein the first electrode material comprises a first electrode structure configured and routed to a vicinity of a plane parallel to a contact area coupled to the second electrode material.

21. The apparatus of claim 20 wherein the single crystal capacitor dielectric material is selected from at least one of AlN, AlGaN, InN, BN, and other group iii nitrides.

22. The device of claim 20 wherein the single crystal capacitor dielectric material is selected from at least one of single crystal oxides including high K dielectrics, ZnO, and MgO.

23. The device of claim 20, wherein the single crystal capacitor dielectric material is configured to be in a first strain state to compensate for the substrate; wherein the single crystal capacitor dielectric material is arranged to cover the exposed portion of the substrate.

24. The device of claim 20, wherein the first electrode material is configured with a backside of the substrate and is coupled to the single-crystal capacitor dielectric material through a via structure configured on the backside of the substrate.

25. The device of claim 20, wherein the first electrode material is configured with a backside of the substrate, the configuration comprising a via structure configured within a thickness of the substrate.

26. The apparatus of claim 20, wherein the surface region is configured at an offset angle.

27. The device of claim 20, further comprising a reflector region configured to the first electrode material.

28. the device of claim 20, further comprising a reflector region configured to the second electrode material; wherein each of the first electrode material and the second electrode material is selected from refractory metals.

29. The device of claim 20, wherein each of the first and second electrode materials is selected from one of tantalum and molybdenum.

30. The device of claim 20 wherein the first electrode material and the single crystal capacitor dielectric material comprise a first interface region substantially free of oxide-containing material.

31. the device of claim 30 wherein the first electrode material and the single crystal capacitor dielectric material comprise a second interface region substantially free of oxide-containing material.

32. The device of claim 20, further comprising a nucleation material disposed between the single crystal capacitor dielectric material and the first electrode material; and the device further comprises a cap material disposed between the single crystal capacitor dielectric material and the second electrode material.

33. The apparatus of claim 20 wherein the single crystal capacitor dielectric material is characterized by a FWHM of less than one degree; and the device further comprises parameters derived from the two-port analysis.

34. The apparatus of claim 20, wherein the surface region of the substrate is bare and exposed crystalline material.

35. The device of claim 20, wherein the single crystal capacitor dielectric material is configured to propagate longitudinal signals at an acoustic speed of 6000 m/sec and greater; and the apparatus further comprises a first contact coupled to the first electrode material and a second contact coupled to the second electrode material such that each of the first and second contacts is configured in a coplanar arrangement.

36. The device of claim 20, wherein the substrate is selected from silicon, gallium arsenide, gallium nitride, aluminum oxide.