CN106549058A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN106549058A CN106549058A CN201510609662.3A CN201510609662A CN106549058A CN 106549058 A CN106549058 A CN 106549058A CN 201510609662 A CN201510609662 A CN 201510609662A CN 106549058 A CN106549058 A CN 106549058A
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- germanium silicon
- lamination
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 79
- 239000010703 silicon Substances 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 57
- 238000003475 lamination Methods 0.000 claims abstract description 25
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 16
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 74
- 229910052732 germanium Inorganic materials 0.000 claims description 28
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 21
- 239000002210 silicon-based material Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000003960 organic solvent Substances 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 3
- 239000002070 nanowire Substances 0.000 abstract description 18
- 238000005516 engineering process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000005293 physical law Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a FinFET manufacturing method, which forms a silicon/germanium-silicon lamination and removes one material to form a nanowire, wherein the silicon/germanium-silicon lamination is contained in a fin, the nanowire does not need to be supported by an extra pad, so that the difficulty of the process is reduced, and the wet etching process with high selection ratio can be used to remove one material without using a dry etching process due to the property difference of the silicon and the germanium-silicon, so that the process is further simplified; and the method is compatible with the conventional FinFET process, and the FinFET nanowire device can be simply, conveniently and effectively obtained.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, in particular to one kind
The manufacture method of FinFET semiconductor device.
Background technology
Over nearly 30 years, semiconductor device is always according to Moore's Law scaled down, quasiconductor collection
Characteristic size into circuit constantly reduces, and integrated level is improved constantly.As technology node enters deep
Within submicrometer field, such as 100nm, or even within 45nm, conventional field effect transistor
(FET), namely plane FET, start to meet with the restriction of various basic physical laws so as to
The prospect of scaled down is challenged.The FET of numerous new structures is developed, to answer
Demand to reality, wherein, FinFET is exactly a kind of new construction for having very much a scaled down potentiality
Device.
FinFET, FinFET is a kind of many gate semiconductor devices.Due to structure
On exclusive feature, FinFET becomes the device of deep submicron integrated circuit field very with prospects
Part.As its name suggests, FinFET includes that the Fin of a substrate perpendicular to body silicon, Fin are claimed
For fin or fin-shaped semiconductor column, different FinFET is separated by sti structure.It is different
In conventional plane FET, the channel region of FinFET is within Fin.Gate insulator and grid
Pole surrounds Fin in side and top surface, so as to form the grid at least two sides, i.e., positioned at the two of Fin
Grid on individual side；Meanwhile, by the thickness for controlling Fin so that FinFET has splendid
Characteristic：More preferable short-channel effect rejection ability, more preferable sub-threshold slope, relatively low pass
State electric current, eliminates floater effect, and lower running voltage is more beneficial for scaled.
Although FinFET has above-mentioned various advantages, yet suffer from that electric current is little, grid-control is weak
Situation.In order to solve the above problems, nano wire is considered as a kind of reasonable solution.
But the lithographic method that the method for routine forms nano wire is more complicated, with conventional FinFET works
Skill is simultaneously not bery compatible；Nano wire needs pad to be supported simultaneously.This causes technics comparing complicated,
Improve cost of manufacture
Accordingly, it is desirable to provide a kind of new FinFET manufacture methods, with easier and effective
Method forms nano wire.
The content of the invention
The present invention proposes a kind of FinFET manufacture methods, employs silicon/germanium silicon lamination and height
Select than etching technics, the FinFET with nano thread structure is manufactured with simple and effective.
The invention provides a kind of method, semi-conductor device manufacturing method, for manufacturing FinFET,
Comprise the steps：
For manufacturing FinFET, it is characterised in that comprise the steps：
Substrate is provided, and impurity layer is formed on the surface of the substrate；
Alternately laminated silicon/germanium silicon the lamination of silicon layer and germanium silicon layer is formed on the impurity layer；
By patterned process, fin is formed；
STI is formed in the fin both sides；
Form dummy gate oxide layer, dummy gate electrode storehouse, grid curb wall；
Form source drain extension area and source-drain area；
Comprehensive metallization medium layer, covers the dummy gate electrode storehouse；
Planarization process exposes the dummy gate electrode storehouse upper surface, and removes the illusory grid
Pole storehouse and the dummy gate oxide layer；
Remove the silicon or germanium silicon material in the silicon/germanium silicon lamination；
Form gate insulator and grid.
According to an aspect of the present invention, the impurity layer is injection over the substrate or outer
Prolong the layer that doping in situ is formed, which has and semiconductor device source-drain area to be made doping class
The contrary impurity of type；Between the impurity layer and the substrate, formation prevents impurity diffusion
Barrier layer；The barrier layer is element of the atomic number less than silicon, preferably carbon.
According to an aspect of the present invention, the top of the STI is higher than the silicon/germanium silicon lamination
Bottom.
According to an aspect of the present invention, the silicon or germanium in the silicon/germanium silicon lamination is removed
During silicon materials, silicon or germanium silicon material are removed using the technique of high etching selection ratio；Remove described
During silicon in silicon/germanium silicon lamination, using dry etching or wet etching；Using wet etching
When, select the organic solvent with hydroxyl, preferably TMAH.
It is an advantage of the current invention that：By forming silicon/germanium silicon lamination and removing one of which material
To form nano wire, among being contained in fin due to silicon/germanium silicon lamination, nano wire simultaneously need not
It is supported using extra pad, reduces the difficulty of technique, also, due to silicon and germanium silicon
Material property differences, can adopt high selectivity wet-etching technology remove one of which material
Material, and dry etch process need not be adopted, further simplify technique；And and invent side
Method and routine FinFET process compatibles, can obtain FinFET nano wire devices with simple and effective
Part.
Description of the drawings
The schematic flow sheet of the semiconductor making method that Fig. 1-10 present invention is provided.
Specific embodiment
Hereinafter, by the specific embodiment that illustrates in accompanying drawing describing the present invention.But should manage
Solution, these descriptions are simply exemplary, and are not intended to limit the scope of the present invention.Additionally,
In below illustrating, the description to known features and technology is eliminated, to avoid unnecessarily obscuring
Idea of the invention.
The present invention provides a kind of method, semi-conductor device manufacturing method, in particular to one kind
FinFET manufacture method.Below, referring to Figure of description, will be described in the present invention
The method, semi-conductor device manufacturing method of offer.
First, referring to accompanying drawing 1, there is provided substrate 1, impurity layer 2 is formed on the surface of substrate 1.
Substrate 1 can be needed and reasonable selection, including but not limited to body silicon substrate, SOI according to device application
Substrate, germanium substrate, germanium silicon (SiGe) substrate, such as compound semiconductor materials, gallium nitride
(GaN), GaAs (GaAs), indium phosphide (InP) etc..For with conventional semiconductors work
The consideration of skill compatibility and cost, the substrate 1 in the present embodiment are served as a contrast preferably by body silicon
Bottom.
The layer that impurity layer 2 is formed for injection on substrate 1 or extension doping in situ, which has
The impurity contrary with semiconductor device source-drain area doping type to be made.Further optionally,
Between impurity layer 2 and substrate 1, formation prevents the barrier layer (not shown) that impurity spreads.
Barrier layer can prevent the impurity element diffusion in impurity layer 2 and the doping for preventing in substrate 1
Elements Diffusion, can adopt and inject or be epitaxially formed on substrate 1.Barrier layer includes atom
Element of the ordinal number less than silicon, it is preferred to use carbon produces barrier effect.
Then, referring to Fig. 2, on impurity layer 2, form silicon layer and germanium silicon layer is alternately laminated
Silicon/germanium silicon lamination 3.Silicon/germanium silicon lamination 3 is preferably formed using epitaxy technique, and its bottom is
Silicon or germanium, in the embodiment of present invention diagram, employ germanium silicon layer for the bottom；It is optional
Embodiment in, silicon layer can be adopted for the bottom.Silicon/germanium silicon lamination 3 is for subsequent
The thickness that nano wire, every layer of silicon layer and germanium silicon layer are formed in technique is 2-50nm, preferably
5-15nm, the number of stacking are generally more than 3 layers, preferably 5 layers, i.e., bottom-up
Germanium silicon/silicon/germanium silicon/silicon/germanium silicon.
Referring to Fig. 3, which is side view, by patterned process, forms fin.Preferably,
Fin includes the protuberance 4 of silicon/germanium silicon lamination 3, impurity layer 2 and substrate 1.
Then, referring to Fig. 4, which is side view, forms sti structure 5 in fin both sides.Its
In, sti structure 5 is formed on substrate 1, using SiO2, the material such as SiON, specifically
Technique include but is not limited to PECVD, HDP-CVD, RTO (rapid thermal oxidation)
Deng.Preferably, bottom of the top of sti structure 5 higher than silicon/germanium silicon lamination 3, to realize receiving
Isolation between nanowire device.
After sti structure 5 is formed, referring to Fig. 5, dummy gate oxide layer 6 is formed, it is illusory
Stack 7, grid curb wall 8.Dummy gate oxide layer 6, dummy gate electrode storehouse 7, gate electrode side
8 lines of wall are typically intersected vertically with fin lines across on fin.Dummy gate oxide layer
6 is, for example, SiO2, the material of dummy gate electrode storehouse 7 is polysilicon or non-crystalline silicon etc., at this
In one embodiment of invention, non-crystalline silicon is employed.The concrete forming method bag of grid curb wall 8
Include：Deposited overall grid curb wall material, and be etched back, wherein, grid curb wall material bag
Include but be not limited to Si3N4。
Then, referring to Fig. 6, source drain extension area and source-drain area 9 are formed.Concrete technology includes
Except part silicon/3 material of germanium silicon lamination, source-drain electrode groove is formed, source drain extension area is then carried out
With the filling of source-drain area 9, for example with techniques such as extensions.Source drain extension area and source-drain area 9 are also
Silicide, or stress material can be adopted.
Referring to Fig. 7, comprehensive metallization medium layer 10 covers dummy gate electrode storehouse 7, gate electrode side
Wall 8 etc..10 material of dielectric layer is SiO2Deng.
Then, referring to Fig. 8, flatening process is adopted to process to expose dummy gate electrode storehouse 7
Upper surface, then, remove dummy gate electrode storehouse 7 and dummy gate oxide layer 6, to form grid
Pole groove 11.Gate recess 11 also expose the fin including silicon/germanium silicon lamination 3 top surface and
Side.
Referring to Fig. 9, via the gate recess 11 for exposing, remove in silicon/germanium silicon lamination 3
One of silicon or germanium silicon material.Preferably, using high selectivity etching technics, for example dry method or
Person's wet etching, removes silicon or germanium silicon.Wet etching is more electedly adopted, and does not adopt dry method to carve
Etching technique, can further Simplified flowsheet.Silicon materials are eliminated in the preferred embodiment of the invention,
When using wet etching, organic solvent of the selection with hydroxyl, preferably TMAH, this
In the case of, retain germanium silicon as nano wire, namely the channel region of device, germanium-silicon groove area can have
There is more preferable device performance；In an alternate embodiment of the invention, silicon can be retained with selective removal germanium silicon
Material.To eliminate the schematic diagram after silicon materials in Fig. 9, wherein diagonal line hatches are represented and are eliminated
The space formed after silicon materials.
Then, referring to Figure 10, gate insulator and grid 12 are formed.Gate insulator and grid
Pole 12 is HKMG, wherein, gate insulator adopts high-K gate insulating layer material, choosing
From one or a combination set of following material constitute one or more layers：Al2O3, HfO2, including
HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOxAnd HfLaSiOx
At least one in interior hafnio high K dielectric material, including ZrO2、La2O3、LaAlO3、
TiO2, or Y2O3At least one in interior rare earth base high K dielectric material.And the material of grid
For metal, alloy or metallic compound, such as TiN, TaN, W etc..Gate insulator and
Grid 12 surrounds remaining germanium silicon or silicon nanowires in silicon/germanium silicon lamination 3, so as to shaper
Part.To surround the schematic diagram of germanium silicon nanowires in Figure 10, its medium square shadow representation grid is exhausted
Edge layer and grid 12.
More than, the method, semi-conductor device manufacturing method of the present invention is illustrated.In the side of the present invention
In method, by forming silicon/germanium silicon lamination and removing one of which material to form nano wire, by
Among silicon/germanium silicon lamination is contained in fin, nano wire simultaneously need not be entered using extra pad
Row is supported, and reduces the difficulty of technique, also, due to silicon and the Material property differences of germanium silicon,
The wet-etching technology of high selectivity can be adopted to remove one of which material, and need not be using dry
Method etching technics, further simplify technique；And and the method and the routine FinFET that invent
Process compatible, can obtain FinFET nano-wire devices with simple and effective.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art
Member could be aware that without departing from the scope of the invention and device architecture and/or technological process made respectively
Plant suitable change and equivalents.Additionally, can be made by disclosed teaching many may fitting
In particular condition or material modification without deviating from the scope of the invention.Therefore, the purpose of the present invention
Do not lie in be limited to as realize the present invention preferred forms and disclosed specific reality
Example is applied, and disclosed device architecture and its manufacture method will include what is fallen within the scope of the present invention
All embodiments.
Claims (7)
1. a kind of method, semi-conductor device manufacturing method, for manufacturing FinFET, its feature exists
In comprising the steps：
Substrate is provided, and impurity layer is formed on the surface of the substrate；
Alternately laminated silicon/germanium silicon the lamination of silicon layer and germanium silicon layer is formed on the impurity layer；
By patterned process, fin is formed；
STI is formed in the fin both sides；
Form dummy gate oxide layer, dummy gate electrode storehouse, grid curb wall；
Form source drain extension area and source-drain area；
Comprehensive metallization medium layer, covers the dummy gate electrode storehouse；
Planarization process exposes the dummy gate electrode storehouse upper surface, and removes the illusory grid
Pole storehouse and the dummy gate oxide layer；
Remove the silicon or germanium silicon material in the silicon/germanium silicon lamination；
Form gate insulator and grid.
2. method according to claim 1, it is characterised in that the impurity layer is in institute
The layer that injection or extension doping in situ are formed on substrate is stated, which has partly is led with to make
The contrary impurity of body device source-drain area doping type.
3. method according to claim 2, it is characterised in that in the impurity layer and institute
State between substrate, formation prevents the barrier layer that impurity spreads.
4. method according to claim 3, it is characterised in that the barrier layer is atom
Element of the ordinal number less than silicon, preferably carbon.
5. method according to claim 1, it is characterised in that the top of the STI is high
In the bottom of the silicon/germanium silicon lamination.
6. method according to claim 1, it is characterised in that removing the silicon/germanium silicon
During silicon or germanium silicon material in lamination, silicon or germanium silicon are removed using the technique of high etching selection ratio
Material.
7. method according to claim 6, it is characterised in that remove the silicon/germanium silicon and fold
Layer in silicon when, using dry etching or wet etching；During using wet etching, tool is selected
There are the organic solvent of hydroxyl, preferably TMAH.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510609662.3A CN106549058A (en) | 2015-09-22 | 2015-09-22 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510609662.3A CN106549058A (en) | 2015-09-22 | 2015-09-22 | Semiconductor device manufacturing method |
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| CN106549058A true CN106549058A (en) | 2017-03-29 |
Family
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| CN103238208A (en) * | 2010-12-01 | 2013-08-07 | 英特尔公司 | Silicon and silicon germanium nanowire structures |
| US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
| CN104126228A (en) * | 2011-12-23 | 2014-10-29 | 英特尔公司 | Non-planar gate fully-enclosed device and method of making same |
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2015
- 2015-09-22 CN CN201510609662.3A patent/CN106549058A/en active Pending
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