CN106549046A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN106549046A CN106549046A CN201610796522.6A CN201610796522A CN106549046A CN 106549046 A CN106549046 A CN 106549046A CN 201610796522 A CN201610796522 A CN 201610796522A CN 106549046 A CN106549046 A CN 106549046A
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- virtual
- emitter stage
- semiconductor device
- gate
- emission lines
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000000994 depressogenic effect Effects 0.000 claims abstract description 22
- 238000012216 screening Methods 0.000 abstract description 13
- 239000011229 interlayer Substances 0.000 description 16
- 238000000034 method Methods 0.000 description 12
- 239000010410 layer Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000003139 buffering effect Effects 0.000 description 5
- 238000007689 inspection Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 208000011580 syndromic disease Diseases 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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Abstract
The present invention provides the semiconductor device of the screening that can carry out virtual groove.The semiconductor device that the present invention is provided possesses：Semiconductor substrate；Virtual groove, which is formed at the face side of semiconductor substrate；Emitter stage, which is formed at the top on the surface of semiconductor substrate, and forms depressed part with the periphery depression under overlooking；Virtual pad, which is electrically connected with virtual groove, is formed at the inner side of depressed part under vertical view at least partially；And dummy line, emitter stage is electrically connected by which with virtual pad.
Description
Technical field
The present invention relates to semiconductor device.
Background technology
In the past, with regard to the semiconductor device with groove structure, it is known to by completing after-applied appropriate electricity in equipment
The technology of screening installation is carried out in field.(for example, referring to patent document 1, patent document 2).
Patent document 1：Japanese Unexamined Patent Publication 2014-053552 publications
Patent document 2：Japanese Unexamined Patent Publication 2010-050211 publications
The content of the invention
Technical problem
However, in the case of the virtual groove structure that there is semiconductor device current potential to be fixed, it is impossible to being formed with void
The region for intending groove structure applies the electric field for being suitable to screen.
Technical scheme
In first form of the present invention, there is provided a kind of semiconductor device, possess：Semiconductor substrate；Virtual groove, its
It is formed at the face side of semiconductor substrate；Emitter stage, which is formed at the top on the surface of semiconductor substrate, and with vertical view
The depressed part of periphery depression；Virtual pad, which is electrically connected with virtual groove, is formed at least partially recessed under vertical view
The inner side in sunken portion；And dummy line, emitter stage is electrically connected by which with virtual pad.
Should illustrate, all features of the unrequited present invention of the above-mentioned content of the invention.In addition, the recombinant of these syndromes
Invention can also be become.
Description of the drawings
One example of the sectional view after the completion of Fig. 1 semiconductor devices 100.
Fig. 2 represents an example of the top view of semiconductor device 100.
Fig. 3 represents the sectional view of the semiconductor device 100 in screening process in the fabrication process.
Fig. 4 represents an example of the manufacturing process of semiconductor device 100.
Fig. 5 represents an example of the top view of the peripheral part of the virtual pad DP for being exaggerated embodiment 1.
Fig. 6 is the sectional view of the plane in the region A of Fig. 5.
Fig. 7 is the illustration for representing the a-a ' sections in Fig. 6.
Fig. 8 is the sectional view of the plane in the region B for represent Fig. 5.
Fig. 9 is the illustration for representing the b-b ' sections in Fig. 8.
Figure 10 represents an example of the top view being exaggerated of the virtual pad DP of embodiment 2.
Figure 11 is the sectional view of the plane in the region C of Figure 10.
Figure 12 is the illustration for representing the c-c ' sections in Figure 11.
Figure 13 is the illustration for representing the d-d ' sections in Figure 11.
Figure 14 is the integrally-built example top view of the semiconductor device 100 of embodiment 3.
Symbol description
10：Semiconductor substrate
12：Drift region
14：Buffering area
16：Emitter region
18：Base region
20：Collector area
30：Virtual groove
32：Dummy insulating film
34：Virtual conductive part
36：Dummy contact portion
40：Gate trench portion
42：Gate insulating film
44：Gate Electrode Conductive portion
46：Gate contact
48：Opposed end
50：Interlayer dielectric
60：Emitter stage
62：Emitter stage contact site
64：Depressed part
70：Colelctor electrode
80：Outside terminal
100：Semiconductor device
Specific embodiment
Hereinafter, by the embodiment explanation present invention for inventing, but following embodiment does not limit sending out for claim
It is bright.In addition, all combinations of the feature illustrated in embodiment are not limited to necessary to the solution invented.
Fig. 1 represents the sectional view of an example after the completion of semiconductor device 100.The semiconductor device 100 of this example
Igbt (the IGBT being formed on semiconductor substrate 10：Insulated Gate Bipolar
Transistor).In this example, cross section structure and electric connecting relation after the assembling of semiconductor device 100 are shown.
Semiconductor device 100 possesses gate trench portion 40, virtual groove 30, interlayer dielectric in the face side of its chip
50 and emitter stage 60.In addition, semiconductor device 100 possesses colelctor electrode 70 in the rear side of its chip.Should illustrate, in this explanation
In book, for each part such as substrate, layer, region, the face of 60 side of emitter stage is referred to as into surface, the face of 70 side of colelctor electrode is claimed
For the back side.In addition, will link direction of the emitter stage 60 with colelctor electrode 70 is referred to as depth direction.
Drift region 12, buffering area 14, emitter region 16, base region 18 and collector area are formed with semiconductor substrate 10
20.Semiconductor substrate 10 has the first conductivity type characteristic.The semiconductor substrate 10 of this example is N-Type substrate.Semiconductor substrate 10 can
Think silicon substrate, or silicon carbide substrate, nitride semiconductor base plate etc..
Drift region 12 with 10 identical conductivity type characteristic of semiconductor substrate.Drift region 12 is the first conductive area.
The drift region 12 of this example is N-Type region.
Buffering area 14 is formed at the rear side of drift region 12.Impurity concentration of the impurity concentration of buffering area 14 than drift region 12
It is high.The electric field that buffering area 14 can reach collector area 20 as the depletion layer for preventing the rear side from base region 18 from extending terminates
Layer function.
The shape within the limits prescribed from the end of that side of the setting emitter stage 60 of semiconductor substrate 10 of base region 18
Into.Base region 18 is with the second conductivity type characteristic different from semiconductor substrate 10.Base region 18 is P-Type region.Should say
Bright, the first conductivity type and the second conductivity type can be contrary conductivity type.
Emitter region 16 is adjacently formed in base region 18 with gate trench portion 40.Emitter region 16 is impurity concentration ratio
The first high conductive area of the impurity concentration of drift region 12.The emitter region 16 of this example is N+Type region.
Side of the gate trench portion 40 to extend along the depth direction of semiconductor substrate 10 on the surface of semiconductor substrate 10
Formula is formed.Gate trench portion 40 possesses gate insulating film 42 and Gate Electrode Conductive portion 44.Side wall in gate trench portion 40 is formed with
Channel region (inversion layer).Semiconductor device 100 is with arranging along the orientation vertical with bearing of trend at a prescribed interval
One or more gate trench portions 40.
Virtual groove 30 with the surface of semiconductor substrate 10 along the bearing of trend identical with gate trench portion 40
The mode that bearing of trend extends is formed.Virtual groove 30 possesses dummy insulating film 32 and virtual conductive part 34.Semiconductor device
100 with one or more the virtual grooves 30 for being arranged along the orientation vertical with bearing of trend at a prescribed interval.
In this example, multiple virtual grooves 30 are arranged side by side with multiple gate trench portions 40 and are alternately arranged.
Interlayer dielectric 50 is arranged between the electrode of the face side for being formed at semiconductor substrate 10 and semiconductor substrate 10.
Interlayer dielectric 50 is with the opening formed with the pattern for specifying.Contact site, institute are formed with the opening of interlayer dielectric 50
State contact site to be connected the electrode on interlayer dielectric 50 with the predetermined region on the surface for being formed at semiconductor substrate 10.For example,
Interlayer dielectric 50 is the dielectric film such as psg film or bpsg film.
Emitter stage 60 is formed at the top of interlayer dielectric 50 in the face side of semiconductor substrate 10.Correspondence interlayer dielectric
The pattern of 50 opening, emitter stage 60 are electrically connected with emitter region 16.Emitter stage 60 is formed by conductive materials such as metals.For example,
At least one of region of emitter stage 60 is formed by aluminium.Each electrode can be with the region formed by the material comprising tungsten.
Fig. 2 represents an example of the top view of semiconductor device 100.In this example, expression is wire bonding sequence
Semiconductor device 100 afterwards.Gate pads GP, virtual pad DP and emitter stage are formed with the surface of semiconductor device 100
60。
Emitter stage 60 has the depressed part 64 of the periphery depression under overlooking.The emitter stage 60 of this example is with the first depression
Portion 64-1 and the second depressed part 64-2 totally 2 depressed parts 64.In this manual, overlook and refer to from half with formation emitter stage 60
The visual angle of the vertical direction observation in the surface of conductor substrate 10.The depressed part 64 of this example relative to the center line EC of emitter stage 60 is in
Line balanced configuration.The center line EC of this example is defined with through the straight line at the center of emitter stage 60.
Gate pads GP are electrically connected with Gate Electrode Conductive portion 44.Gate pads GP are formed at emitter stage 60 under vertical view to be had
The first depressed part 64-1 inner side.In this example, the first depressed part 64-1 by relative to center line EC in line it is symmetrical in the way of
Formed, it is corresponding, gate pads GP also by relative to center line EC in line it is symmetrical in the way of formed.Gate pads GP are not required to
It is disposed completely within the inner side of the first depressed part 64-1, at least part of the first depressed part 64-1 for being contained in emitter stage 60
.For example, in the case of gate pads GP are tetragonal, can be by feelings three sides arranged opposite with the end of emitter stage 60
Condition is used as the inner side situation for being formed at depressed part 64.Should illustrate, can be formed and gate pads GP in the periphery of emitter stage 60
The gate runner GR (Gate runner) of connection.
Virtual pad DP is electrically connected with virtual conductive part 34.Virtual pad DP is formed at emitter stage 60 under vertical view to be had
The second depressed part 64-2 inner side.The second depressed part 64-2 of this example by relative to center line EC in line it is symmetrical in the way of shape
Into, it is corresponding, virtual pad DP also by relative to center line EC in line it is symmetrical in the way of formed.Virtual pad DP need not
The inner side of the second depressed part 64-2 is configured at completely, and at least part of the second depressed part 64-2 for being contained in emitter stage 60 is i.e.
Can.For example, in the case of virtual pad DP is tetragonal, can be by situation three sides arranged opposite with the end of emitter stage 60
As the situation of the inner side for being formed at depressed part 64.Should illustrate, can be formed and virtual pad DP in the periphery of emitter stage 60
The virtual running channel DR (Dummy runner) of connection.
Outside terminal 80 is electrically connected with emitter stage 60 via one or more emission lines EW (Emitter wire).This example
Emitter stage 60 is electrically connected with outside terminal 80 by outside terminal 80 by 3 emission lines EW1-EW3 for being mutually juxtaposed configuration.Due to
Outside terminal 80 is configured in the positive direction side of X-axis relative to center line EC, so positive direction of the outlet side of emission lines EW in X-axis
Side.There are between emission lines EW1-EW3 and emitter stage 60 2 tie points respectively, and there is 1 respectively between outside terminal 80
Tie point.The number of the tie point between emission lines EW and each electrode is not limited by this example, suitably can be changed.Should say
Bright, in this manual, tie point refers to the central point of bonding line (bonding wire) and the face of electrode contact.
For example, emission lines EW1 pass through tie point P1a、P1bElectrically connect with emitter stage 60, and pass through tie point P1cWith outer end
Son 80 is electrically connected.Emission lines EW2 pass through tie point P2a、P2bElectrically connect with emitter stage 60, and pass through tie point P2cWith outside terminal
80 electrical connections.Emission lines EW3 pass through tie point P3a、P3bElectrically connect with emitter stage 60, and pass through tie point P3cWith outside terminal 80
Electrical connection.
Tie point P1a、P2a、P3aIt is the connection of the farthest of the negative direction side that X-axis is configured in each emission lines EW1-EW3
Point.The tie point P of this example1a、P2a、P3aIt is configured in the negative direction side closer to X-axis than center line EC.On the other hand, tie point
P1b、P2b、P3bWith tie point P1a、P2a、P3aCompare, be configured at the positive direction side of X-axis.The tie point P of this example1b、P2b、P3bWith in
Heart line EC is compared, and is configured at the positive direction side of X-axis.That is, each emission lines EW1-EW3 have extremely in outlet side relative to center line EC
Few 1 tie point, and there is at least one tie point in the side contrary with outlet side relative to center line EC.
Emission lines EW1-EW3 are arranged in the way of being mutually juxtaposed.That is, link tie point P1a、P1b、P1cIllusory straight line with
Link tie point P2a、P2b、P2cVirtual line and link tie point P3a、P3b、P3cVirtual line it is almost parallel.Here, sending out
Ray EW1-EW3 is arranged substantially in parallel and is referred to and do not need each virtual line to be substantially parallel, also including producing when there is wire bonding
The situation of the deviation that the deviation of raw tie point, the characteristic to semiconductor device 100 are hardly impacted.
In addition, emission lines EW1-EW3 are equally spaced arranged.Interval between emission lines EW1 and emission lines EW2 is by tie point
P1aWith P2aApart from W12Represent.In addition, the interval between emission lines EW2 and emission lines EW3 is by tie point P2aWith P3aDistance
W23Represent.In this example, apart from W12With apart from W23It is equal.But, emission lines EW1-EW3 it is respective between interval can not
Together.Should illustrate, the interval of emission lines EW1 and emission lines EW2 can also be by tie point P1bWith P2bDistance represent.Similarly,
The interval of emission lines EW2 and emission lines EW3 can also be by tie point P2bWith P3bDistance represent.
Virtual pad DP is electrically connected with emitter stage 60 via dummy line DW (dummy wire).The virtual pad DP of this example leads to
Cross tie point PdElectrically connect with emitter stage 60, and pass through tie point Pd’Electrically connect with virtual pad DP.
The tie point P of dummy line DWdIt is configured in the side (negative direction side of X-axis) contrary with outlet side.It is preferred that dummy line
The tie point P of DWdSetting will be away from virtual pad DP.For example, it is preferable to tie point PdWith tie point Pd’Between interval near connect
In the tie point P of emission lines EW1 of virtual pad DP1aWith tie point Pd’Between interval it is big.
Also it is preferred that the outlet side of emission lines EW1-EW3 is in the case of the positive direction side of X-axis, with emission lines
Tie point Ps positioned at farthest of the EW1-EW3 in the negative direction side of X-axis1a、P2a、P3aCompare, tie point PdIt is configured in the negative of X-axis
The farther place of direction side.That is, the tie point P of preferred dummy line DWdWith the tie point P of emission lines EW1-EW31a、P2a、P3aCompare,
It is less with the distance between the end of emitter stage 60 of the opposition side of outlet side.Thus, the rotation during bonding of dummy line DW
The free degree is improved.
Furthermore it is preferred that dummy line DW presses predetermined distance away from configuration with emission lines EW1-EW3.For example, it is preferable to dummy line DW
Interval between emission lines EW1 is bigger than the interval between emission lines EW1-EW3.That is, the tie point P of dummy line DWdWith
The tie point P of emission lines EW11aThe distance between WdeThan the interval between emission lines EW1-EW3 i.e. apart from W12And W23Greatly.
Here, due to the current convergence on each tie point of emission lines EW, so compared with the region beyond tie point, even
The current potential of contact rises.So, by making the tie point P of dummy line DWdAs far as possible away from the tie point P of emission lines EW1a, so as to not
It is vulnerable to and rises the impact to dummy line DW for causing because of current potential.
Fig. 3 is the sectional view of the semiconductor device 100 of the screening process in manufacture process.The semiconductor device of this example
100 with shown in Fig. 1 after the completion of the difference of semiconductor device 100 be, between virtual conductive part 34 and emitter stage 60 not
It is electrically connected.
In screening process, the reliability of dummy insulating film 32 and gate insulating film 42 is evaluated.Specifically, by every
Between the virtual conductive part 34 of dummy insulating film 32 and semiconductor layer and across the Gate Electrode Conductive portion of gate insulating film 42
Apply the voltage for specifying between 44 and semiconductor layer evaluating the reliability of dummy insulating film 32 and virtual conductive part 34.For example,
The voltage of the regulation being applied to during screening between virtual conductive part 34 and emitter stage 60 is (that is, by product specification than rated voltage
The higher limit of setting) big magnitude of voltage, and be the value forced down more resistance to than the insulation breakdown of dummy insulating film 32.
Although the semiconductor device of this example 100 is formed with emitter stage 60 in face side, bond sequence and formation is not carried out
The operation of the rear side of 70 grade of colelctor electrode.That is, when screening process is carried out, due to not yet carrying out bond sequence, therefore virtually lead
Electrically disconnected state is between electric portion 34 and emitter stage 60.Similarly, it is also between Gate Electrode Conductive portion 44 and emitter stage 60
Electrically disconnected state.Thereby, it is possible to screen dummy insulating film 32 and this two side of Gate Electrode Conductive portion 44.
Should illustrate, in the existing semiconductor device with virtual groove, the current potential of virtual conductive part is fixed
It is and emitter stage and/or source electrode identical current potential, therefore, it is difficult to applying appropriate electric field in dummy insulating film.Therefore, it is impossible to suitable
Local screening dummy insulating film.
Fig. 4 represents an example of the manufacturing process of semiconductor device 100.In this example, Jing S100～S116 carries out void
Intend the appropriate screening of groove 30, manufacture semiconductor device 100.
First, formation drift region 12, emitter region 16, base region 18,30 and of virtual groove on semiconductor substrate 10
The surface side structure such as gate trench portion 40 (S100).Surface side structure can pass through the usual side used in semiconductor fabrication sequence
Method is formed.
Next, the face side in semiconductor substrate 10 forms the interlayer dielectric 50 (S102) with the pattern for specifying.
The formation of the pattern of interlayer dielectric 50 can be etching mode, or peel off mode.Thereafter, in semiconductor substrate 10
Face side forms surface lateral electrode (S104).Surface lateral electrode refers to virtual pad DP, gate pads GP and emitter stage 60.
Then, dummy insulating film 32 and gate insulating film 42 (S106) are screened.By entering after surface lateral electrode is formed
Row screening such that it is able to correctly screened.In addition, entering to underproof semiconductor chip is judged as in screening process
Line flag, it is possible thereby to remove in follow-up operation.Thereafter, form back side lateral electrode (S108).For example, back side lateral electrode is
Colelctor electrode 70.
After the structure of semiconductor device 100 is formed, the common wafer inspection (S110) in addition to screening is carried out.Example
Such as, wafer inspection is come WAT (the Wafer Acceptance for evaluating whether to be operating normally by being powered to semiconductor device 100
Test：Chip permits Acceptance Tests).In wafer inspection, Evaluation threshold voltage, there are leakage current, conducting voltage etc..Should illustrate,
Even if in wafer inspection operation, also can be marked to being judged as underproof semiconductor chip, such that it is able to follow-up
Operation in remove.
Then, semiconductor wafer is cut into into single shaped like chips (S112).Now, remove S106 screening process or
Underproof semiconductor chip is judged as in the wafer inspection operation of S110.For example, after the cutting of semiconductor wafer, pass through
Only select and be judged as qualified semiconductor chip, underproof semiconductor chip is judged as so as to remove.Thereby, it is possible to letter
Change follow-up assembling procedure.
Next, being packaged the common assembling procedure of semiconductor chip.For example, the back side of semiconductor chip is welded
(mount：Attachment) in DCB (Direct Copper Bonding：Direct Bonding copper) on the insulated substrate such as substrate (S114).Its
Afterwards, by wire bonding, wire bonding is carried out to virtual pad DP, gate pads GP and emitter stage 60.Thus, Fig. 2 institutes are completed
The semiconductor device 100 of the trench gate IGBT for showing.
(embodiment 1)
Fig. 5 represents an example of the top view of the peripheral part of the virtual pad DP for being exaggerated embodiment 1.In this example
In, it is illustrated that the periphery for being formed at virtual pad DP virtual running channel DR and gate runner GR.
Virtual running channel DR is arranged at the periphery of emitter stage 60.The virtual running channel DR of this example is recessed along the second of emitter stage 60
Portion 64-2 is configured.Virtual running channel DR is electrically connected with virtual pad DP in the inner side of the second depressed part 64-2 of emitter stage 60.This
Sample, the inner side of at least part of second depressed part 64-2 for being formed at emitter stage 60 of the virtual running channel DR of this example.
Gate runner GR is set along the periphery of virtual running channel DR and emitter stage 60.The gate runner GR of this example has the
One opposed end 48-1 and the second opposed end 48-2.Configure between the first opposed end 48-1 and the second opposed end 48-2
There is virtual running channel DR.That is, virtual running channel DR is across being arranged between the first opposed end 48-1 and the second opposed end 48-2.By
This, the virtual running channel DR of the inner circumferential that can make to be formed at gate runner GR and the virtual pad in the outside for being configured in gate runner GR
DP is electrically connected.Should illustrate, the gate runner GR of this example is formed by conductive materials such as polysilicons.
Fig. 6 is the sectional view of the plane in the region A of Fig. 5.Region A represents the end of the virtual pad DP sides of emitter stage 60
Portion, a part of virtual running channel DR and gate runner GR.
Virtual groove 30 extends to virtual running channel DR from emitter stage 60 under vertical view.The void that virtual groove 30 has
At least a portion for intending conductive part 34 is electrically connected with virtual running channel DR via dummy contact portion 36.
Dummy contact portion 36 is accordingly configured with multiple virtual grooves 30 under vertical view.The setting dummy contact portion of this example
36 position is an example, and the number and shape in dummy contact portion 36 arbitrarily can be selected.Dummy contact portion 36 for example by
The material of the electric conductivity such as metal is formed.
Gate trench portion 40 under vertical view exceedes virtual running channel DR from emitter stage 60 and extends to gate runner GR.Grid ditch
At least a portion in the Gate Electrode Conductive portion 44 that groove portion 40 has is electrically connected with gate runner GR via gate contact 46.
Gate contact 46 is accordingly configured with multiple gate trench portions 40 under vertical view.This example is provided with gate contact
46 position is an example, and the number and shape of gate contact 46 arbitrarily can be selected.For example, gate contact 46 by
The material of the electric conductivity such as metal is formed.
Emitter stage contact site 62 is accordingly configured with the emitter region 16 of the both sides positioned at gate trench portion 40 under vertical view.
The position for arranging emitter stage contact site 62 of this example is an example, and the number and shape of emitter stage contact site 62 can be any
Select.Emitter stage contact site 62 is for example formed by the material of the electric conductivity such as metal.
Fig. 7 is the illustration for representing the a-a ' sections in Fig. 6.A-a ' sections be provided with it is in the region of virtual running channel DR, and
The section of 40 square crossing of virtual groove 30 and gate trench portion.
In the region of virtual running channel DR is provided with, virtual conductive part 34 and virtual running channel DR are electrically connected by dummy contact portion 36
Connect.On the other hand, Gate Electrode Conductive portion 44 is covered and do not electrically connected with virtual running channel DR by interlayer dielectric 50.
Fig. 8 is the sectional view of the plane in the region B of Fig. 5.Region B is to be located in the first opposed end 48-1 and the second phase
Neighboring area to the virtual running channel DR between the 48-2 of end.
In this example, in the region of gate runner GR is provided with, by gate contact 46 by Gate Electrode Conductive portion 44 and grid
Pole running channel GR electrical connections.On the other hand, gate contact 46 is not provided with the region of virtual running channel DR is provided with.Therefore this
In the case of, then will be virtual running channel DR electric with virtual conductive part 34 by dummy contact portion 36 in the region of virtual running channel DR is provided with
Connection.The dummy contact portion 36 of this example and the shape of gate contact 46, number and position are an example, and the present invention is not
It is limited to this.
Fig. 9 is the figure of an example for representing the b-b ' sections in Fig. 8.B-b ' sections are included positioned at the first opposed end
It is in the region of the gate runner GR of 48-1 peripheries and virtual running channel DR, vertical with virtual groove 30 and gate trench portion 40 to hand over
The section of fork.
In the region of gate runner GR is provided with, will be gate runner GR electric with Gate Electrode Conductive portion 44 by gate contact 46
Connection.On the other hand, in the region of gate runner GR is provided with, virtual conductive part 34 by interlayer dielectric 50 cover and not with grid
Pole running channel GR electrical connections.In addition, in the region of virtual running channel DR is provided with, gate trench portion 40 covered by interlayer dielectric 50 and
Do not electrically connect with virtual running channel DR.
(embodiment 2)
Figure 10 represents an example of the top view being exaggerated of the virtual pad DP peripheries of embodiment 2.The grid of this example
Running channel GR does not have opposed end 48.
It is as the situation of embodiment 1, at least part of in virtual pad DP to be formed at the interior of the second depressed part 64-2
Side.Virtual running channel DR is connected with virtual pad DP, and in the way of surrounding the outside of emitter stage 60 is formed as ring-shaped.
Gate runner GR is formed as ring-shaped in the way of the periphery for surrounding emitter stage 60 and virtual running channel DR.Due to this example
Gate runner GR there is no the opposed end 48 that the gate runner GR that is related in embodiment 1 has, it is possible to evenly
The current potential of ground control gate conductive part 44.
Figure 11 is the sectional view of the plane in the region C of Figure 10.Corresponding to the C of region is virtual pad DP and gate runner
The regional area of GR.
At least a portion in virtual groove 30 and gate trench portion 40 is formed with the lower floor of virtual pad DP.In addition,
At least a portion in gate trench portion 40 is formed with the lower floor of gate runner GR.
In this example, in the region of virtual pad DP is provided with, by configuring dummy contact portion 36, by virtual pad DP with
Virtual conductive part 34 is electrically connected.In the region of virtual pad DP is provided with, gate contact 46 is not configured.In addition, being provided with void
Intend, in the region of pad DP, by configuring emitter stage contact site 62, virtual pad DP being electrically connected with emitter region 16.
On the other hand, in the region of gate runner GR is provided with, by configuring gate contact 46, by gate runner GR with
Gate Electrode Conductive portion 44 electrically connects.In the region of gate runner GR is provided with, dummy contact portion 36 is not configured.
Figure 12 is the figure of an example for representing the c-c ' sections in Figure 11.C-c ' sections are provided with the area of virtual pad DP
It is in domain, and virtual 40 square crossing of groove 30 and gate trench portion section.
In the region of virtual pad DP is provided with, will be virtual conductive part 34 electric with virtual pad DP by dummy contact portion 36
Connection.On the other hand, Gate Electrode Conductive portion 44 is covered and do not electrically connected with virtual pad DP by interlayer dielectric 50.
Figure 13 is the illustration for representing the d-d ' sections in Figure 11.D-d ' sections be provided with it is in the region of virtual pad DP,
With the section of 40 square crossing of virtual groove 30 and gate trench portion.
In the region of virtual pad DP is provided with, will be emitter region 16 electric with virtual pad DP by emitter stage contact site 62
Connection.On the other hand, virtual conductive part 34 and Gate Electrode Conductive portion 44 are covered by interlayer dielectric 50 and not electric with virtual pad DP
Connection.
(embodiment 3)
Figure 14 is the integrally-built example top view of the semiconductor device 100 of embodiment 3.The virtual pad DP of this example with
Configure in asymmetrical mode relative to the center line EC of emitter stage 60.
Virtual pad DP is configured in the positive direction side of X-axis relative to center line EC.Thereby, it is possible to increase dummy line DW
The tie point P at two endsdWith Pd’Between interval, therefore easily by dummy line DW wire bonding.For example, tie point PdWith Pd’Between
Interval can be more than 5 times, preferably more than 10 times of diameter of dummy line DW.In addition, tie point PdWith Pd’Between between
Every can be more than 1mm, preferably more than 2mm.That is, virtual pad DP is being configured at into outlet side (positive direction side of X-axis)
In the case of, the tie point P of preferred dummy line DWdRelative to the respective tie point P of emission lines EW1-EW31a、P1b、P1cIt is configured in
The side (negative direction side of X-axis) contrary with outlet side.
On the other hand, gate pads GP are relative to center line EC balanced configurations.But, gate pads GP can also with it is virtual
Pad DP is the same, to configure relative to the asymmetrical modes of center line EC.
More than, the present invention is illustrated using embodiment, but the scope of the technology of the present invention is not limited to above-mentioned embodiment
Described in scope.Those skilled in the art would appreciate that can carry out various changes or improvement to above-mentioned embodiment.According to power
The record of sharp claim understands that the various changes carried out to above-mentioned embodiment or the mode of improvement are obviously also included within the present invention
Technical scheme in.
It should be noted that in device shown in the claims, specification and drawings, system, program and method
Action, order, each execution sequence for processing such as step and stage especially not clearly " ... before ", " prior " etc., separately
Outward, so long as not need in subsequent treatment using pre-treatment result, it is possible to realize in any order.It is for the sake of convenient, right
Motion flow in claims, specification and drawings is used " first ", and " following " etc. illustrates, and is not also indicated that certain
To implement according to the order.
Claims (16)
1. a kind of semiconductor device, it is characterised in that possess：
Semiconductor substrate；
Virtual groove, which is formed at the face side of the semiconductor substrate；
Emitter stage, which is formed at the top on the surface of the semiconductor substrate, and with the recessed of the periphery depression under overlooking
Sunken portion；
Virtual pad, which is electrically connected with the virtual groove, is formed in the depressed part at least partially under vertical view
Side；And
Dummy line, the emitter stage is electrically connected by which with the virtual pad.
2. semiconductor device according to claim 1, it is characterised in that the semiconductor device is also equipped with one or more
Emission lines, described one or more emission lines are with the tie point being connected with the emitter stage, and are drawn out to the emitter stage
Outside, the emitter stage is electrically connected with outside terminal,
The dummy line outlet side when the virtual pad is brought out with described one or more emission lines it is contrary one
Side is with the tie point being connected with the emitter stage.
3. semiconductor device according to claim 2, it is characterised in that described one or more emission lines at described 1 or
The outlet side of multiple emission lines and across virtual pad side this both sides contrary with the outlet side with described
The tie point of emitter-base bandgap grading connection.
4. semiconductor device according to claim 3, it is characterised in that described one or more emission lines include with it is described
The first adjacent emission lines of dummy line and adjacent with first emission lines and with its arranged in parallel the second emission lines,
Interval between the tie point of the dummy line and the tie point of first emission lines is than first emission lines
Tie point and the tie point of second emission lines between interval it is big.
5. semiconductor device according to claim 3, it is characterised in that the tie point with one or more emission lines
Compare, the tie point of the dummy line is in the side contrary with the outlet side of the plurality of emission lines from the emitter stage
The distance of end closer to.
6. semiconductor device according to claim 4, it is characterised in that the tie point with one or more emission lines
Compare, the tie point of the dummy line is in the side contrary with the outlet side of the plurality of emission lines from the emitter stage
The distance of end closer to.
7. the semiconductor device according to any one of claim 1～6, it is characterised in that under vertical view, the virtual weldering
Disk is configuring in asymmetrical mode relative to the center line of the emitter stage.
8. the semiconductor device according to any one of claim 1～6, it is characterised in that the semiconductor device also has
It is standby：
Gate trench portion, which is formed at the face side of the semiconductor substrate；And
Gate pads, which is electrically connected with the gate trench portion, with the center line relative to the emitter stage in line under vertical view
Symmetrical mode is configured.
9. semiconductor device according to claim 8, it is characterised in that at least a portion in the gate trench portion is formed
In the lower floor of the virtual pad.
10. semiconductor device according to claim 9, it is characterised in that the semiconductor device is also equipped with：
Emitter region, which is formed at described semiconductor-based in the way of adjacent with the virtual groove and the gate trench portion
The surface of plate；And
Contact site, the virtual pad is electrically connected by which with the emitter region.
11. semiconductor devices according to claim 8, it is characterised in that the semiconductor device is also equipped with：
Gate runner, which is formed at the outside of the emitter stage under vertical view, by the gate trench portion and the gate pads
Electrical connection；And
Virtual running channel, which is configured between the inner circumferential of the periphery of the emitter stage and the gate runner under vertical view, will be described
Virtual groove is electrically connected with the virtual pad.
12. semiconductor devices according to claim 9 or 10, it is characterised in that the semiconductor device is also equipped with：
Gate runner, which is formed at the outside of the emitter stage under vertical view, by the gate trench portion and the gate pads
Electrical connection；And
Virtual running channel, which is configured between the inner circumferential of the periphery of the emitter stage and the gate runner under vertical view, will be described
Virtual groove is electrically connected with the virtual pad.
13. semiconductor devices according to claim 11, it is characterised in that the gate pads are formed at institute under vertical view
The outside of virtual running channel and the gate runner is stated,
The gate runner has the first opposed end and second opposed end opposed with first opposed end,
The virtual running channel is under vertical view with the side of the part between first opposed end and second opposed end
Formula is formed.
14. semiconductor devices according to claim 12, it is characterised in that the gate pads are formed at institute under vertical view
The outside of virtual running channel and the gate runner is stated,
The gate runner has the first opposed end and second opposed end opposed with first opposed end,
The virtual running channel is under vertical view with the side of the part between first opposed end and second opposed end
Formula is formed.
15. semiconductor devices according to claim 11, it is characterised in that the gate runner has covering under vertical view
The ring-shaped of the periphery of the emitter stage.
16. semiconductor devices according to claim 12, it is characterised in that the gate runner has covering under vertical view
The ring-shaped of the periphery of the emitter stage.
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| JP2015183087A JP6665457B2 (en) | 2015-09-16 | 2015-09-16 | Semiconductor device |
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| US10256331B2 (en) * | 2017-03-03 | 2019-04-09 | Pakal Technologies, Inc. | Insulated gate turn-off device having low capacitance and low saturation current |
| JP6984732B2 (en) * | 2018-03-15 | 2021-12-22 | 富士電機株式会社 | Semiconductor device |
| WO2020162013A1 (en) | 2019-02-07 | 2020-08-13 | 富士電機株式会社 | Semiconductor device |
| EP3859775A1 (en) * | 2020-02-03 | 2021-08-04 | Infineon Technologies AG | Semiconductor arrangement and method for producing the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| US9870965B2 (en) | 2018-01-16 |
| US20170077004A1 (en) | 2017-03-16 |
| CN106549046B (en) | 2020-11-20 |
| JP2017059672A (en) | 2017-03-23 |
| JP6665457B2 (en) | 2020-03-13 |
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