CN106549018B - Cell contact structure - Google Patents
Cell contact structure Download PDFInfo
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- CN106549018B CN106549018B CN201610170103.1A CN201610170103A CN106549018B CN 106549018 B CN106549018 B CN 106549018B CN 201610170103 A CN201610170103 A CN 201610170103A CN 106549018 B CN106549018 B CN 106549018B
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- cell contact
- cell
- upwardly protruding
- contact region
- oxide
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- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 4
- 229910021318 lanthanum strontium oxide Inorganic materials 0.000 claims description 2
- 210000004027 cell Anatomy 0.000 description 25
- 238000000034 method Methods 0.000 description 20
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910016909 AlxOy Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 210000000352 storage cell Anatomy 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
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- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a unit contact structure, which comprises a semiconductor substrate, a first contact layer, a second contact layer and a third contact layer, wherein the semiconductor substrate is provided with a main surface; an upwardly protruding structure on the major surface; a cell contact region located at the major surface and adjacent to the upwardly protruding structure; an interface film conformally covering the sidewalls of the upwardly protruding structures and the cell contact regions; and a contact plug on the cell contact region, wherein the interface film is between the contact plug and the cell contact region.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a cell contact structure of a Dynamic Random Access Memory (DRAM).
Background
In the semiconductor field, a Dynamic Random Access Memory (DRAM) is a capacitor-based memory device that is integrated into an integrated circuit and stores individual digital data on individual capacitors and is randomly readable. DRAM is generally constructed of a plurality of charge storage cells arranged in an array, wherein each charge storage cell generally includes a capacitor and a transistor.
Generally, each transistor in a DRAM includes a gate, a drain in a semiconductor substrate, and a source spaced apart from the drain. The gate is typically electrically connected to a word line, the source is typically electrically connected to a bit line (digit line), and the drain is typically electrically connected to a capacitor through a cell contact (cell contact) structure.
The demand for ever-shrinking devices has accelerated the evolution of DRAM cell designs with smaller feature sizes, cell areas, and unit densities. However, as the contact area is reduced, the size of the cell contact structure is also reduced, resulting in higher contact resistance and tighter process window.
Accordingly, there remains a need in the art for an improved DRAM cell contact structure that avoids the above-mentioned problems of the prior art without increasing process complexity.
Disclosure of Invention
The present invention is directed to an improved cell contact structure and a method for fabricating the same, which can reduce contact resistance and improve process margin.
The invention provides a unit contact structure, which comprises a semiconductor substrate with a main surface; an upwardly protruding structure on the major surface; a cell contact region located at the major surface and adjacent to the upwardly protruding structure; an interface film conformally covering the sidewalls of the upwardly protruding structures and the cell contact regions; and a contact plug on the cell contact region, wherein the interface film is between the contact plug and the cell contact region.
According to an embodiment of the present invention, the interface film includes a metal oxide. The metal oxide comprises aluminum oxide, yttrium oxide, lanthanum oxide, or strontium oxide. Wherein the interfacial film thickness is less than 10 nanometers.
Needless to say, the objects of the present invention will be understood by those skilled in the art after reading the following detailed description of the preferred embodiments of the present invention and the accompanying drawings.
Drawings
Fig. 1 to 8 are cross-sectional views illustrating a method of fabricating a cell contact structure of a Dynamic Random Access Memory (DRAM) device according to an embodiment of the present invention.
Wherein the reference numerals are as follows:
10 semiconductor substrate
10a main surface
20 shallow trench isolation structure
21/22/23/24 Trench Gate Structure
30/40 upward convex structure
30a/30b/40a/40b side wall
50 polysilicon layer
52a side wall
54 recessed groove
60 dielectric layer
202 gate dielectric layer
210 conductive layer
220 cap layer
230/240 cell contact area
260 interfacial film
300/400 lower part of siliceous material
310/410 metal part
320/420 insulating layer
330/430 patterned contact oxide layer
500 unit contact structure
510 polysilicon contact plug
510a upper surface
Detailed Description
In the following description, numerous specific details are provided to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In addition, well known system configurations and process steps have not been shown in detail since they would be apparent to one skilled in the art
Also, the drawings of the illustrated embodiments of the devices are semi-schematic and not to scale, and certain dimensions may be exaggerated in the drawings for clarity of presentation. Further, where multiple embodiments are disclosed and described having certain features in common, the same or similar features are generally indicated by the same reference numerals to facilitate explanation.
In the field of transistor and integrated circuit fabrication processes, the term "major surface" is generally considered to be the surface on which a plurality of transistors are formed, for example, in a semiconductor fabrication process. Likewise, in the present description, the term "perpendicular" is generally considered to be substantially at right angles to the major surface. The major surface is generally coplanar with the <100> crystal lattice plane of the monocrystalline silicon layer where the field effect transistor is formed.
Fig. 1 to 8 illustrate a method of fabricating a cell contact structure of a Dynamic Random Access Memory (DRAM) device according to an embodiment of the present invention. First, as shown in fig. 1, a semiconductor substrate 10, for example, a silicon substrate, is provided. It is understood that the semiconductor substrate 10 may be formed of other semiconductor materials or wafers. The semiconductor substrate 10 has a main surface 10 a. According to an embodiment of the present invention, a Shallow Trench Isolation (STI) structure 20 and a plurality of trench gate structures 21, 22, 23, and 24 are formed under a main surface 10a of a semiconductor substrate 10. Each of the trench gate structures 21, 22, 23 and 24 includes a gate dielectric layer 202, a conductive layer 210 and a cap layer 220. The conductive layer 210 may include, but is not limited to, titanium nitride or tungsten. The cap layer 220 may comprise silicon oxide or silicon nitride, among others.
According to an embodiment of the present invention, the semiconductor substrate 10 has at least two adjacent upwardly protruding structures 30 and 40 on the main surface 10a thereof. According to an embodiment of the present invention, both upwardly projecting structures 30 and 40 are in close proximity. The upwardly projecting structures 30 and 40 extend in a first direction and are parallel to each other when viewed from above. The upwardly projecting structures 30 and 40 each have a wavy or saw-tooth pattern when viewed from above. It should be appreciated that the illustrated embodiment illustrates only two upwardly projecting structures for ease of illustration.
According to an embodiment of the present invention, the upward protruding structure 30 includes a silicon lower portion 300, a metal portion 310 directly above the silicon lower portion 300, and an insulating layer 320, such as a silicon nitride layer, above the metal portion 310 and covering the sidewall thereof. Above the insulating layer 320 is a patterned contact oxide layer 330, such as a silicon oxide layer. The upwardly projecting structure 30 has two opposing sidewalls 30a and 30 b.
According to an embodiment of the present invention, the upwardly protruding structure 40 comprises a silicon lower portion 400, a metal portion 410 directly above the silicon lower portion 400, and an insulating layer 420, such as a silicon nitride layer, above the metal portion 410 and covering sidewalls of the metal portion. Above the insulating layer 420 is a patterned contact oxide layer 430, for example, a silicon oxide layer. The upwardly projecting structure 40 has two opposing sidewalls 40a and 40 b. Wherein the sidewall 40a is adjacent to and directly facing the sidewall 30 b.
It is to be understood that the upwardly projecting structures 30 and 40 are for illustrative purposes only. According to an embodiment of the present invention, the metal portions 310 and 410 directly above the silicon lower portions 300 and 400 can be used as bit lines (digit lines) in a DRAM device, but are not limited thereto.
The patterned contact oxide layers 330 and 430 extend along a second direction and are parallel to each other when viewed from above. According to an embodiment of the present invention, the first direction is orthogonal to the second direction at right angles, but is not limited thereto. According to an embodiment of the present invention, the patterned contact oxide layers 330 and 430 may be composed of, but not limited to, a spin-on (SOD) dielectric material. The patterned contact oxide layers 330 and 430 may be a line pattern, but are not limited thereto.
According to the embodiment of the present invention, a cell contact region 230 is adjacent to the trench gate structure 22 and a cell contact region 240 is adjacent to the trench gate structure 23 on the semiconductor substrate 10. It should be understood that the layout configuration of the Shallow Trench Isolation (STI) structure 20 and the plurality of trench gate structures 21, 22, 23 and 24 is only for illustration and is not intended to limit the scope of the present invention.
As shown in fig. 2, an interfacial film (interfacial film)260 is conformally deposited on the semiconductor substrate 10 and the upwardly protruding structures 30 and 40 by a Chemical Vapor Deposition (CVD) process or other suitable process according to an embodiment of the present invention. According to the embodiment of the present invention, the interface film 260 conformally covers the surfaces of the contact oxide layers 330 and 430, the sidewalls 30a, 30b, 40a, 40b of the upwardly protruding structures 30 and 40, and the cell contact regions 230 and 240.
According to an embodiment of the present invention, the interface film 260 may be a metal oxide film, such as, but not limited to, aluminum oxide (AlxOy), yttrium oxide (YxOy), lanthanum oxide (LaOx), strontium oxide (SrOx), and the like. In other embodiments, the interfacial film 260 may also be a metal nitride film, such as titanium nitride. The thickness of the interfacial film 260 is preferably less than 10 nanometers in accordance with an embodiment of the present invention. According to an embodiment of the present invention, an ion implantation process may be performed to form doped regions (not shown), such as N-type doped regions, in the cell contact regions 230, 240 before the interface film 260 is deposited.
As shown in FIG. 3, a polysilicon layer 50 is then deposited on the interfacial film 260 by a chemical vapor deposition process according to an embodiment of the present invention. Polysilicon layer 50 covers upwardly protruding structures 30 and 40 and patterned contact oxide layers 330 and 430. Then, the polysilicon layer 50 is etched back such that the patterned contact oxide layers 330 and 430 protrude from an upper surface 50a of the polysilicon layer 50. Portions of the interfacial film 260 over the patterned contact oxide layers 330 and 430 are now exposed.
As shown in fig. 4, a conformal sidewall sub-layer, such as a silicon nitride layer, is deposited on the upper surface 50a of the polysilicon layer 50 and the protruding patterned contact oxide layers 330 and 430 by another Chemical Vapor Deposition (CVD) process according to an embodiment of the present invention. An anisotropic dry etch process is then performed to etch the spacer layer until the upper surface 50a of the polysilicon layer 50 is exposed, thereby forming spacers 52a on the opposing sidewalls of the patterned contact oxide layers 330 and 430. The spacer 52a directly contacts the interfacial film 260. The sidewall sub-layer may be silicon nitride, silicon oxynitride, silicon oxide, but is not limited thereto.
As shown in fig. 5, according to the embodiment of the present invention, a dry etching process is performed to etch the polysilicon layer 50 uncovered by the spacers 52a in a self-aligned etching manner using the spacers 52a as a hard mask until the interface film 260 on the main surface 10a of the semiconductor substrate 10 is exposed, thereby forming the recess trench 54 in the polysilicon layer 50. In this etching step, the interface film 260 may serve as an etch stop layer. The self-aligned dry etching process divides the polysilicon layer 50 between the upwardly protruding structures 30 and 40 into two parts to form the separated polysilicon contact plugs 510.
As shown in fig. 6, an etching process is performed to selectively etch away the interface film 260 exposed at the bottom of the recess trench 54, exposing the main surface 10a of the semiconductor substrate 10. The exposed surface of the bottom of the recessed trench 54 may include the surface of the shallow trench isolation structure 20 and the surface of a portion of the cell contact regions 230 and 240. The above etching process has a high etching selectivity ratio so that the degree of etching of the main surface 10a of the semiconductor substrate 10 can be greatly reduced, thereby improving the problem of insufficient margin of the past polysilicon/silicon substrate etching selection process and solving the past active area trimming (AAclipping) problem.
As shown in fig. 7, a chemical vapor deposition process is then performed to deposit a dielectric layer 60, such as a silicon oxide layer, on the semiconductor substrate 10. According to an embodiment of the present invention, the dielectric layer 60 may fill the recess trench 54 and cover the spacer 52a and the patterned contact oxide layers 330 and 430.
Finally, as shown in fig. 8, a Chemical Mechanical Polishing (CMP) process is performed to polish the dielectric layer 60, the interface film 260, the spacers 52a, and the patterned contact oxide layers 330 and 430 until the upper surface 510a of the polysilicon contact plug 510 is exposed. At this time, the spacers 52a and the patterned contact oxide layers 330 and 430 are polished away, and the interfacial film 260 on the surfaces of the patterned contact oxide layers 330 and 430 is also removed.
Structurally, as shown in fig. 8, the cell contact structure 500 of the present invention is composed of a polysilicon contact plug 510 and an interface film 260 interposed between the polysilicon contact plug 510 and the sidewalls 30a, 30b, 40a, 40b of the upwardly protruding structures 30 and 40. The interfacial film 260 has an L-shaped cross-sectional profile and is interposed between the polysilicon contact plug 510 and the cell contact regions 230, 240. In other words, the polysilicon contact plug 510 does not directly contact the cell contact regions 230, 240.
The interface film 260 may be a metal oxide film, such as, but not limited to, aluminum oxide (AlxOy), yttrium oxide (YxOy), lanthanum oxide (LaOx), strontium oxide (SrOx), and the like. In other embodiments, the interfacial film 260 may also be a metal nitride film, such as titanium nitride. According to an embodiment of the present invention, the thickness of the interfacial film 260 is preferably less than 10 nm. By providing the interface film 260 between the polysilicon contact plug 510 and the cell contact regions 230, 240, the energy barrier (energy barrier) of the interface can be reduced, thereby achieving the purpose of reducing the contact resistance.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A cell contact structure, comprising:
a semiconductor substrate having a main surface;
an upwardly protruding structure on said major surface, said upwardly protruding structure comprising a silicon lower portion, a metal portion directly on said silicon lower portion, and an insulating layer on said metal portion;
a cell contact region located at the major surface and adjacent to the upwardly protruding structure;
an interface film conformally covering sidewalls of the upwardly protruding structure including the silicon lower portion, the metal portion and the insulating layer and conformally covering the cell contact region; and
a contact plug on the major surface and on the cell contact region, wherein the interface film is interposed between the contact plug and the cell contact region.
2. The cell contact structure of claim 1, wherein the interfacial film comprises a metal oxide.
3. The cell contact structure of claim 2, wherein the metal oxide comprises aluminum oxide, yttrium oxide, lanthanum oxide, or strontium oxide.
4. The cell contact structure of claim 2, wherein the interfacial film thickness is less than 10 nanometers.
5. The cell contact structure of claim 1, wherein the interface film comprises a metal nitride.
6. The cell contact structure of claim 5, wherein the metal nitride comprises titanium nitride.
7. The cell contact structure of claim 1, further comprising at least one trench gate structure in the semiconductor substrate, wherein the cell contact region is adjacent to the trench gate structure.
8. The cell contact structure of claim 7, further comprising a shallow trench isolation structure in the semiconductor substrate, wherein the cell contact region is between the trench gate structure and the shallow trench isolation structure.
9. The cell contact structure of claim 1, wherein the metal portion is a bitline of a dynamic random access memory device.
10. The cell contact structure of claim 1, wherein the contact plug is a polysilicon contact plug.
11. A cell contact structure comprising:
an upwardly protruding structure on a main surface of the semiconductor substrate;
a cell contact region located at the major surface and adjacent to the upwardly protruding structure;
a conformal interface film on opposing sidewalls of the upwardly protruding structure and on the cell contact region; and
a contact plug on the major surface and on the cell contact region, wherein the compliant interfacial film is interposed between the contact plug and the cell contact region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104130371A TWI560853B (en) | 2015-09-15 | 2015-09-15 | Cell contact structure |
| TW104130371 | 2015-09-15 |
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| Publication Number | Publication Date |
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| CN106549018A CN106549018A (en) | 2017-03-29 |
| CN106549018B true CN106549018B (en) | 2020-04-07 |
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| CN201610170103.1A Active CN106549018B (en) | 2015-09-15 | 2016-03-23 | Cell contact structure |
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| CN (1) | CN106549018B (en) |
| TW (1) | TWI560853B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107546226A (en) * | 2017-09-29 | 2018-01-05 | 睿力集成电路有限公司 | Memory and its manufacture method |
| CN110534515B (en) * | 2018-05-24 | 2024-07-09 | 长鑫存储技术有限公司 | Manufacturing method for reducing unit contact defect and semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325829A (en) * | 2012-03-22 | 2013-09-25 | 株式会社东芝 | Semiconductor device and manufacturing method of the same |
| CN103377905A (en) * | 2012-04-30 | 2013-10-30 | 三星电子株式会社 | Methods of fabricating semiconductor devices having buried channel array |
| TW201501307A (en) * | 2013-02-18 | 2015-01-01 | Ps4 Luxco Sarl | Semiconductor device |
| CN104282645A (en) * | 2013-07-08 | 2015-01-14 | 茂达电子股份有限公司 | trench type power semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100474737B1 (en) * | 2002-05-02 | 2005-03-08 | 동부아남반도체 주식회사 | Dram fabrication capable of high integration and fabrication method |
| KR20120007708A (en) * | 2010-07-15 | 2012-01-25 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
| JP2012248686A (en) * | 2011-05-27 | 2012-12-13 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
| US20150371991A1 (en) * | 2013-02-07 | 2015-12-24 | Hidekazu Nobuto | Semiconductor device and method for manufacturing same |
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- 2015-09-15 TW TW104130371A patent/TWI560853B/en active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325829A (en) * | 2012-03-22 | 2013-09-25 | 株式会社东芝 | Semiconductor device and manufacturing method of the same |
| CN103377905A (en) * | 2012-04-30 | 2013-10-30 | 三星电子株式会社 | Methods of fabricating semiconductor devices having buried channel array |
| TW201501307A (en) * | 2013-02-18 | 2015-01-01 | Ps4 Luxco Sarl | Semiconductor device |
| CN104282645A (en) * | 2013-07-08 | 2015-01-14 | 茂达电子股份有限公司 | trench type power semiconductor device and manufacturing method thereof |
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| Publication number | Publication date |
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| CN106549018A (en) | 2017-03-29 |
| TWI560853B (en) | 2016-12-01 |
| TW201711169A (en) | 2017-03-16 |
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