CN106528920B - A kind of process mapping method cascading look-up table - Google Patents
A kind of process mapping method cascading look-up table Download PDFInfo
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- CN106528920B CN106528920B CN201610856090.3A CN201610856090A CN106528920B CN 106528920 B CN106528920 B CN 106528920B CN 201610856090 A CN201610856090 A CN 201610856090A CN 106528920 B CN106528920 B CN 106528920B
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000012367 process mapping Methods 0.000 title claims abstract description 9
- 238000013507 mapping Methods 0.000 claims abstract description 21
- 101100510695 Arabidopsis thaliana LUT2 gene Proteins 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 101100021997 Arabidopsis thaliana CYP97A3 gene Proteins 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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Abstract
A kind of process mapping method cascading look-up table provided by the invention, by obtaining gate level circuit, the gate level circuit includes combinatorial logic unit, and look-up table mapping is carried out to combinatorial logic unit, look-up table after mapping is grouped, obtain basic logic unit, wherein basic logic unit includes at least one path, each path includes at least two look-up tables, one-to-one connection is carried out by quick hardwired between two look-up tables in each path, finally according to the logical connection information of look-up table in basic logic unit, logic level counting number is carried out to path.The method reduce the logic series in path, so that fpga chip be made to possess higher fmax.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of process mapping method for cascading look-up table.
Background technique
Currently, being applied at FPGA (Field Programmable Gate Array, field programmable gate array)
In, it is desirable that integrated circuit has a programmable or configurable interference networks, logic gate by the interference networks that can configure each other
Connection, the FPGA to work as core in individual chips or system are applied to a large amount of microelectronic devices extensively
In.
As fpga chip continues to develop, it is defeated to can be only generated simple K when carrying out Technology Mapping for traditional fpga chip
Enter look-up table (English: Look-Up-Table, LUT), in order to improve fmax, quick hardwired is devised between look-up table.So
And the prior art can not effectively utilize quick hardwired, to being treated as the unification of quick hardwired by general coiling
The common coiling of resource.Common winding department usually there will be the transmission apparatus such as at least one gate, since fpga chip is through work
Without completing placement-and-routing after skill mapping, therefore every line Jing Guo general coiling resource its delay is unknown.
It follows that in the prior art since quick hardwired is treated as common coiling, cause with calculating logic level
When several modes estimates the delay of each path and determines critical path, the fmax of entire fpga chip will be greatly reduced.Its
In, logic series refers to the number of the look-up table passed through on a paths, in part fpga chip structure shown in Fig. 1, by
Input terminal A [0] arrives a critical path of output end O composition, and the logic series in the path is 2 grades.
Summary of the invention
To solve the above-mentioned problems, the efficiency of transmission for improving fpga chip, this application provides a kind of cascade look-up tables
Process mapping method this method comprises: including combinatorial logic unit gate level circuit by obtaining, and carries out combinatorial logic unit
Look-up table mapping, the look-up table after mapping is grouped, and obtains basic logic unit, which includes at least one
Paths, each path include at least two look-up tables, are carried out between two look-up tables by quick hardwired in each path
One-to-one connection carries out logic level counting number to path finally according to the logical connection information of look-up table in basic logic unit.
In an optional realization, this method further include: by common coiling, to different in the basic logic unit
Path be attached.
In an optional realization, according to the logical connection information of look-up table in basic logic unit, path is carried out
Logic level counting number, specifically: if the logical connection carried out between look-up table by quick hardwired, signal is through quick hardwired
Path Logical series by a look-up table is pre-set value.If the logical connection carried out between look-up table by common coiling,
The Path Logical series that then signal passes through a look-up table through common coiling is 1.
In an optional realization, pre-set value is directly proportional to quick hard-wired length, and pre-set value is less than 1.
A kind of process mapping method cascading look-up table provided by the present application, by obtaining gate level circuit, the gate level circuit
Look-up table mapping is carried out including combinatorial logic unit, and to combinatorial logic unit, the look-up table after mapping is grouped, is obtained
Basic logic unit, wherein basic logic unit include at least one path, each path include at least two look-up tables, every
One-to-one connection is carried out by quick hardwired between two look-up tables in path, finally according to look-up table in basic logic unit
Logical connection information, to path carry out logic level counting number.The method reduce the logic series in path, to make FPGA
Chip possesses higher fmax.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is the partial structure diagram of fpga chip in the prior art；
Fig. 2 is a kind of flow chart of process mapping method for cascading look-up table provided in an embodiment of the present invention；
Fig. 3 be in the prior art 10 select it is 1 with gate cell structural schematic diagram；
Fig. 4 A is the structural schematic diagram of basic logic unit provided in an embodiment of the present invention；
Fig. 4 B selects 1 and the structural schematic diagram after gate cell mapping for provided in an embodiment of the present invention 10；
Fig. 5 is the schematic diagram of Fig. 4 B logic series.
Specific embodiment
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Fig. 2 is a kind of flow chart of process mapping method for cascading look-up table provided in an embodiment of the present invention.Such as Fig. 2 institute
Show, this method may include:
Step 210 obtains gate level circuit, which includes combinatorial logic unit.
In the synthesis and library mapping phase of fpga chip, gate level circuit need to be converted by subscriber's line circuit.Subscriber's line circuit can be with
It is using made of hardware description language (verilog or VHDL) compiling.It is compiled using high-level hardware description language
Subscriber's line circuit, the gate level circuit of low level will be become after comprehensive, which may include at least one combinational logic list
Member, combinatorial logic unit can be with the units such as door or door, NOT gate, as Fig. 3 be one 10 select 1 and gate cell.
Step 220 carries out look-up table mapping to combinatorial logic unit, and the look-up table after mapping is grouped, base is obtained
This logic unit, the basic logic unit include at least one path, and each path includes at least two look-up tables, each path
In pass through quick hardwired between two look-up tables and carry out one-to-one connection.
Look-up table mapping is carried out at least one combinatorial logic unit in the gate level circuit of acquisition, acquisition contains look-up table
Map netlist.Fpga chip can be according to the far and near distance between the logic connecting relation or look-up table of map netlist, to look-up table
It is grouped and is packaged as a basic logic unit.Obtained basic logic unit may include at least one path, and every
Path may include at least two look-up tables, can carry out a pair by quick hardwired between two look-up tables in each path
One connection.As shown in Figure 4 A, include the path A and B path in basic logic unit, include 3 look-up tables in the path A, in B path
Including 4 look-up tables, one-to-one connection is carried out by quick hardwired (solid line in figure) between adjacent look-up table in each path.
Fig. 4 B selects 1 and the structural schematic diagram after gate cell mapping for provided in an embodiment of the present invention 10.As shown, 10 choosings
1 can carry out cascade connection by tri- look-up tables of LUT0, LUT2 and LUT4 with after gate cell mapping.By fast between LUT0 and LUT2
Fast hardwired connection, is connected between LUT2 and LUT4 by quick hardwired.A [0]-A [9] is input terminal, and O is output end.
Optionally, the look-up table between two path A and B can be attached by common coiling resource.In Figure 4 A,
Between LUT0 and LUT1 or between LUT2 and LUT5, it can be attached by common coiling resource (dotted line in figure).
It should be noted that quickly the quick transmission of signal may be implemented in hardwired, and common coiling resource is by gating
Device composition, its main feature is that in order to improve the success rate of wiring and occupy relatively small hardware area, due to by gating
Device is also required to expend the time, and therefore, common coiling resource cannot quickly transmit signal.
In addition, the gate level circuit can also include at least one sequential logic unit, the sequential logic list in mapping process
Member carries out register mappings.
Step 230, according to the logical connection information of look-up table in basic logic unit, logic series meter is carried out to path
Number.
The logical connection information of look-up table in the basic logic unit obtained according to step 220, such as input signal in path
Behavioural characteristic, logic level counting number is carried out to path, can specifically include: if being carried out by quick hardwired between look-up table
Logical connection, then the Path Logical series that signal passes through a look-up table through quick hardwired is pre-set value, such as 0.2；If looking into
The logical connection carried out between table by common coiling is looked for, then signal passes through the Path Logical series of a look-up table through common coiling
It is 1.
Wherein, quickly hard-wired logic series is less than the logic series of common coiling, i.e., pre-set value is less than 1.It is default
Definite value is directly proportional to quick hard-wired length, that is to say, that the quick hard-wired length between look-up table is longer, corresponding to patrol
The pre-set value for collecting series is bigger.
In one example, pre-set value is set as 0.2.Fig. 5 is the schematic diagram of Fig. 4 B logic series.In figure, signal from
Input terminal A [3] passes through quick hardwired into the path of output end O, since signal is no before by LUT0, passes through
Logic series is 1 on the path of LUT0；Signal is quick from have passed through during the output end O2 of output end O1 to the LUT2 of LUT0
Hardwired, therefore logic series is 0.2 on the path for passing through LUT2；Output end O of the signal from output end O2 to the LUT4 of LUT2
The quick hardwired that period have passed through, therefore be 0.2 by logic series on the path of LUT4, in summary logic series can
Know, in A [3] -> O logical path, total logic series is 1.4.
A kind of logic level counting number method cascading look-up table provided by the invention, by obtaining gate level circuit, the gate leve
Circuit includes combinatorial logic unit, and carries out look-up table mapping to combinatorial logic unit, and the look-up table after mapping is grouped,
Basic logic unit is obtained, wherein basic logic unit includes at least one path, and each path includes at least two look-up tables,
One-to-one connection is carried out by quick hardwired between two look-up tables in each path, is finally looked into according in basic logic unit
The logical connection information for looking for table carries out logic level counting number to path.The method reduce the logic series in path, to make
Fpga chip possesses higher fmax.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can be executed with hardware, processor
The combination of software module or the two is implemented.Software instruction can be made of corresponding software module, and software module can be by
Deposit in random access memory, flash memory, read-only memory, erasable programmable read-only register (English: erasable
Programmable read-only memory, EPROM) memory, Electrically Erasable Programmable Read-Only Memory memory (English:
Electrically erasable programmable read-only memory, EEPROM), hard disk, CD-ROM (English
Text: compact disc read-only memory, CD-ROM) or any other form well known in the art storage be situated between
In matter.A kind of illustrative storage medium is coupled to processor, thus enable a processor to from the read information, and
Information can be written to the storage medium.Certainly, storage medium is also possible to the component part of processor.Pocessor and storage media
It can be located in ASIC.In addition, the ASIC can be located in user equipment.Certainly, pocessor and storage media can also be used as
Discrete assembly is present in user equipment.
Those skilled in the art are it will be appreciated that in said one or multiple examples, function described in the invention
It can be realized with hardware, software, firmware or their any combination.It when implemented in software, can be by these functions
Storage in computer-readable medium or as on computer-readable medium one or more instructions or code transmitted.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all any modification, equivalent substitution, improvement and etc. on the basis of technical solution of the present invention, done should all
Including within protection scope of the present invention.
Claims (4)
1. a kind of process mapping method for cascading look-up table, which is characterized in that the described method includes:
Gate level circuit is obtained, the gate level circuit includes combinatorial logic unit；
Look-up table mapping is carried out to the combinatorial logic unit, the look-up table after mapping is grouped, acquisition is patrolled substantially
Unit is collected, the basic logic unit includes at least one path, and each path includes at least two look-up tables, described every
One-to-one connection is carried out by quick hardwired between two look-up tables in paths；The quickly hard-wired logic series is small
In the logic series of common coiling, i.e., pre-set value is less than 1；
According to the logical connection information of look-up table described in the basic logic unit, logic series meter is carried out to the path
Number.
2. the method according to claim 1, wherein the method also includes:
By common coiling, path different in the basic logic unit is attached.
3. according to the method described in claim 2, it is characterized in that, the look-up table according to the basic logic unit
Logical connection information, to the path carry out logic level counting number, specifically:
If the logical connection carried out between the look-up table by the quick hardwired, signal pass through through the quick hardwired
The Path Logical series of one look-up table is pre-set value；
If the logical connection carried out between the look-up table by the common coiling, signal pass through one through the common coiling
The Path Logical series of the look-up table is 1.
4. according to the method described in claim 3, it is characterized in that, the pre-set value and it is described quickly hard-wired length at
Direct ratio, and the pre-set value is less than 1.
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| CN108182303B (en) * | 2017-12-13 | 2020-08-28 | 京微齐力(北京)科技有限公司 | Programmable device structure based on mixed function memory unit |
| CN112699131B (en) * | 2021-01-18 | 2021-11-30 | 中国电子系统技术有限公司 | Mapping connection interaction method and device |
| CN115686985B (en) * | 2022-12-30 | 2023-04-18 | 无锡亚科鸿禹电子有限公司 | Trigger condition realizing method based on lookup table structure |
| CN116911227B (en) * | 2023-09-05 | 2023-12-05 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and storage medium based on hardware |
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