CN106504991B

CN106504991B - Method for fabricating nanowires for horizontal full-ring gate devices for semiconductor applications

Info

Publication number: CN106504991B
Application number: CN201610752395.XA
Authority: CN
Inventors: S·孙; N·吉田; B·伍德
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2015-09-03
Filing date: 2016-08-29
Publication date: 2021-08-27
Anticipated expiration: 2036-08-29
Also published as: CN106504991A; KR20170031047A; TW201724500A; KR102552613B1; TWI716441B

Abstract

The present disclosure provides methods for forming nanowire structures for horizontal all-around gate (hGAA) structure Field Effect Transistors (FETs) of semiconductor chips with desired materials. In one example, a method of forming a nanowire structure on a substrate includes: supplying an oxygen-containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of first and second layers having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer; and selectively forming an oxide layer on the second set of sidewalls in the second layer.

Description

Method for fabricating nanowires for horizontal full-ring gate devices for semiconductor applications

Background

Technical Field

Embodiments of the invention generally relate to methods for forming vertically stacked nanowires on a semiconductor substrate with a desired material, and more particularly to methods for forming vertically stacked nanowires on a semiconductor substrate with a desired material for use in Field Effect Transistor (FET) semiconductor fabrication applications.

Background

Reliable production of sub-half micron and smaller features is one of the key technical challenges for the next generation of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) semiconductor devices. However, as circuit technology limits advance, shrinking-size VLSI and ULSI technologies have additional demands on processing power. Reliable formation of gate structures on substrates is important to VLSI and ULSI success and to continued efforts to increase circuit density and quality of individual substrates and dies.

As the circuit density of next generation devices increases, the width of interconnects (such as vias, trenches, contacts, gate structures and other features, and dielectric material therebetween) decreases to 25nm and 20nm dimensions and less, while the thickness of the dielectric layer remains substantially constant, whereby the aspect ratio of the features increases. Furthermore, the reduced channel length typically results in significant short channel effects for conventional planar MOSFET architectures. To enable fabrication of next generation devices and structures, three-dimensional (3D) device structures are often used to improve the performance of transistors. In particular, fin field effect transistors (finfets) are commonly used to enhance device performance. FinFET devices typically include a semiconductor fin having a high aspect ratio, with channel and source/drain regions for the transistor formed on the semiconductor fin. Subsequently, a gate electrode is formed over and along the sides of a portion of the fin device, taking advantage of the increased surface area of the channel and source/drain regions, in order to produce faster, more reliable, and better controlled semiconductor transistor devices. Additional advantages of finfets include reduced short channel effects and higher current supply. Device structures having the hGAA configuration typically provide superior electrostatic control by surrounding the gate in order to suppress short channel effects and associated leakage currents.

In some applications, horizontal all-ring gate (hGAA) structures are used for next generation semiconductor device applications. The hGAA device structure includes several lattice-matched channels (e.g., nanowires) suspended in a stacked configuration and connected by source/drain regions.

In hGAA structures, different materials are typically utilized to form the channel structure (e.g., nanowire), which undesirably increases the manufacturing difficulty in integrating all of these materials in the nanowire structure without degrading device performance. For example, one of the challenges associated with hGAA structures includes the presence of large parasitic capacitances between the metal gate and the source/drain. Improperly managing such parasitic capacitances can result in a significant reduction in device performance.

Accordingly, there is a need for improved methods for forming channel structures of hGAA device structures on a substrate with good profile and dimensional control.

Disclosure of Invention

The present disclosure provides methods for forming nanowire structures of a horizontal full-ring gate (hGAA) structure of a semiconductor chip with desired materials. In one example, a method of forming a nanowire structure on a substrate includes: supplying an oxygen-containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of first and second layers having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer; and selectively forming an oxide layer on the second set of sidewalls in the second layer.

In another example, a method of forming a nanowire structure on a substrate includes: forming an oxide layer primarily on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer includes repeating pairs of first and second layers having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer, wherein the oxide layer is selectively formed on the second set of sidewalls in the second layer.

In yet another example, a method of forming a nanowire structure on a substrate comprises: forming an oxide layer primarily on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer includes a repeating pair of a silicon layer and a SiGe layer having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer, wherein the portion of the oxide layer selectively formed thereon is located on the second set of sidewalls in the SiGe layer.

Drawings

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 depicts a plasma processing chamber that may be used to perform a deposition process on a substrate;

FIG. 2 depicts a processing system that may include the plasma processing chamber of FIG. 1to be incorporated therein;

FIG. 3 depicts a flow diagram of a method for fabricating nanowire structures formed on a substrate;

4A-4C depict cross-sectional views of one example of a sequence for forming nanowire structures with desired materials during the fabrication process of FIG. 3; and

fig. 5A-5B depict schematic diagrams of examples of horizontal full-ring gate (hGAA) structures.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

Detailed Description

Methods are provided for fabricating nanowire structures with controlled parasitic capacitance for horizontal all-around gate (hGAA) semiconductor device structures. In one example, a superlattice structure (superlattice structure) including different materials (e.g., a first material and a second material) arranged in an alternating stacked configuration may be formed on a substrate to be later used as a nanowire (e.g., channel structure) of a horizontal all-around gate (hGAA) semiconductor device structure. A selective oxidation process may be performed to selectively form an oxide layer on sidewalls of the first material in the superlattice structure with minimal oxidation occurring on the second material. The oxidation selectivity on the sidewalls of the first material and the second material in the superlattice structure is greater than 5: 1. In this way, the interface where the parasitic device is formed between the nanowire and the source/drain region is maintained and controlled so as to effectively reduce parasitic capacitance.

Fig. 1 is a cross-sectional view of an illustrative processing system 132 suitable for performing a selective oxidation process, as described further below. The processing system 132 may be

And

SE or

GT deposition systems, all of which are commercially available from Applied Materials inc, Santa Clara, California. It is contemplated that other processing systems (including those available from other manufacturers) may be suitable for practicing the present invention.

The processing system 132 includes a process chamber 100 coupled to a gas panel 130 and a controller 110. The processing chamber 100 generally includes a top 124, sides 101, and a bottom wall 122 that define an interior volume 126.

A support pedestal 150 is provided in the interior volume 126 of the chamber 100. The base 150 may be made of aluminum, ceramic, and other suitable materials. In one embodiment, the pedestal 150 is made of a ceramic material, such as aluminum nitride, which is a material suitable for use in high temperature environments, such as plasma processing environments, without causing thermal damage to the pedestal 150. The susceptor 150 may be moved in a vertical direction within the chamber 100 using a lift mechanism (not shown).

The pedestal 150 may include an embedded heater element 170, the embedded heater element 170 being adapted to control the temperature of a substrate 190 supported on the pedestal 150. In one embodiment, the susceptor 150 may be resistively heated by applying an electrical current from the power source 106 to the heater element 170. In one embodiment, the heater element 170 may be formed from a metal encapsulated in a nickel-iron-chromium alloy (e.g.,

) Nickel chromium wire in the sheath. The current supplied from the power supply 106 is regulated by the controller 110 to control the heat generated by the heater element 170, thereby maintaining the substrate 190 and susceptor 150 at a substantially constant temperature during film deposition at any suitable temperature rangeAnd (4) degree. In another embodiment, the base may be maintained at room temperature as desired. In yet another embodiment, the susceptor 150 may further include a cooler (not shown) as needed in order to cool the susceptor 150 in a range below room temperature as needed. The supplied current may be adjusted to selectively control the temperature of the pedestal 150 between about 100 degrees celsius and about 1100 degrees celsius, for example, between 200 degrees celsius and about 1000 degrees celsius, such as between about 300 degrees celsius and about 800 degrees celsius.

A temperature sensor 172, such as a thermocouple, may be embedded in the support pedestal 150 to monitor the temperature of the pedestal 150 in a conventional manner. The measured temperature will be used by the controller 110 to control the power supplied to the heater element 170 in order to maintain the substrate at the desired temperature.

A vacuum pump 102 is coupled to a port formed in the wall 101 of the chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure in the processing chamber 100. The vacuum pump 102 also evacuates the processed gases and byproducts of the process from the chamber 100.

A showerhead 120 having a plurality of apertures 128 is coupled to the top 124 of the processing chamber 100 above the substrate support pedestal 150. The apertures 128 of the showerhead 120 are used to introduce process gases into the chamber 100. The apertures 128 may be of different sizes, numbers, distributions, shapes, designs and diameters to facilitate the flow of various process gases for different process requirements. The showerhead 120 is coupled to a gas panel 130 to allow various gases to be supplied to the interior volume 126 during processing. The plasma is formed from the process gas mixture exiting the showerhead 120 to enhance pyrolysis of the process gases, resulting in deposition of material on the surface 191 of the substrate 190.

The showerhead 120 and the substrate support pedestal 150 may be formed as a pair of spaced apart electrodes in the interior volume 126. One or more RF power sources 140 provide a bias potential to the showerhead 120 through a matching network 138 in order to facilitate generation of a plasma between the showerhead 120 and the pedestal 150. Alternatively, the RF power source 140 and the matching network 138 may be coupled to the showerhead 120, the substrate support pedestal 150, or to both the showerhead 120 and the substrate support pedestal 150, or to an antenna (not shown) disposed outside the chamber 100. In one embodiment, the RF power source 140 may provide between about 10 watts and about 3000 watts at a frequency of about 30kHz to about 13.6 MHz.

An optional Water Vapor Generation (WVG) system 152 is coupled to the processing system 132, the Water Vapor Generation (WVG) system 152 being in fluid communication with the interior volume 126 defined in the process chamber 100. WVG System 152 by O₂And H₂The catalytic reaction of (a) produces ultra-high purity water vapor. In one embodiment, WVG system 152 has a reactor or canister lined with a catalyst in which water vapor is generated via a chemical reaction. The catalyst may include metals or alloys such as palladium, platinum, nickel, combinations thereof, and alloys thereof.

The controller 110 includes a Central Processing Unit (CPU)112, memory 116, and support circuits 114 for controlling process sequences and regulating the flow of gases from the gas panel 130 and the WVG system 152. The CPU 112 may be any form of a general purpose computer processor that can be used in an industrial environment. The software routines may be stored in a memory 116, such as random access memory, read only memory, floppy or hard disk drive, or other form of digital storage. The support circuits 114 are conventionally coupled to the CPU 112 and may include cache, clock circuits, input/output systems, power supplies, and the like. Bidirectional communication between the controller 110 and the various components of the processing system 132 is handled through a number of signal cables (collectively referred to as signal buses 118, some of which are shown in fig. 1).

Fig. 2 depicts a plan view of a semiconductor processing system 200 in which the methods described herein may be practiced. One processing system that may be adapted to benefit from the present invention is a 300mm Producer commercially available from applied materials, Inc. of Santa Clara, Calif^TMAnd (4) processing the system. The processing system 200 generally includes: a front stage 202 in which a substrate cassette 218 included in the FOUP214 is supported and substrates are loaded into and unloaded from the load lock chamber 209; a transfer chamber 211 housing a substrate handler 213; and a series of in-line process chambers 206 mounted on the conveyorAnd is fed into the chamber 211.

Each of the tandem process chambers 206 includes two process zones for processing substrates. The two process zones share a common gas supply, a common pressure control, and a common process gas exhaust/pumping system. The modular design of the system enables rapid conversion from any one configuration to any other. The arrangement and combination of chambers may be altered for the purpose of performing a particular process step. According to aspects of the invention, any of the tandem process chambers 206 may include a lid as described below, which includes one or more of the chamber configurations described above with reference to the process chamber 100 depicted in fig. 1. It should be noted that the processing chamber 100 may be configured to perform a deposition process, an etch process, a curing process, or a heating/annealing process, as desired. In one embodiment, the processing chamber 100, shown as a single chamber designed, may be incorporated into a semiconductor processing system 200.

In one embodiment, the processing system 132 may be adapted with one or more of a series of process chambers having support chamber hardware known to accommodate various other known processes, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etching, curing, or heating/annealing, etc. For example, the system 200 may be configured with one of the processing chambers 100 as a plasma deposition chamber for depositing, for example, a dielectric film on a substrate. This configuration maximizes development manufacturing utilization and, if desired, eliminates exposure of the etched film to the atmosphere.

A controller 240, including a Central Processing Unit (CPU)244, a memory 242 and support circuits 246, is coupled to the various components of the semiconductor processing system 200 in order to facilitate control of the processes of the present invention. Memory 242 may be any computer-readable medium, such as Random Access Memory (RAM), Read Only Memory (ROM), floppy disk, hard disk, or any other form of digital storage, whether local or remote to semiconductor processing system 200 or CPU 244. Support circuits 246 are coupled to CPU 244 to support the CPU in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuits and subsystems, and the like. A software routine or series of program instructions stored in memory 242, when executed by CPU 244, executes the tandem process chamber 206.

Fig. 3 is a flow diagram of one example of a method 300 for fabricating nanowire structures (e.g., channel structures) with composite materials for horizontal all-around gate (hGAA) semiconductor device structures. Fig. 4A-4C are cross-sectional views of a portion of a composite substrate corresponding to various stages of method 300. The method 300 may be used to form a nanowire structure of a desired material of a horizontal all-around gate (hGAA) semiconductor device structure on a substrate, which may be later used to form a Field Effect Transistor (FET). Alternatively, the method 300 may be advantageously used to fabricate other types of structures.

The method 300 begins at operation 302 by providing a substrate, such as the substrate 502 depicted in fig. 2 with the film stack 401 formed thereon as shown in fig. 4A. The substrate 502 may be a material such as crystalline silicon (e.g., Si <100> or Si <111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and Silicon On Insulator (SOI) patterned or unpatterned wafers, carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 502 may have various dimensions, such as 200mm, 300mm, 450mm, or other diameters, and may be a rectangular or square panel. Unless otherwise indicated, the examples described herein are performed on substrates having a diameter of 200mm, 300mm, or 450 mm.

The membrane stack 401 includes a multi-material layer 212 disposed on an optional material layer 504. In embodiments where the optional material layer 504 is not present, the film stack 401 may be formed directly on the substrate 502 as desired. In one example, the optional material layer 504 is an insulating material. Suitable examples of the insulating material may include a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or any suitable insulating material. Alternatively, the optional material layer 504 may be any suitable material, including a conductive material or a non-conductive material, as desired. The multi-material layer 212 includes at least one pair of layers, each pair including a first layer 212a and a second layer 212 b. Although depicted in FIG. 4AThe example shows four pairs, each pair comprising a first layer 212a and a second layer 212b (alternating pairs, each pair comprising a first layer 212a and a second layer 212b), but it should be noted that the number of pairs (each pair comprising a first layer 212a and a second layer 212b) can vary based on different process needs. In one particular embodiment, 4 pairs of the first layer 212a and the second layer 212b may be deposited to form the multi-material layer 212 on the substrate 502. In one embodiment, the thickness of each individual first layer 212a may be about

And about

Between, such as about

And the thickness of each individual second layer 212b may be about

And about

Between, such as about

The multi-material layer 212 may have a thickness of about

And about

Of total thickness, such as in the range of about

And about

In the meantime.

The first layer 212a may be a crystalline silicon layer formed by an epitaxial deposition process, such as a single crystal (single crystal)) A silicon layer, a polysilicon layer, or a monocrystalline (monocrystalline) silicon layer. Alternatively, the first layer 212a may be a doped silicon layer, including a p-type doped silicon layer or an n-type doped silicon layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, and the like. Suitable N-type dopants include N-dopants, P-dopants, As-dopants, Sb-dopants, and the like. In yet another example, the first layer 212a can be a group III-V material, such as a GaAs layer. The second layer 212b may be a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layer. Alternatively, the second layer 212b may be a doped silicon layer, including a p-type doped silicon layer or an n-type doped silicon layer. In yet another example, the second layer 212b can be a group III-V material, such as a GaAs layer. In yet another example, the first layer 212a can be a silicon layer and the second layer 212b is a metallic material having a coating of a high-k material on an outer surface of the metallic material. Suitable examples of high-k materials include hafnium oxide (HfO)₂) Zirconium dioxide (ZrO)₂) Hafnium oxy-silicate (HfSiO)₄) Hafnium aluminum oxide (HfAlO), zirconium oxysilicate (ZrSiO)₄) Tantalum dioxide (TaO)₂) Aluminum oxide, aluminum doped hafnium oxide, Bismuth Strontium Titanate (BST) or zirconium platinum titanate (PZT), and the like. In a particular embodiment, the coating is hafnium oxide (HfO)₂) And (3) a layer.

In the particular example depicted in fig. 4A, the first layer 212a is a crystalline silicon layer, such as a single crystalline silicon layer, a polycrystalline silicon layer, or a single crystalline silicon layer. The second layer 212b is a SiGe layer.

In some examples, a hard mask layer (not shown in fig. 4A) and/or a patterned photoresist layer may be disposed on the multi-material layer 212 to pattern the multi-material layer 212. In the example shown in fig. 4A, the multi-material layer 212 has been patterned in a previous patterning process in order to form an opening 402 in the multi-material layer 212, which may later have source/drain anchor heads formed therein.

In embodiments where the substrate 502 is a crystalline silicon layer and the insulating layer 504 is a silicon oxide layer, the first layer 212a may be an intrinsic epitaxial silicon layer and the second layer 212b is a SiGe layer. In another embodiment, the first layer 212a may be a doped silicon-containing layer and the second layer 212b may be an intrinsic epitaxial silicon layer. The doped silicon-containing layer may be a p-type dopant or an n-type dopant, or a SiGe layer as desired. In yet another embodiment where the substrate 502 is a Ge or GaAs substrate, the first layer 212a may be a GeSi layer and the second layer 212b may be an intrinsic epitaxial Ge layer, or vice versa. In yet another embodiment, where the substrate 502 is a GaAs layer having predominantly a crystal plane at <100>, the first layer 212a can be an intrinsic Ge layer and the second layer 212b a GaAs layer, or vice versa. It should be noted that the selection of the substrate material and the first and

second layers

212a, 212b in the multi-material layer 212 may be in different combinations utilizing the materials listed above.

At optional operation 303, a liner layer 404 may be formed on the sidewalls 405 of the multi-material layer 212, as shown in fig. 4B 2. Liner layer 404 may provide a substantially planar (e.g., uniform) surface that allows an oxide layer to later form thereon with good interfacial adhesion and planarity. The process for forming the oxide layer will be described later at operation 304. Accordingly, in embodiments where the sidewalls 405 of the multi-material layer 212 are substantially planar with a desired straightness, the liner layer 404 may be eliminated and an oxide layer may be formed directly on the sidewalls 405 of the multi-material layer 212 at operation 304.

In one example, liner layer 404 may be selected from materials that may help bridge the oxide layer to sidewalls 405 of multi-material layer 212 with good adhesion at the interface. Further, liner layer 404 may have a sufficient thickness to fill in the nanoscale rough surface from sidewalls 405 of the multi-material layer 212 so as to provide a substantially planar surface that allows an oxide layer to later be formed thereon with a desired level of planarity and flatness. In one example, liner layer 404 may have a thickness between about 0.5nm and about 5 nm.

In one embodiment, liner layer 404 is a silicon-containing dielectric layer, such as a silicon nitride-containing layer, a silicon carbide-containing layer, a silicon oxide-containing layer, e.g., SiN, SiON, SiC, SiCN, SiOC, or silicon oxycarbonitride, or a silicon material with a dopant, among others. The dopant formed in the silicon-containing dielectric layer may have a relatively low concentration, having the film properties of being rich in silicon atoms. At one endIn one example, liner layer 404 is a silicon nitride layer or a silicon oxynitride (SiON) having a thickness of about

And about

A thickness of between, such as about

Liner layer 404 may be formed by a CVD process, an ALD process, or any suitable deposition technique in a PVD, CVD, ALD, or other suitable plasma processing chamber.

At operation 304, after an optional liner layer 404 is formed on the sidewalls 405 of the multi-material layer 212, a selective oxide deposition may be performed to selectively form an oxide layer on certain regions of the multi-material layer 212. In examples where optional operation 303 is not performed and liner layer 404 is not formed on the substrate, a selective oxide deposition process may be performed directly on the substrate, as mentioned in fig. 4B 1.

Since the first layer 212a and the second layer 212b in the multi-material layer 212 are made of different materials, when a selective oxide deposition process is performed, an oxidation process may occur mainly on one material with respect to the other material. In the example depicted in fig. 4B1, where the first layer 212a is a silicon layer and the second layer 212B is a SiGe layer, the selective oxidation process may occur primarily on the sidewalls 406 of the second layer 212B, rather than on the first layer 212 a. The selective oxidation process that occurs on the sidewalls 406 of the second layer 212b forms an oxide layer 407 primarily on the sidewalls 406 of the second layer 212 b. It is believed that SiGe alloys have higher activity than the primary silicon-containing materials. Thus, when oxygen atoms are supplied, the oxygen atoms tend to react with the Si atoms in the SiGe alloy at a faster reaction rate than with Si atoms from the primarily silicon-containing material, thereby providing a selective deposition process to form an oxide layer 407 primarily on the sidewalls 406 of the second layer 212b of the SiGe alloy, but not on the first layer 212 a. A minimum oxide residue 411 may be present on the sidewalls 408 of the first layer 212 a.

The oxidation process consumes silicon atoms from the SiGe alloy in the second layer 212b, pulling the silicon atoms outward to react with oxygen atoms to form the oxide layer 407. Since Ge atoms can be activated and moved relatively easily during the oxidation process, silicon atoms in the second layer 212b are gradually pulled out and react with oxygen atoms to form an oxide layer 407 on the sidewalls 406.

In contrast, since the silicon atoms in the first layer 212a do not have Ge atoms to act as an active driver to actively push the silicon atoms outward to a position that allows reaction to react with oxygen atoms, the oxide layer formation rate in the first layer 212a is significantly lower than the oxide layer formation rate in the second layer 212b, thereby providing a selective oxidation process that forms the oxide layer 407 primarily on the sidewalls 406 of the second layer 212b rather than on the first layer 212 a. In one example, the selectivity of the oxidation rate between the second layer 212b (e.g., a SiGe layer) and the first layer 212a (e.g., a silicon layer) is greater than 5:1, such as about 6:1 and 10: 1.

In one embodiment, the selective oxidation process may be performed in a suitable plasma processing chamber, including a processing chamber, such as processing chamber 100 depicted in fig. 1 or other suitable plasma chamber. The process temperature is controlled within a low temperature range, such as less than 1200 degrees celsius. It is believed that the low temperature process may provide mild thermal energy to consume the silicon atoms and push the silicon atoms toward the surface of the sidewall where oxygen atoms are present in order to form silicon oxide 407 without damaging the lattice structure formed by the Ge atoms in film stack 401. In this way, a portion of the silicon atoms may be gradually converted into the oxide layer 407 without forming interface sites or atom vacancies. In one embodiment, the process temperature may be realized between about 100 degrees celsius to about 1100 degrees celsius, for example, between 200 degrees celsius to about 1000 degrees celsius, such as between about 300 degrees celsius and about 800 degrees celsius.

In one embodiment, the oxidation process may be in a plasma-containing environment (such as decoupled plasma oxidation or rapid thermal oxidation), a thermal environment (such as a furnace), or a thermal plasma environment (such as APCVD, SACVD, LPCVD, or LPCVD)Any suitable CVD process). The oxidation process may be performed by using an oxygen-containing gas mixture in a processing environment to react the multi-material layer 212. In one embodiment, the oxygen-containing gas mixture comprises at least one of an oxygen-containing gas with or without an inert gas. Suitable examples of oxygen-containing gases include O₂、O₃、H₂O、NO₂、N₂O, steam, water vapor, and the like. Suitable examples of inert gases supplied with the process gas mixture include at least one of Ar, He, Kr, and the like. In an exemplary embodiment, the oxygen-containing gas supplied in the oxygen-containing gas mixture is O having a flow rate between about 50sccm and about 1000sccm₂A gas.

During the oxidation process, several process parameters may be adjusted to control the oxidation process. In an exemplary embodiment, the process pressure is adjusted to be between about 0.1Torr and about atmospheric pressure (e.g., 760 Torr). In one example, the oxidation process as performed at operation 304 is configured to have a relatively high deposition pressure, such as a pressure greater than 100Torr, such as between about 300Torr and atmospheric pressure. Suitable techniques that may be used to perform the selective oxidation process at operation 304 may include a decoupled plasma oxidation process (DPO), a plasma enhanced chemical vapor deposition Process (PECVD), a low pressure chemical vapor deposition process (LPCVD), a sub-atmospheric pressure chemical vapor deposition process (SACVD), an atmospheric pressure chemical vapor deposition process (APCVD), a furnace process, an oxygen annealing process, a plasma immersion process, or any suitable process, as desired. In one embodiment, the oxidation process may be performed under Ultraviolet (UV) light irradiation.

In one embodiment, the oxidation process is completed when an oxide layer 407 of a desired thickness is formed on the sidewalls 406 of the second layer 212 b. In one example, the oxide layer 407 may have a thickness between about 1nm and about 10 nm. The total process time of the oxidation process may be determined by the time pattern after the desired portion of silicon atoms primarily react with oxygen atoms to form the desired thickness of the oxide layer 407. In one example, the substrate 502 is subjected to a selective oxidation process for about 5 seconds to about 5 minutes, depending on the oxidation rate of the second layer 212b, the pressure and flow rate of the gas. In an exemplary embodiment, the substrate 502 is exposed to the oxidation process for about 600 seconds or less.

Furthermore, in instances in which the liner layer 404 is formed on the sidewalls 405 of the multi-material layer 212, when a selective oxidation process is performed at operation 304, similarly, the oxide layer 416 may be selectively formed only on the sidewalls 406 of the second layer 212B with the liner layer 404 in contact therewith, as shown in fig. 4B 2'. As discussed above, the GeSi alloy in the second layer 212b is more reactive than the Si material present in the first layer 212 a. During the oxidation process, the Ge atoms may be activated by thermal energy from the oxidation process, thereby forming interface vacancies that allow oxygen atoms to be pulled into bonding with the silicon atoms. Thus, oxygen atoms from the selective oxidation process pass through the liner layer 404 to react with silicon atoms from the second layer 212b to form an oxide layer 416 on the sidewalls 406 of the second layer 212 b. Since the liner layer 404 provides a substantially planar surface on the sidewalls 405 of the multi-material layer 212, the oxide layer 416 formed in the second layer 212b under the liner layer 404 can still maintain a substantially planar surface on the sidewalls 405 to provide a straight sidewall profile for the nanowire structure as desired. In one embodiment, liner layer 404 in combination with oxide layer 416 may have a thickness between about 3nm and about 15nm, such as between about 7nm and about 8 nm.

After the oxide layers 416, 407 are formed in the film stack 401, the first layer 212a and the multi-material layer 212 having the second layer 212b to the bottom of which the oxide layers 416, 407 are formed may be used as nanowires 403 in a Field Effect Transistor (FET) with reduced parasitic capacitance and minimal device leakage.

At operation 306, a mild surface cleaning process is performed to selectively remove oxide residues 411 (if present) from the film stack 401 without damaging the surface of the film stack 401, as shown in fig. 4C. The oxide residue 411 may be removed by a dry etching process or a wet etching process as needed.

Fig. 5A depicts a schematic diagram of a multi-material layer 212 having a pair of first layers 212a and a second layer 212b with an oxide layer 407 formed therein for use in a horizontal all-around gate (hGAA) structure 500. The horizontal all-around gate (hGAA) structure 500 uses the multi-material layer 212 as a nanowire (e.g., channel) between a source/drain anchor 508 (also shown as source and

drain anchor

508a, 508b, respectively) and a gate structure 510. As shown in the enlarged view of the multi-material layer 212 in fig. 5B indicated by circle 514, the oxide layer 407 (or oxide layer 416 as previously shown in fig. 4B 2') formed at the bottom (e.g., or end) of the second layer 212B may help manage the interface where the second layer 212B contacts the gate structure 510 and/or the source/drain anchor 508a, 508B in order to reduce parasitic capacitance and maintain minimal device leakage.

Accordingly, methods are provided for forming nanowire structures of horizontal all-ring gate (hGAA) structures with reduced parasitic capacitance and minimal device leakage. The method utilizes a selective oxidation process to selectively form an oxide layer on certain types of materials from a multi-material layer in order to form a nanowire structure with reduced parasitic capacitance and minimal device leakage at the interface, which can later be used to form a horizontal all-around gate (hGAA) structure. Thus, a horizontal full-ring gate (hGAA) structure having the desired type of material and device electrical properties can be obtained, particularly for application in a horizontal full-ring gate field effect transistor (hGAA FET).

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of forming a nanowire structure on a substrate, the method comprising:

supplying an oxygen-containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of first and second layers having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer; and

selectively forming an oxide layer primarily on the second set of sidewalls in the second layer compared to the first set of sidewalls in the first layer,

wherein the multi-material layer is used to form nanowires between source and drain anchor heads in a horizontal all-around gate (hGAA) structure.

2. The method of claim 1, wherein supplying the oxygen-containing gas mixture further comprises:

forming an inner liner layer on the first and second sets of sidewalls of the first and second layers prior to supplying the oxygen containing gas mixture to the substrate.

3. The method of claim 2, wherein the liner layer is silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride or a doped silicon material.

4. The method of claim 2 wherein the liner layer is fabricated by an ALD process.

5. The method of claim 2, wherein the liner layer has a thickness between 0.5nm and 5 nm.

6. The method of claim 2, wherein the liner layer has a surface parallel to a plane of the oxide layer.

7. The method of claim 1, wherein the oxygen-containing gas mixture comprises a gas selected from the group consisting of O₂、O₃、H₂O、NO₂And N₂At least one oxygen-containing gas of the group consisting of O.

8. The method of claim 7, wherein H is₂O is in the form of steam or water vapor.

9. The method of claim 1, wherein the first layer of the multi-material layer is an intrinsic silicon layer and the second layer of the multi-material layer is a SiGe layer, while the substrate is a silicon substrate.

10. The method of claim 1, further comprising:

forming the horizontal full-ring gate (hGAA) structure using the openings defined in the multi-material layer.

11. The method of claim 1, wherein supplying the oxygen-containing gas mixture further comprises:

performing a decoupled plasma process to form the oxide layer on the second set of sidewalls in the second layer.

12. The method of claim 1, further comprising:

a cleaning process is performed to remove oxide residues from the substrate.

13. The method of claim 1, wherein the multi-material layer comprises at least 4 repeating pairs.

14. The method of claim 1, wherein the oxide layer has a thickness between 1nm and 10 nm.

15. The method of claim 1, wherein supplying the oxygen-containing gas mixture further comprises:

the substrate temperature is maintained between 200 degrees Celsius and 1000 degrees Celsius.

16. The method of claim 1, wherein the oxide layer is selectively formed by an Ultraviolet (UV) light irradiation process.

17. A method of forming a nanowire structure on a substrate, the method comprising:

forming primarily an oxide layer on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer includes repeating pairs of first and second layers having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer, wherein the oxide layer is selectively formed primarily on the second set of sidewalls in the second layer as compared to the first set of sidewalls in the first layer, wherein the multi-material layer is used to form nanowires between source and drain anchor heads in a horizontal all-around gate (hGAA) structure.

18. The method of claim 17, wherein the first layer of the multi-material layer is an intrinsic silicon layer and the second layer of the multi-material layer is a SiGe layer, while the substrate is a silicon substrate.

19. The method of claim 17, further comprising:

forming a liner layer on the first and second sets of sidewalls of the first and second layers prior to forming the oxide layer.

20. A method of forming a nanowire structure on a substrate, the method comprising:

forming an oxide layer primarily on a portion of a multi-material layer disposed on a substrate, wherein the multi-material layer includes repeating pairs of silicon and SiGe layers having first and second sets of sidewalls respectively exposed through openings defined in the multi-material layer, wherein the oxide layer is selectively formed primarily on the second set of sidewalls in the SiGe layer as compared to the first set of sidewalls in the silicon layer,