CN106454162B - Stacking-type cmos image sensor and its manufacturing method - Google Patents
Stacking-type cmos image sensor and its manufacturing method Download PDFInfo
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- CN106454162B CN106454162B CN201610805097.2A CN201610805097A CN106454162B CN 106454162 B CN106454162 B CN 106454162B CN 201610805097 A CN201610805097 A CN 201610805097A CN 106454162 B CN106454162 B CN 106454162B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
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Abstract
The present invention provides a kind of stacking-type cmos image sensor and its manufacturing methods, wherein, m row n column pixel is divided into multiple block of pixels, each block of pixels is connect with one or more signal processor, that is the pixel of every row or each column is divided into muti-piece, connect respectively with signal processor, even if thus having respective pixel existing defects among every row or each column, will not cause full line perhaps column of pixels defect so as to avoiding the black line or bright line problem of full line or permutation.
Description
Technical field
The present invention relates to ic manufacturing technology field, in particular to a kind of stacking-type cmos image sensor and its system
Make method.
Background technique
Cmos image sensor belongs to photoelectric component, and cmos image sensor is due to its manufacturing process and existing integrated electricity
Road manufacturing process is compatible, while its performance has many good qualities than original charge-coupled device (CCD) imaging sensor, and gradually
Mainstream as imaging sensor.Cmos image sensor can integrate driving circuit and pixel, simplify hardware
Design, while also reducing the power consumption of system.Cmos image sensor is due to that can take out electricity while acquiring optical signal
Signal, moreover it is possible to which real time processed images information, speed is faster than ccd image sensor, while cmos image sensor also has price
Cheaply, the advantages of bandwidth is larger, anti-blur, the flexibility of access and biggish fill factor and obtained a large amount of use, extensively
It is general to be applied in the multiple products such as industry automatic control and consumer electronics, such as monitor, video communication, toy.
Continuous pursuit with people to high quality image, stacking-type cmos image sensor are developed.Stacking-type
The pixel wafer that cmos image sensor generally includes logic wafer and is bonded on the logic wafer.Relative to traditional
Cmos image sensor (including cmos image sensor front-illuminated or back-illuminated cmos image sensors), stacking-type CMOS figure
As sensor has smaller chip structure and faster processing speed.But current stacking-type cmos image sensor
There is also some defects, for example, being easy to appear black line or bright line of full line or permutation etc..
Summary of the invention
It is existing to solve the purpose of the present invention is to provide a kind of stacking-type cmos image sensor and its manufacturing method
Stacking-type cmos image sensor is easy to appear the problem of black line or bright line of full line or permutation.
In order to solve the above technical problems, the present invention provides a kind of stacking-type cmos image sensor, the stacking-type CMOS
Imaging sensor includes: logic wafer and the pixel wafer that is bonded on the logic wafer；Wherein, the pixel wafer includes
M row n column pixel, m row n column pixel are divided into multiple block of pixels, and m, n are the natural number more than or equal to 2, the picture in each block of pixels
Plain line number is respectively less than m and pixel columns is respectively less than n；The logic wafer includes multiple signal processors, each block of pixels and one
A or multiple signal processor connections.
Optionally, in the stacking-type cmos image sensor, each block of pixels includes a pixel.
Optionally, in the stacking-type cmos image sensor, each block of pixels is connect with a signal processor.
Optionally, in the stacking-type cmos image sensor, the pixel wafer includes multiple transmission blocks, each
Each pixel in block of pixels is connect with the same transmission block, and each transmission block is connect with a signal processor.
Optionally, in the stacking-type cmos image sensor, each pixel in each block of pixels passes through one
Root or more connecting lines are connect with the same transmission block.
Optionally, in the stacking-type cmos image sensor, the logic wafer includes multiple transmission blocks, each
Each pixel in block of pixels is connect with the same transmission block, and each transmission block is connect with a signal processor.
The present invention also provides a kind of manufacturing method of stacking-type cmos image sensor, the stacking-type cmos image sensing
The manufacturing method of device includes:
Logic wafer is provided, the logic wafer includes multiple signal processors；
Pixel wafer is provided, the pixel wafer includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels, m, n
It is the natural number more than or equal to 2, the number of lines of pixels in each block of pixels is respectively less than m and pixel columns is respectively less than n；
By the pixel wafer and the logic wafer bonding, so that each block of pixels and one or more signal processing
Device connection.
Optionally, in the manufacturing method of the stacking-type cmos image sensor, each block of pixels includes a picture
Element.
Optionally, in the manufacturing method of the stacking-type cmos image sensor, the pixel wafer includes multiple
Transmission block, each pixel in each block of pixels are connect with the same transmission block, and the pixel wafer and the logic is brilliant
When round key closes, so that each transmission block is connect with a signal processor.
Optionally, in the manufacturing method of the stacking-type cmos image sensor, the logic wafer includes multiple
Transmission block, each transmission block are connect with a signal processor, when by the pixel wafer and the logic wafer bonding, so that
Each pixel in each block of pixels is connect with the same transmission block.
In stacking-type cmos image sensor provided by the invention and its manufacturing method, m row n column pixel is divided into multiple pictures
Plain block, each block of pixels are connect with one or more signal processor, that is to say, that the pixel of every row or each column is divided into
Muti-piece is connect with signal processor respectively, even if thus having respective pixel existing defects among every row or each column, will not be led
Cause full line perhaps column of pixels defect so as to avoiding the black line or bright line problem of full line or permutation.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the stacking-type cmos image sensor of the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of the stacking-type cmos image sensor of the embodiment of the present invention two；
Fig. 3 is the structural schematic diagram of the stacking-type cmos image sensor of the embodiment of the present invention three.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of stacking-type cmos image sensor proposed by the present invention and its system
The method of making is described in further detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It needs
Illustrate, attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly auxiliary is said
The purpose of the bright embodiment of the present invention.Particularly, the emphasis that each attached drawing needs to show is different, often all uses different ratios
Example.
[embodiment one]
Referring to FIG. 1, its structural schematic diagram for the stacking-type cmos image sensor of the embodiment of the present invention one.Such as Fig. 1
Shown, the stacking-type cmos image sensor 1 includes: that logic wafer 10 and the pixel being bonded on the logic wafer 10 are brilliant
Circle 11；Wherein, the pixel wafer 11 includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels, m, n be greater than etc.
Number of lines of pixels in 2 natural number, each block of pixels is respectively less than m and pixel columns is respectively less than n；The logic wafer 10 includes
Multiple signal processors, each block of pixels are connect with one or more signal processor.
In the embodiment of the present application, schematically, the equal value of the m and n is four, i.e., the described pixel wafer 11 includes four rows
Four column have 16 pixels altogether.Wherein, Fig. 1 shows the sectional view along line direction, that is, illustrates only four pixels in a line
Structural schematic diagram.
In the embodiment of the present application, each block of pixels includes a pixel, that is to say, that 16 pixels have been divided into 16
A block of pixels, i.e., each pixel are connect with a signal processor.It is specific as shown in Figure 1, i.e. pixel 110a and signal processing
Device 100a connection, pixel 110b are connect with signal processor 100b, and pixel 110c is connect with signal processor 100c, pixel 110d
It is connect with signal processor 100d.Any one pixel existing defects, other pixels are all unaffected as a result,.To mention
The high quality and reliability of stacking-type cmos image sensor 1.Further, each pixel connects with a signal processor
It connects, it is possible thereby to greatly improve the signal handling capacity of stacking-type cmos image sensor 1, i.e., quickly realizes photosignal
Conversion.
With continued reference to FIG. 1, in the embodiment of the present application, the pixel wafer 11 further includes connecting line, and each pixel is equal
It connect with a connecting line, and then is connect by connecting line with signal processor.Specifically, pixel 110a passes through connecting line 111a
It is connect with signal processor 100a, pixel 110b is connect by connecting line 111b with signal processor 100b, and pixel 110c passes through
Connecting line 111c is connect with signal processor 100c, and pixel 110d is connect by connecting line 111d with signal processor 100d.
Further, the logic wafer 10 also includes connecting line, and each signal processor is connect with a connecting line, into
And convenient for being connect with pixel.Specifically, signal processor 100a is connect with connecting line 101a, signal processor 100b and connecting line
101b connection, signal processor 100c are connect with connecting line 101c, and signal processor 100d is connect with connecting line 101d.It is preferred that
, connecting line 101a, connecting line 101b, connecting line 101c and connecting line 101d respectively with connecting line 111a, connecting line 111b, even
Wiring 111c and connecting line 111d is corresponded, consequently facilitating pixel 110a passes through connecting line 111a and connecting line 101a and signal
Processor 100a connection, pixel 110b are connect by connecting line 111b and connecting line 101b with signal processor 100b, pixel
110c is connect by connecting line 111c and connecting line 101c with signal processor 100c, and pixel 110d passes through connecting line 111d and company
Wiring 101d is connect with signal processor 100d.
In the embodiment of the present application, each pixel passes through different connecting lines and connect with signal processor, even if as a result,
A certain connecting line existing defects, will not influence entire row of pixels.For example, connecting line 111a and connecting line 101a itself or both
Junction existing defects, also only will affect the display of pixel 110a, and pixel 110b, pixel 110c and pixel 110d may be used
Normally to be shown under the control of corresponding signal processor and connecting line.
In the embodiment of the present application, the logic wafer 10 further includes dielectric layer, realizes multiple letters by the dielectric layer
Isolation number between processor and connecting line；Correspondingly, the pixel wafer 11 also further includes dielectric layer, pass through the dielectric layer
It realizes the isolation between multiple pixels and connecting line, the prior art that is isolated between device architecture is realized by dielectric layer, this
Application embodiment repeats no more this.
Correspondingly, the present embodiment also provides a kind of manufacturing method of stacking-type cmos image sensor 1, the stacking-type
The manufacturing method of cmos image sensor 1 includes:
Logic wafer 10 is provided, the logic wafer 10 includes multiple signal processors；
Pixel wafer 11 is provided, the pixel wafer 11 includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels,
M, n is the natural number more than or equal to 2, and the number of lines of pixels in each block of pixels is respectively less than m and pixel columns is respectively less than n；
The pixel wafer 11 is bonded with the logic wafer 10, so that each block of pixels and one or more signal
Processor connection.
In the embodiment of the present application, the pixel wafer 11 is patrolled with described using the compound bonding technology of copper and dielectric layer
Wafer 10 is collected to be bonded.
[embodiment two]
Referring to FIG. 2, its structural schematic diagram for the stacking-type cmos image sensor of the embodiment of the present invention two.Such as Fig. 2
Shown, the stacking-type cmos image sensor 2 includes: that logic wafer 20 and the pixel being bonded on the logic wafer 20 are brilliant
Circle 21；Wherein, the pixel wafer 21 includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels, m, n be greater than etc.
Number of lines of pixels in 2 natural number, each block of pixels is respectively less than m and pixel columns is respectively less than n；The logic wafer 20 includes
Multiple signal processors, each block of pixels are connect with one or more signal processor.
In the embodiment of the present application, same schematical, the m and the equal value of n are four, i.e., the described pixel wafer 21 includes
Four rows four column have 16 pixels altogether.Wherein, four in a line are illustrated only Fig. 2 shows the sectional view along line direction, that is,
The structural schematic diagram of pixel.
One of the present embodiment two and embodiment one the difference is that, in the present embodiment two, each block of pixels includes four
Pixel, specifically, four rows, four column pixel has been divided into the block of pixels of four two rows two column.In the embodiment of the present application, each pixel
The number of pixels for including in block is identical, and in the other embodiments of the application, the number of pixels for including in each block of pixels can also
With not identical.Here, each block of pixels connect with a signal processor namely four pixels of the same block of pixels with it is same
A signal processor connection.Wherein, Fig. 2 illustrates only the sectional view along line direction, namely illustrates only in two block of pixels
Two pixels, another two pixel and other two block of pixels in two block of pixels are not shown.
The present embodiment two and embodiment one another difference is that, the pixel wafer 21 further includes multiple transmission blocks,
Each pixel in each block of pixels is connect with the same transmission block, and each transmission block is connect with a signal processor.I.e.
The connection between block of pixels and signal processor is realized by transmission block, so that the connection between block of pixels and signal processor
It is more convenient.
Specifically, pixel 210a is connect by connecting line 211a with transmission block 212a, the pixel in the same block of pixels
210b is connect by connecting line 211b with transmission block 212a；Pixel 210c is connect by connecting line 211c with transmission block 212b, together
Pixel 210d in one block of pixels is connect by connecting line 211d with transmission block 212b.Meanwhile transmission block 212a is further through even
Wiring 201a is connect with signal processor 200a, and transmission block 212b is connect further through connecting line 201b with signal processor 200b.
Pixel 210a is just realized as a result, and pixel 210b is connect with signal processor 200a, pixel 210c and pixel 210d and signal
Processor 200b connection.
Here, can be convenient due to the presence of transmission block, reliably realizing company between block of pixels and signal processor
It connects.Particularly, the connecting line in logic wafer 20 (referring to connecting line 201a and connecting line 201b herein) can not be with pixel wafer
Connecting line in 21 corresponds and (refers to connecting line 211a, connecting line 211b, connecting line 211c and connecting line 211d herein), from
And simplify the formation of the connecting line in logic wafer 20, that is, it reduces and the precision etc. of the connecting line in logic wafer 20 is wanted
It asks.
The third of the present embodiment two and embodiment one the difference is that, each pixel picks out that there are two connecting lines, to protect
The connection reliability between each pixel and other component is demonstrate,proved.Here, pixel 210a passes through two connecting line 211a and transmission
Block 212a connection, the pixel 210b in the same block of pixels are connect by two connecting line 211b with transmission block 212a；Pixel
210c is connect by two connecting line 211c with transmission block 212b, and the pixel 210d in the same block of pixels passes through two connecting lines
211d is connect with transmission block 212b.Thereby it is ensured that connection reliability between each pixel and corresponding transmission block.
In the embodiment of the present application, the logic wafer 20 also further includes dielectric layer, is realized by the dielectric layer multiple
Isolation between signal processor and connecting line；Correspondingly, the pixel wafer 21 also further includes dielectric layer, pass through the medium
Layer realizes the isolation between multiple pixels, connecting line and transmission block, realizes being isolated into now between device architecture by dielectric layer
There is technology, the embodiment of the present application repeats no more this.
Correspondingly, the present embodiment also provides a kind of manufacturing method of stacking-type cmos image sensor 2, the stacking-type
The manufacturing method of cmos image sensor 2 includes:
Logic wafer 20 is provided, the logic wafer 20 includes multiple signal processors；
Pixel wafer 21 is provided, the pixel wafer 21 includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels,
M, n is the natural number more than or equal to 2, and the number of lines of pixels in each block of pixels is respectively less than m and pixel columns is respectively less than n；
The pixel wafer 21 is bonded with the logic wafer 20, so that each block of pixels and one or more signal
Processor connection.
In the embodiment of the present application, the pixel wafer 21 includes multiple transmission blocks, specifically, every in each block of pixels
A pixel is connect with the same transmission block, when the pixel wafer 21 is bonded with the logic wafer 20, so that each biography
Defeated piece connect with a signal processor.
[embodiment three]
Referring to FIG. 3, its structural schematic diagram for the stacking-type cmos image sensor of the embodiment of the present invention three.Such as Fig. 3
Shown, the stacking-type cmos image sensor 3 includes: that logic wafer 30 and the pixel being bonded on the logic wafer 30 are brilliant
Circle 31；Wherein, the pixel wafer 31 includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels, m, n be greater than etc.
Number of lines of pixels in 2 natural number, each block of pixels is respectively less than m and pixel columns is respectively less than n；The logic wafer 30 includes
Multiple signal processors, each block of pixels are connect with one or more signal processor.
In the embodiment of the present application, same schematical, the m and the equal value of n are four, i.e., the described pixel wafer 31 includes
Four rows four column have 16 pixels altogether.Wherein, Fig. 3 shows the sectional view along line direction, that is, illustrates only four in a line
The structural schematic diagram of pixel.
One of the present embodiment three and embodiment one the difference is that, in the present embodiment three, each block of pixels includes four
Pixel, specifically, four rows, four column pixel has been divided into the block of pixels of four two rows two column.In the embodiment of the present application, each pixel
The number of pixels for including in block is identical, and in the other embodiments of the application, the number of pixels for including in each block of pixels can also
With not identical.Here, each block of pixels connect with a signal processor namely four pixels of the same block of pixels with it is same
A signal processor connection.Wherein, Fig. 3 illustrates only the sectional view along line direction, namely illustrates only in two block of pixels
Two pixels, another two pixel and other two block of pixels in two block of pixels are not shown.
The present embodiment three and embodiment one another difference is that, the logic wafer 30 further includes multiple transmission blocks,
Each pixel in each block of pixels is connect with the same transmission block, and each transmission block is connect with a signal processor.I.e.
The connection between block of pixels and signal processor is realized by transmission block, so that the connection between block of pixels and signal processor
It is more convenient.
Specifically, pixel 310a is connect by connecting line 311a with transmission block 302a, the pixel in the same block of pixels
310b is connect by connecting line 311b with transmission block 302a；Pixel 310c is connect by connecting line 311c with transmission block 302b, together
Pixel 310d in one block of pixels is connect by connecting line 311d with transmission block 302b.Meanwhile transmission block 302a is further through even
Wiring 301a is connect with signal processor 300a, and transmission block 302b is connect further through connecting line 301b with signal processor 300b.
Pixel 310a is just realized as a result, and pixel 310b is connect with signal processor 300a, pixel 310c and pixel 310d and signal
Processor 300b connection.
Here, can be convenient due to the presence of transmission block, reliably realizing company between block of pixels and signal processor
It connects.Particularly, the connecting line in logic wafer 30 (referring to connecting line 301a and connecting line 301b herein) can not be with pixel wafer
Connecting line in 31 corresponds and (refers to connecting line 311a, connecting line 311b, connecting line 311c and connecting line 311d herein), from
And simplify the formation of the connecting line in logic wafer 30 and the connecting line in pixel wafer 31, that is, it reduces for logic crystalline substance
Precision of connecting line in circle 30 and the connecting line in pixel wafer 31 etc. requires.
In the embodiment of the present application, the logic wafer 30 also further includes dielectric layer, is realized by the dielectric layer multiple
Isolation between signal processor, connecting line and transmission block；Correspondingly, the pixel wafer 31 also further includes dielectric layer, pass through
The dielectric layer realizes the isolation between multiple pixels and connecting line, realizes being isolated into now between device architecture by dielectric layer
There is technology, the embodiment of the present application repeats no more this.
Correspondingly, the present embodiment also provides a kind of manufacturing method of stacking-type cmos image sensor 3, the stacking-type
The manufacturing method of cmos image sensor 3 includes:
Logic wafer 30 is provided, the logic wafer 30 includes multiple signal processors；
Pixel wafer 31 is provided, the pixel wafer 31 includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels,
M, n is the natural number more than or equal to 2, and the number of lines of pixels in each block of pixels is respectively less than m and pixel columns is respectively less than n；
The pixel wafer 31 is bonded with the logic wafer 30, so that each block of pixels and one or more signal
Processor connection.
In the embodiment of the present application, the logic wafer 30 includes multiple transmission blocks, at each transmission block and a signal
Device connection is managed, when the pixel wafer 31 is bonded with the logic wafer 30, so that each pixel in each block of pixels is equal
It is connect with the same transmission block.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (7)
1. a kind of stacking-type cmos image sensor, which is characterized in that the stacking-type cmos image sensor includes: logic crystalline substance
Circle and the pixel wafer being bonded on the logic wafer；Wherein, the pixel wafer includes m row n column pixel, m row n column pixel
It is divided into multiple block of pixels, m, n are the natural number more than or equal to 2, and the number of lines of pixels in each block of pixels is respectively less than m and pixel column
Number is respectively less than n；The logic wafer includes multiple signal processors, and each block of pixels and one or more signal processor connect
It connects；
Wherein, the pixel wafer or the logic wafer include multiple transmission blocks, and each pixel in each block of pixels is logical
It crosses one or more connecting line to connect with the same transmission block, each transmission block is connect with a signal processor.
2. stacking-type cmos image sensor as described in claim 1, which is characterized in that each block of pixels includes a picture
Element.
3. stacking-type cmos image sensor as claimed in claim 2, which is characterized in that at each block of pixels and a signal
Manage device connection.
4. a kind of manufacturing method of stacking-type cmos image sensor, which is characterized in that the stacking-type cmos image sensor
Manufacturing method include:
Logic wafer is provided, the logic wafer includes multiple signal processors；
Pixel wafer is provided, the pixel wafer includes m row n column pixel, and m row n column pixel is divided into multiple block of pixels, and m, n are
Natural number more than or equal to 2, the number of lines of pixels in each block of pixels is respectively less than m and pixel columns is respectively less than n；
By the pixel wafer and the logic wafer bonding, so that each block of pixels and one or more signal processor connect
It connects；
Wherein, the pixel wafer or the logic wafer include multiple transmission blocks, and each pixel in each block of pixels is logical
It crosses one or more connecting line to connect with the same transmission block, each transmission block is connect with a signal processor.
5. the manufacturing method of stacking-type cmos image sensor as claimed in claim 4, which is characterized in that each block of pixels packet
Include a pixel.
6. the manufacturing method of stacking-type cmos image sensor as claimed in claim 4, which is characterized in that the pixel wafer
Including multiple transmission blocks, when by the pixel wafer and the logic wafer bonding, so that at each transmission block and a signal
Manage device connection.
7. the manufacturing method of stacking-type cmos image sensor as claimed in claim 4, which is characterized in that the logic wafer
Including multiple transmission blocks, when by the pixel wafer and the logic wafer bonding, so that each pixel in each block of pixels
It is connect with the same transmission block.
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