CN106341153A - High-speed transceiver - Google Patents

Abstract

The high-speed transceiver of the present invention has the advantages of low power consumption, small size, easy configuration, high efficiency, etc., and greatly reduces communication costs. The present invention comprises FPGA, transmitter channel and receiver channel; Transmitter channel is made up of physical coding sublayer and physical medium additional sublayer, and receiver channel is also made up of physical coding sublayer and physical medium additional sublayer; The physical encoding sublayer of the receiver channel includes phase compensation FIFO, byte serializer, 8B/10B encoder, word aligner, rate matching FIFO, 8B/10B decoder, byte deserializer, byte sorter, Phase Compensation FIFO, Physical Media Additional Sublayer for Transmitter Channel and Receiver Channel Includes Analog Circuitry for I/O Buffers, CDR, Serializer/Deserializer; CDR includes Phase Lock Controller, Phase Difference, Phase The detector, the phase divider, and the signal output end of the phase lock controller are connected with the signal input end of the phase difference device; the transmitter channel and the receiver channel are connected with FPGA.

Description

A high-speed transceiver

technical field

The invention belongs to the technical field of digital systems, and in particular relates to a high-speed transceiver.

Background technique

With the continuous development of technology, high-speed serial I/O technology has become the current trend instead of traditional parallel I/O technology. The fastest parallel bus interface speed is 133 MB/s of ATA7. The transmission rate provided by the SATA1.0 specification released in 2003 has reached 150 MB/s. The theoretical speed of SATA3.0 has reached 600 MB/s. When working at high speed, the parallel bus is susceptible to interference and crosstalk, which makes the wiring quite complicated. The use of serial transceivers can simplify layout design and reduce the number of connectors. When having the same bus bandwidth, the power consumption of the serial interface is also lower than that of the parallel port. And the working mode of the device changes from parallel transmission to serial transmission, and the serial speed can be doubled as the frequency increases.

Based on the current FPGA has the advantages of embedded Gb rate level and low power consumption architecture, it enables designers to use efficient EDA tools to quickly solve protocol and rate changes. With the wide application of FPGA, the integration of transceivers in FPGA has become an effective way to solve the problem of equipment transmission speed.

Contents of the invention

The present invention aims at the above problems and provides a high-speed transceiver; the present invention has the advantages of low power consumption, small size, easy configuration, high efficiency, etc., reduces the required transmission channels and the number of device pins, thereby greatly reducing communication costs .

To achieve the above object of the present invention, the present invention adopts the following technical solutions.

A kind of high-speed transceiver of the present invention comprises FPGA, sender channel and receiver channel; Described sender channel is made up of physical coding sublayer and physical medium additional sublayer, and described receiver channel is also made up of physical coding sublayer and physical The medium additional sub-layer is formed; its structural points are: the physical encoding sub-layer of the transmitter channel and the receiver channel includes a phase compensation FIFO, a byte serializer, an 8B/10B encoder, a word aligner, a rate matching FIFO, 8B/10B Decoder, Byte Deserializer, Byte Sequencer, Phase Compensation FIFO, Physical Media Additional Sublayers for the Transmitter and Receiver Channels Analog Circuitry including I/O Buffers, CDR, Serial Device/deserializer; The CDR includes a phase lock controller, a phase differencer, a phase detector, a phase frequency divider, and the signal output of the phase lock controller is connected to the signal input of the phase differencer; The transmitter channel and receiver channel are connected to FPGA.

As a preferred solution of the present invention, the deserializer uses a high-speed recovered clock on the CDR.

The beneficial effect of the present invention is.

The invention provides a high-speed transceiver. The high-speed transceiver makes it possible to transmit a large amount of data point-to-point. This serial communication technology makes full use of the channel capacity of the transmission medium. Compared with the previous parallel data bus, the required transmission channel is reduced. and device pin count, thereby greatly reducing communication costs. The transceiver of the present invention has the advantages of low power consumption, small size, easy configuration, high efficiency, etc., so that it can be easily integrated into the bus system. In the high-speed serial data transmission protocol, the performance of the transceiver plays a decisive role in the transmission rate of the bus interface, and also affects the performance of the bus interface system to a certain extent. The invention analyzes the realization of the high-speed transceiver module on the FPGA platform, and also provides useful references for the realization of various high-speed serial protocols.

Description of drawings

FIG. 1 is a structural diagram of a high-speed transceiver of the present invention.

FIG. 2 is a CDR structure diagram of a high-speed transceiver of the present invention.

detailed description

Referring to Fig. 1 and shown in Fig. 2, a kind of high-speed transceiver of the present invention comprises FPGA, transmitter channel and receiver channel; Described transmitter channel is made up of physical encoding sublayer and physical medium additional sublayer, and described receiver The channel is also composed of a physical encoding sublayer and a physical medium additional sublayer; the key points of its structure are: the physical encoding sublayer of the transmitter channel and receiver channel includes a phase compensation FIFO, a byte serializer, and an 8B/10B encoder , Word Aligner, Rate Match FIFO, 8B/10B Decoder, Byte Deserializer, Byte Sequencer, Phase Compensation FIFO, the physical medium additional sublayer of the transmitter channel and receiver channel includes I/O buffering The analog circuit of the device, CDR, serializer/deserializer; The CDR includes a phase lock controller, a phase difference device, a phase detector, a phase frequency divider, and the signal output terminal of the phase lock controller is connected to the phase The signal input terminals of the difference device are connected; the transmitter channel and the receiver channel are connected with FPGA.

As shown in Figure 2, the signal output terminal of the phase lock controller is connected with the signal input terminal of the phase difference device, the output terminal of the phase difference device is divided into high-speed CLK and low-speed CLK, and the low-speed CLK is divided into The output of the frequency converter, the phase interpolator outputs a clock sampling signal to the phase detector, and the signal output terminal of the phase detector is connected to the phase interpolator.

The deserializer uses the high speed recovered clock on the CDR.

The 8B/10B encoder receives 8-bit data and 1-bit control code, and converts it into a 10-bit code group. On the one hand, the encoder can transmit an equal number of 0s and 1s, up to 5 all 0s or all 1s, which provides a good DC balance and a good jump density, which is conducive to improving the reliability of transmission, thus Reduce intersymbol interference so that the receiver can lock the phase on the received data stream; on the other hand, it can provide data with a specific code pattern that can better identify boundaries, that is, establish word boundaries in the data stream, and the receiver can use specific The code pattern divides the bytes.

The byte serializer bisects the parallel data bit width from the phase compensation FIFO module. The valid low byte is forwarded first, followed by the valid high byte. While maintaining the system transmission data rate, the system transmission clock rate is reduced, that is, while meeting the maximum FPGA architecture frequency limit, it is realized to enable the transmission channel to operate at a higher data rate.

The phase compensation FIFO compensates the phase difference between the low-speed parallel clock and the high-speed interface clock of the FPGA architecture, is a shallow FIFO, and compensates the phase difference of the clock between the FIFO core and the transceiver PCS.

The deserializer corresponds to the transmitter byte serializer, which converts the received serial data into 8-bit or 10-bit parallel data. The deserializer runs at half the serial data rate using the high-speed recovered clock on the CDR.

The 8B/10B decoder receives 10-bit data and decodes it into an 8-bit data and a 1-bit control identifier. Two 8B/10B decoders are used to detect incorrectly encoded code groups and detect parity errors, which can be bypassed.

It can be understood that the above specific descriptions of the present invention are only used to illustrate the present invention and are not limited to the technical solutions described in the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can still be modified or Equivalent replacements to achieve the same technical effect; as long as they meet the needs of use, they are all within the protection scope of the present invention.

Claims (2)

1. A high-speed transceiver, comprising FPGA, sender channel and receiver channel; Described sender channel is made up of physical coding sublayer and physical medium additional sublayer, and described receiver channel is also made up of physical coding sublayer and physical The medium additional sublayer is composed; it is characterized in that: the physical encoding sublayer of the transmitter channel and the receiver channel includes a phase compensation FIFO, a byte serializer, an 8B/10B encoder, a word aligner, a rate matching FIFO, an 8B /10B Decoder, Byte Deserializer, Byte Sequencer, Phase Compensation FIFO, Physical Medium Additional Sublayer for the Transmitter Channel and Receiver Channel Analog Circuitry including I/O Buffers, CDR, Serializer / deserializer; the CDR includes a phase-locked controller, a phase differencer, a phase detector, and a phase frequency divider, and the signal output of the phase-locked controller is connected to the signal input of the phase differencer; The transmitter channel and receiver channel described above are connected to the FPGA. 2. A high-speed transceiver according to claim 1, wherein the deserializer uses a high-speed recovered clock on the CDR.