Summary of the invention
To solve existing technical problem, the embodiment of the present invention provides a kind of filtering counteracting method and device by force.
The embodiment of the present invention provides a kind of strong filtering counteracting method, is applied to strong filtering canceller, and described device is parallel
It is provided with N concurrent equalizer, N=2n, the n is positive integer, which comprises
Noise in input signal channel is smoothed, obtains receiving signal;
According to the reception signal and theory signal, parallel input weight is calculated;
According to the parallel input weight, determines and sentence result and corresponding soft value firmly;
According to the soft value and it is described sentence firmly as a result, determining output valve and export.
Preferably, it is described according to the parallel input weight, it determines and sentences result firmly, comprising:
The parallel input weight being calculated is divided into first group and second group by preset rules;
It determines and reaches the first specified the smallest weighted value of node in described first group for the first MINIMUM WEIGHT weight values, described in determination
It is the second MINIMUM WEIGHT weight values that the second specified the smallest weighted value of node is reached in second group;
According to the first MINIMUM WEIGHT weight values and the second MINIMUM WEIGHT weight values, inquiry is preset to sentence register lookup table firmly, obtains
Result is sentenced firmly to described.
Preferably, it is described according to the soft value and it is described sentence firmly output valve and exported as a result, determining, comprising:
When sentencing result firmly is the first setting value, determine that preset fixed value is output valve and exports;
When sentencing result firmly is the second setting value, determine that the soft value is output valve and exports.
Preferably, the noise in input signal channel is smoothed, obtain receiving signal, comprising:
The noise in input signal channel is smoothed by first-order lag filtering, obtains receiving signal.
Preferably, the balanced device is four concurrent equalizers, the balanced device is Viterbi viterbi balanced device.
The embodiment of the present invention provides a kind of strong filtering canceller, and described device is provided with N concurrent equalizer, N=parallel
2n, the n is positive integer, described device further include:
Weight calculation unit obtains receiving signal for being smoothed the noise in input signal channel;According to
The reception signal and theory signal, calculate parallel input weight;
Acs unit, for determining and sentencing result and corresponding soft value firmly according to the parallel input weight;
Recall soft value unit, for according to the soft value and it is described sentence firmly as a result, determining output valve and export.
Preferably, the acs unit, for the parallel input weight being calculated to be divided by preset rules
First group and second group;
It determines and reaches the first specified the smallest weighted value of node in described first group for the first MINIMUM WEIGHT weight values, described in determination
It is the second MINIMUM WEIGHT weight values that the second specified the smallest weighted value of node is reached in second group;
According to the first MINIMUM WEIGHT weight values and the second MINIMUM WEIGHT weight values, inquiry is preset to sentence register lookup table firmly, obtains
Result is sentenced firmly to described.
Preferably, the backtracking soft value unit, for determining preset fixed value when sentencing result firmly is the first setting value
For output valve and export;
When sentencing result firmly is the second setting value, determine that the soft value is output valve and exports.
Preferably, the weight calculation unit, for by first-order lag filtering to the noise in input signal channel into
Row smoothing processing obtains receiving signal.
Preferably, the balanced device is four concurrent equalizers, the balanced device is Viterbi viterbi balanced device.
From the foregoing, it will be observed that the technical solution of the embodiment of the present invention includes: to be applied to strong filtering canceller, described device is parallel
It is provided with N concurrent equalizer, N=2n, the n is positive integer, is smoothed, obtains to the noise in input signal channel
Receive signal;According to the reception signal and theory signal, parallel input weight is calculated;According to the parallel input weight, really
It is fixed to sentence result and corresponding soft value firmly;According to the soft value and it is described sentence firmly as a result, determining output valve and export.The present invention is implemented
The technical solution of example can effectively offset strong filtering, guarantee transmission performance.
Specific embodiment
A kind of strong filtering counteracting method provided in an embodiment of the present invention, is applied to strong filtering canceller, described device is simultaneously
Row is provided with N concurrent equalizer, N=2n, the n is positive integer, as shown in Figure 1, which comprises
Step 101 is smoothed the noise in input signal channel, obtains receiving signal;
Specifically, the noise in input signal channel is smoothed, obtain receiving signal, comprising:
The noise in input signal channel is smoothed by first-order lag filtering, obtains receiving signal.
In practical applications, formula Y can be usedk=(1- α) * Xk+α*Xk-1Realize noise smoothing, wherein X is input letter
Number, Y is to receive signal, and α is the first parameter, and the α may be greater than 0 coefficient less than 1, can be set according to concrete scene
It is fixed;The k indicates that current sampling point, the K-1 indicate the sampled point before current sampling point.
Step 102, according to the reception signal and theory signal, calculate parallel input weight;
In practical applications, formula W=(Y-S) can be used2, wherein S representation theory signal.
Step 103, according to the parallel input weight, determine and sentence result and corresponding soft value firmly;
Specifically, it is described according to the parallel input weight, it determines and sentences result firmly, comprising:
The parallel input weight being calculated is divided into first group and second group by preset rules;Here, described
One group identical with the quantity of described second group of parallel input weight, in practical applications, will can currently input corresponding for 0
Weight is divided into group, is that 1 corresponding weight is divided into another group by current input.
It determines and reaches the first specified the smallest weighted value of node in described first group for the first MINIMUM WEIGHT weight values, described in determination
It is the second MINIMUM WEIGHT weight values that the second specified the smallest weighted value of node is reached in second group;
According to the first MINIMUM WEIGHT weight values and the second MINIMUM WEIGHT weight values, inquiry is preset to sentence register lookup table firmly, obtains
Result is sentenced firmly to described.
Step 104, according to the soft value and it is described sentence firmly as a result, determining output valve and export.
Specifically, it is described according to the soft value and it is described sentence firmly output valve and exported as a result, determining, comprising:
When sentencing result firmly is the first setting value, determine that preset fixed value is output valve and exports;
When sentencing result firmly is the second setting value, determine that the soft value is output valve and exports.
In practical applications, it can set when sentencing result firmly is 1, determine preset fixed value output valve and to export;
When sentencing result firmly is 0, determine that the soft value is output valve and exports.
What needs to be explained here is that balanced device described in the present embodiment is four concurrent equalizers, the balanced device is Wei Te
Than viterbi balanced device.
It is understood that the embodiment of the present invention can be applied in optical transmission device.
The embodiment of the invention provides a kind of strong filtering canceller, described device is provided with N concurrent equalizer, N parallel
=2n, the n is positive integer, as shown in Fig. 2, described device further include:
Weight calculation unit 201 obtains receiving signal for being smoothed the noise in input signal channel;
According to the reception signal and theory signal, parallel input weight is calculated;
Acs unit 202, for determining and sentencing result and corresponding soft value firmly according to the parallel input weight;
Recall soft value unit 203, for according to the soft value and it is described sentence firmly as a result, determining output valve and export.
What needs to be explained here is that balanced device described in the present embodiment is four concurrent equalizers, the balanced device can be
Viterbi viterbi balanced device.
In one embodiment, the acs unit, for by the parallel input weight being calculated by default rule
Then it is divided into first group and second group;
It determines and reaches the first specified the smallest weighted value of node in described first group for the first MINIMUM WEIGHT weight values, described in determination
It is the second MINIMUM WEIGHT weight values that the second specified the smallest weighted value of node is reached in second group;
According to the first MINIMUM WEIGHT weight values and the second MINIMUM WEIGHT weight values, inquiry is preset to sentence register lookup table firmly, obtains
Result is sentenced firmly to described.
In one embodiment, the backtracking soft value unit, for determining preset when sentencing result firmly is the first setting value
Fixed value is output valve and exports;
When sentencing result firmly is the second setting value, determine that the soft value is output valve and exports.
In one embodiment, the weight calculation unit, for being filtered by first-order lag in input signal channel
Noise is smoothed, and obtains receiving signal.
The strong filtering cancellation technology scheme that the embodiment of the present invention is proposed, using the parallel viterbi balanced device of N, the N's
Quantity can be 2 power side, i.e., 2n, wherein n is positive integer.
The embodiment of the present invention eliminates letter using the noise in first-order lag filtering channel, the parallel viterbi balanced device of N
Crosstalk between number.The embodiment of the present invention is made that innovation in structure, so that using the system area of technical solution of the present invention
Small, small power consumption, handling capacity is big, and realization price of hardware is small.The technical solution of the embodiment of the present invention can be in 100G optic communication
It is achieved and verifies in DSP processing chip, system can effectively offset the influence of strong filter effect in real channel, protect
In the case of card reaches 128Gbit/s handling capacity, more traditional realization area reduces by 70%, lower power consumption 70%.
It describes in detail to one embodiment of the invention, is illustrated in the present embodiment using N=4 below, other values
Implementation is similar.
The concrete scheme of the present embodiment is realized in four steps: 1, passing through the noise in first-order lag filtering channel;
2, four parallel input weight values are calculated;3, it completes acs unit output and sentences result and soft value firmly;4, result output is sentenced according to hard
Recall soft value outputs;Below by four steps in step-by-step instructions this method.
1, pass through the noise in first-order lag filtering channel.
In Fig. 4, input signal X obtains receiving signal Y after first-order lag filter circuit is smoothk, specifically, Yk=
(1-α)*Xk+α*Xk-1, Yk-1=(1- α) * Xk-1+α*Xk-2, Yk-2=(1- α) * Xk-2+α*Xk-3, Yk-3=(1- α) * Xk-3+α*
Xk-4, wherein in chronological sequence sequence, k indicate that the 5th sampled point (current sampling point), k-1 indicate that the 4th sampled point, k-2 indicate
Third sampled point, k-3 indicate that the second sampled point, k-4 indicate the first sampled point.Fig. 3 is state transition diagram, as shown in figure 3, in figure
Every line all contains 8 paths.
2, four parallel input weight values are calculated.
First below to the reception signal Y derived under serial inputkIt is introduced with corresponding weight W.
Assume initially that δ is input signal power, Xk=0 corresponding input signal power is-δ, Xk=1 corresponding input letter
Number power is δ, and bringing the δ into above-mentioned first-order lag Filtering Formula can be obtained Yk;Then it calculates and receives signal Y and theoretical letter
Number S directly poor square, obtains weight W;Finally identical entry in all weights is removed, obtains serial input signals all situations
Under, the relative value of corresponding all weights, table 1 is that serial input exports truth table.
Xk |
Xk-1 |
Yk |
W |
-δ |
-δ |
-δ |
(S+δ)2=S2+2δS+δ2→S |
-δ |
δ |
-δ*(1-2α) |
(S+δ(1-2α))2=S2+2δ(1-2α)S+δ2-4δ2α(1-α)→βS-γ |
δ |
-δ |
δ*(1-2α) |
(S-δ(1-2α))2=S2-2δ(1-2α)S+δ2-4δ2α(1-α)→-βS-γ |
δ |
δ |
δ |
(S-δ)2=S2-2δS+δ2→-S |
Table 1
Correspondingly, to the reception signal Y calculated under parallel inputkWith being described below for corresponding weight W.
Firstly for the parallel scheme of N=4, according to table 1, Y=- δ when inputting 00, Y=- δ * (1-2 α), defeated when inputting 01
Y=δ * (1-2 α) when entering 10, Y=δ when inputting 11, therefore parallel the first truth table of input and output of N=4 can be calculated, such as table 2
It is shown.
Table 2
Secondly, setting the theory signal received as Sk、Sk-1、Sk-2、Sk-3, signal Y is received according to obtained in table 2k、Yk-1、
Yk-2、Yk-3, with reference to the calculation method of weight under serial input, available N=4 parallel under each weight;By every weight
The sum of successively subtract Sk 2、Sk-1 2、Sk-2 2、Sk-3 2、4δ2, then divided by 2 δ, the weight W that identical entry is simplified is subtracted, referring to 3 institute of table
Show, table 3 is parallel the second truth table of input and output of N=4.Wherein the second parameter beta=1-2 α, the third parameter α of γ=2 (1-
α) δ, the 4th parameter d=W1-W0, δ=0.89.
Table 3
3, it completes acs unit output and sentences result and soft value firmly.
32 weighted values are divided into two groups, select currently to reach the MINIMUM WEIGHT weight values of node 1 as W0, and reach node 0
MINIMUM WEIGHT weight values as W1;
It calculates
Work as W0, W1When equal to a certain weight, register inquiry is sentenced firmly by searching for as shown in table 4 in acs unit
Result is sentenced in table, selection output firmlyAnd To backtracking
Soft value unit is sentenced in register group firmly.
What needs to be explained here is that weight calculation unit implementation method in Fig. 5 can be obtained by table 3, it can be seen that 32
There is a large amount of identical arithmetic element in weight, it can be individually using identical arithmetic element as standalone module in hardware realization
Exampleization is realized simple.Wherein α, β=1-2 alpha, gamma=2 α (1- α) δ, can direct register configuration, reduce operand.
Table 4
It is obtained in acs unit
ByIt calculates, selection
Export soft valueAccording in sequence deposit soft bit (bit) register of input sample, need here
It should be noted that deposit sequence must be corresponding with register position is sentenced firmly, whereinRespectively represent k, k-
1, the soft value at k-2, k-3 moment;
4, result output backtracking soft value outputs are sentenced according to hard.
Here, the process of backtracking sentences starting backtracking when register meets length of window, if W as tradition backtracking firmly0It is small
In W1, then from sel0Start to recall, if W0Greater than W1, then from sel1Start to recall.Pass throughOrState back and forth
It traces back previous moment, and so on.Here backtracking is one bit of primary backtracking, requires to judge lower W every time0、W1, so that learning is
Recall since sel0 or sel1 recall.
Soft bit is exported according to result is sentenced firmly, specifically, exporting a fixed value, the value is by posting if sentencing result firmly is 1
Storage is configurable;If sentencing result firmly is 0, corresponding value in current soft bit register is exported.
Strong filtering cancellation technology scheme provided in an embodiment of the present invention can guarantee while offsetting route high-frequency noises
Transmit the quality of signal.The parallel viterbi balanced device of N is proposed in the embodiment of the present invention, realizes that cost is optimal.Meet 100G and
Small using the parallel viterbi balanced device area of N under the scene of the high-throughputs such as 400G, low in energy consumption, hardware realization is simple.Table 5 is N
Value and cost relation table, ginseng is shown in Table 5, and works as N=1, and when same throughput, storage unit tricks is equal to data parallel degree, this
When area it is larger, power consumption is larger, and timing cost is higher than system operating frequency by 30%, belongs to Planar Mechanisms degree;As N=2, in phase
With under handling capacity, half is reduced when memory cell area is compared with N=1, so that area reduces half, power consumption half, timing cost ratio
System operating frequency is high by 10%, belongs to Planar Mechanisms degree;As N > 4, under same throughput, the speed of memory cell area reduction
Degree is far smaller than the increased speed of computing unit logical complexity, so that area increases instead, power consumption increases, and timing cost is than system
Working frequency of uniting is low, and timing breaks rules;Just reach an equalization point as N=4, so that under same throughput, storage unit
Area occupies moderate with computing unit logical complexity, so that area is optimal, power consumption optimum, timing cost is optimal;In summary
Such as the following table 5.
N (degree of parallelism) |
Area (ten thousand) |
Power consumption (watt) |
Timing (megahertz) |
1 |
About 500 |
About 1.5W |
About 600M |
2 |
About 220 |
About 0.7W |
About 550M |
4 |
About 130 |
About 0.5W |
About 500M |
>4 |
>550 |
>1.7W |
<300M |
Table 5
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the present invention
Formula.Moreover, the present invention, which can be used, can use storage in the computer that one or more wherein includes computer usable program code
The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.