CN106329487B - High pressure negative electricity voltage protection circuit and method - Google Patents
High pressure negative electricity voltage protection circuit and method Download PDFInfo
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- CN106329487B CN106329487B CN201510373856.8A CN201510373856A CN106329487B CN 106329487 B CN106329487 B CN 106329487B CN 201510373856 A CN201510373856 A CN 201510373856A CN 106329487 B CN106329487 B CN 106329487B
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Abstract
The present invention provides high pressure negative electricity voltage protection circuit and method, comprising: grid end connects the first PMOS tube of input signal, source connection positive voltage；One end connects the first PMOS tube, and the other end connects the current source of negative voltage；Grid end connects the second PMOS tube of the first PMOS tube, source connection positive voltage；One end connects the negative voltage pull-down module that the second PMOS tube, other end connection negative voltage, control terminal are connected to the drain terminal of the first PMOS tube by current limliting module；One end connects the clamper module of the negative control terminal of voltage pull-down module, the other end connection negative voltage.Output end voltage is pulled to positive voltage when charging, and when carrying out charging shutdown protection, output end voltage is pulled low to negative voltage, realizes that high pressure negative voltage is protected with this.The present invention uses general P-sub technique, above cost and versatility advantageously；Big resistance is substituted using the 5V low pressure NMOS of isolated form, realizes the output pull down resistor of 5K Ω or so, while saving chip area；It can also be achieved the function of 0V battery charging.
Description
Technical field
The present invention relates to field of power management, more particularly to a kind of high pressure negative electricity voltage protection circuit and method.
Background technique
High pressure negative electricity voltage protection circuit is applied in many circuits for realizing the protection of high pressure negative voltage, to be applied to
Be as shown in Figure 1 the protection circuit of lithium ion battery in the prior art for lithium ionic battery protection circuit, comprising: lithium from
Sub- battery, anode charger+, the negative voltage side of the positive voltage terminal connection charger of the lithium ion battery pass through electric discharge metal-oxide-semiconductor
The negative terminal charger- of charger is connected to after MD and charging metal-oxide-semiconductor MC；Li-ion Battery Protective Chip, the lithium ion battery
The end VCC of protection chip is connected to the high-voltage end of the lithium ion battery by resistance R1, the end VSS is connected to the lithium-ion electric
The low-pressure end in pond, is also connected with capacitor C between the end VCC and the end VSS, the negative pressure end V- of the Li-ion Battery Protective Chip passes through
Resistance R2 is connected to the negative terminal charger- of charger, and the Li-ion Battery Protective Chip output control signal OD is for controlling
The electric discharge metal-oxide-semiconductor MD executes discharge operation, and the Li-ion Battery Protective Chip output control signal OC is described for controlling
The metal-oxide-semiconductor MC that charges executes charging operations.The operating voltage range of the lithium ion battery both end voltage is 0V~5V, the charging
Operating voltage between the anode Charger+ of device and the negative terminal Charger- of the charger is 0V~35V, therefore described is filled
The negative terminal Charger- (voltage of the negative pressure end V- of the Li-ion Battery Protective Chip) of electric appliance is relative to the lithium-ion electric
The low-pressure end (the ground VSS of the i.e. described Li-ion Battery Protective Chip) in pond is -30V~0V negative voltage.When the control signal
When the voltage of OC is VCC, MC is opened, and charger can normally charge to lithium battery；It is described when OC voltage is V- voltage
The metal-oxide-semiconductor MC that charges is turned off, and the charging that the charger cannot carry out the lithium battery is in charge protection state.Therefore, it needs
High pressure negative electricity voltage protection circuit is used, the control signal OC is when shutdown controls the charging metal-oxide-semiconductor MC, the control letter
The voltage of number OC is equal to the voltage of the negative pressure end V- of the Li-ion Battery Protective Chip, and voltage range is -30V~0V.
There are two types of existing high pressure negative voltage protection schemes:
Scheme one: high pressure negative electricity voltage protection circuit is realized using N-sub technique, as shown in Fig. 2, including being series at power supply
PMOS tube and NMOS tube between voltage VCC and negative pressure V-, the PMOS tube are connected as input with the grid end of the NMOS tube
IN is held, the PMOS tube is connected as output end OC with the drain terminal of the NMOS tube.When the voltage of input terminal IN is logic low,
The voltage of output end OC be it is logically high, output end OC output voltage be supply voltage VCC, will control charging metal-oxide-semiconductor MC open；When
When the voltage of input terminal IN is logically high, the voltage of output end OC is logic low, and output end OC output voltage is negative pressure V-, will be controlled
System charging metal-oxide-semiconductor MC shutdown.The shortcomings that this circuit, needs to use the high pressure thickness grid oxygen of high pressure thickness grid oxygen PMOSFET and isolated form
NMOSFET.The PMOS tube is the high pressure thickness grid oxygen PMOS being prepared on N-sub, and the NMOS tube is to be prepared in P-well
Isolated form high pressure thickness grid oxygen NMOS, and N-sub is not common processes, generally requires development technology again, and cost price is higher.
Scheme two: high pressure negative electricity voltage protection circuit is realized in P-sub technique using big resistance, as shown in figure 3, including
The grid end of the PMOS tube being series between supply voltage VCC and negative pressure V- and big resistance R, the PMOS tube connect input terminal IN,
Drain terminal is connected to the big resistance R and as output end OC.When the voltage of input terminal IN is logic low, the voltage of output end OC
To be logically high, output end OC output voltage is supply voltage VCC, and control charging metal-oxide-semiconductor MC is opened；When the voltage of input terminal IN
When being logically high, the voltage of output end OC is logic low, and output end OC output voltage is negative pressure V-, by control charging metal-oxide-semiconductor MC
Shutdown.In order to maintain small chip quiescent current (such as typical 3uA quiescent current), the big resistance R needs to be greater than 10Meg
Ω consumes biggish chip area；And the big resistance R is the pull-down as output end OC, and generally for output
The pull down resistor resistance value that end OC more optimizes is 5K Ω or so, and the resistance value greater than 10Meg Ω can weaken the drop-down of output OC significantly
Ability.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of high pressure negative electricity voltage protection circuits
And method, for solve prior art mesohigh negative voltage protection circuit technology is complicated, chip occupying area is big, it is at high cost, under
The problems such as drawing ability is weak.
In order to achieve the above objects and other related objects, the present invention provides a kind of high pressure negative electricity voltage protection circuit, the height
Pressure negative electricity voltage protection circuit includes at least:
First PMOS tube, current source, the second PMOS tube, negative voltage pull-down module, current limliting module and clamper module；
Wherein, the source of first PMOS tube connects positive voltage, and drain terminal connects the current source, grid end connection input letter
Number；
One end of the current source connects first PMOS tube, and the other end connects negative voltage；
The source of second PMOS tube connects the positive voltage, and drain terminal connects the negative voltage pull-down module, and grid end connects
Connect first PMOS tube drain terminal and the current limliting module；
One end of the negative voltage pull-down module connects the drain terminal of second PMOS tube as output end, other end connection
The negative voltage, control terminal are connected to the drain terminal of first PMOS tube, drawing-die under the negative voltage by the current limliting module
Block is used to pull down the voltage of the output end；
One end of the clamper module connects the control terminal of the negative voltage pull-down module, and the other end connects the negative electricity
Pressure, for limiting the control terminal voltage of the negative voltage pull-down module.
Preferably, first PMOS tube and second PMOS tube are high voltage PMOS FET.
Preferably, the current source is resistance or high voltage depletion mode MOSFET.
Preferably, the negative voltage pull-down module includes multiple concatenated NMOS.
It is highly preferred that the NMOS is isolated form low pressure NMOSFET.
Preferably, the current limliting module is resistance or high voltage depletion mode MOSFET.
Preferably, further include be connected to it is back-to-back between the output end and the negative voltage pull-down module control terminal
Diode.
Preferably, the clamper module is low pressure MOSFET, and clamp voltage is not more than 5V.
Preferably, the positive voltage is 0V~5.5V relative to the working range on reference ground, and the negative voltage is relative to ginseng
The working range for examining ground is -30V~0V.
In order to achieve the above objects and other related objects, the present invention provides a kind of high pressure negative voltage guard method, in use
High pressure negative electricity voltage protection circuit is stated, the high pressure negative voltage guard method includes at least:
Input signal turns off the first PMOS tube, and the drain terminal voltage of first PMOS tube is dragged down by current source, makes second
PMOS tube conducting, negative voltage pull-down module shutdown, output end voltage is pulled to positive voltage by second PMOS tube, described
Positive voltage drives external circuit to work normally；
Input signal opens first PMOS tube, and the drain terminal voltage of first PMOS tube is raised, and makes described the
The shutdown of two PMOS tube, negative voltage pull-down module conducting, the output end voltage are pulled down to by the negative voltage pull-down module
Negative voltage, the negative voltage driving external circuit realize negative voltage shutdown and protection.
Preferably, further include 0V battery charging function: when the positive voltage drops are to 0V, the first PMOS tube shutdown,
The drain terminal voltage of first PMOS tube is connected by the current source pull-down to the negative voltage, second PMOS tube, is described
The shutdown of negative voltage pull-down module, the output end voltage are pulled to positive voltage, the positive voltage driving by second PMOS tube
The charging to 0V voltage is realized in metal-oxide-semiconductor conducting of charging.
Preferably, the output end voltage can be obtained to institute by adjusting the device size in the negative voltage pull-down module
State equivalent pull down resistor required for negative voltage.
As described above, high pressure negative electricity voltage protection circuit of the invention and method, have the advantages that
1, high pressure negative electricity voltage protection circuit of the invention and method use general P-sub technique to realize circuit, no
With developing new technique, in cost and above versatility advantageously.
2, high pressure negative electricity voltage protection circuit of the invention and method use the 5V low pressure NMOSFET of isolated form instead of big electricity
Resistance, realizes the output pull down resistor of 5K Ω or so, while saving chip area.
3, the high pressure negative electricity voltage protection circuit and method invented also achieve the function of 0V battery charging.
Detailed description of the invention
Fig. 1 is shown as the protection circuit schematic diagram of lithium ion battery in the prior art.
Fig. 2 is shown as the high pressure negative voltage in the prior art realized using N-sub technique and protects electrical block diagram.
Fig. 3 is shown as the high pressure negative electricity voltage protection circuit in the prior art realized in P-sub technique using big resistance
Structural schematic diagram.
Fig. 4 is shown as high pressure negative voltage protection electrical block diagram of the invention.
Component label instructions
1 high pressure negative electricity voltage protection circuit
11 current sources
12 negative voltage pull-down modules
13 current limliting modules
14 clamper modules
15 phase inverters
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 4.It should be noted that illustrating what only the invention is illustrated in a schematic way provided in the present embodiment
Basic conception, only shown in schema then with related component in the present invention rather than component count, shape when according to actual implementation
And size is drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout
Kenel may also be increasingly complex.
As shown in figure 4, the present invention provides a kind of high pressure negative electricity voltage protection circuit 1, the high pressure negative electricity voltage protection circuit 1 to
Include: less
First PMOS tube P1, current source 11, the second PMOS tube P2, negative voltage pull-down module 12, current limliting module 13 and clamper
Module 14.
As shown in figure 4, the source of the first PMOS tube P1 connects positive voltage VCC, drain terminal connects the current source 11, grid
End connection input signal IN.
Specifically, the first PMOS tube P1 is high voltage PMOS FET, and grid end is connected to the input by phase inverter 15
Signal IN, when the input signal IN be logic low when described in the first PMOS tube P1 cut-off, when the input signal IN be logic
The conducting of first PMOS tube P1 described in when high.Wherein, the power supply of the phase inverter 15 connects the positive voltage VCC, and ground connects with reference to ground
GND.The logically high and logic low of the input signal IN can pass through increase to the different conditions control of the first PMOS tube P1
Phase inverter implements, and is not limited to this embodiment.The positive voltage VCC relative to reference GND working range be 0V
~5.5V.
As shown in figure 4, one end of the current source 11 connects the first PMOS tube P1, the other end connects negative voltage V-.
Specifically, the current source 11 can be resistance, high voltage depletion mode MOSFET or other any achievable drop-down function
Can device, in the present embodiment, the preferred MOSFET of high voltage depletion mode is realized.The negative voltage relative to reference GND
Working range be -30V~0V.
As shown in figure 4, the source of the second PMOS tube P2 connects the positive voltage VCC, drain terminal connects the negative voltage
Pull-down module 12, grid end A connect the drain terminal of the first PMOS tube P1.
Specifically, the second PMOS tube P2 is high voltage PMOS FET.
As shown in figure 4, one end of the negative voltage pull-down module 12 connects the drain terminal of the second PMOS tube P2 as defeated
The other end of outlet OC, the negative voltage pull-down module 12 connect the negative voltage V-, the control of the negative voltage pull-down module 12
End B processed is connected to the drain terminal of the first PMOS tube P1 by the current limliting module 13.
Specifically, the negative voltage pull-down module 12 includes multiple concatenated NMOS, and the NMOS is isolated form low pressure
NMOSFET.In the present embodiment, the negative voltage pull-down module 12 includes 3 concatenated NMOS, the source of the first NMOS tube N1
Connect the negative voltage V-, drain terminal connects the source of the second NMOS tube N2, the drain terminal connection third of the second NMOS tube N2
The source of NMOS tube N3, the drain terminal of the third NMOS tube N3 connect the drain terminal of the second PMOS tube P2 and as the outputs
Hold OC；The grid end of the first NMOS tube N1, the second NMOS tube N2 and the third NMOS tube N3 link together work
For the control terminal B of the negative voltage pull-down module 12；The first NMOS tube N1, the second NMOS tube N2 and the third
The substrate and source of NMOS tube N3 is shorted (not shown) respectively.Assuming that the first NMOS tube N1, second NMOS tube
The N2 and third NMOS tube N3 is 5V low pressure NMOS, breakdown voltage 10V, then the first NMOS tube N1, described the
The series connection of the two NMOS tube N2 and third NMOS tube N3 can be the pressure resistance for realizing 30V.In a particular application, change can be passed through
The quantity of concatenated NMOS tube realizes different pressure voltages, and the quantity of concatenated NMOS tube is more, and pressure voltage is higher, not with this
Embodiment is limited.Parasitism has respectively by the first NMOS tube N1, the second NMOS tube N2 and the third NMOS tube N3
One parasitic diode D1, the second parasitic diode D2 and third parasitic diode D3.
Specifically, the current limliting module 13 can be resistance, high voltage depletion mode MOSFET or other any achievable current limlitings
The device of function, in the present embodiment, the preferred MOSFET of high voltage depletion mode is realized.The current limliting module 13 is described to flowing into
The electric current of 12 control terminal B of the grid end A of second PMOS tube P2 and the negative voltage pull-down module is limited, to avoid excessive grid
Injury of the voltage to device.
As shown in figure 4, one end of the clamper module 14 connects the control terminal B of the negative voltage pull-down module 12, it is another
End connects the negative voltage V-.
Specifically, the clamper module 14 can be realized with low pressure MOSFET or the MOSFET of diode connection type, pincers
Position voltage is not more than 5V, to ensure that the NMOS tube in the negative voltage pull-down module 12 works normally.
As shown in figure 4, the high pressure negative electricity voltage protection circuit 1 further includes being connected to the output end OC and the negative voltage
Back-to-back diode between pull-down module control terminal B.
Specifically, the cathode of the 4th diode D4 connects the control terminal B of the negative voltage pull-down module 12, anode connection the
The cathode of the anode of five diode D5, the 5th diode D5 connects the output end OC, for limiting the first NMOS
The drain-to-gate voltage of pipe N1, the second NMOS tube N2 and the third NMOS tube N3 protect the first NMOS tube N1, described
Grid oxygen between the grid and leakage of second NMOS tube N2 and the third NMOS tube N3.Its implementation is including but not limited to adopting
It is realized with the MOSFET of parasitic diode.
The working principle of above-mentioned high pressure negative electricity voltage protection circuit 1 is as follows:
Input signal turns off the first PMOS tube, and the drain terminal voltage of first PMOS tube is dragged down by current source, makes second
PMOS tube conducting, negative voltage pull-down module shutdown, output end voltage is pulled to positive voltage by second PMOS tube, described
Positive voltage drives external circuit to work normally.
In the present embodiment, by taking the high pressure negative electricity voltage protection circuit 1 is applied to Li-ion Battery Protective Chip as an example, tool
It is suitable for the field of any required high pressure negative voltage protection in body application.
In the present embodiment, the logic low of the input signal IN controls the high pressure negative electricity voltage protection circuit 1 and realizes electricity
Pond charge function；The logically high control of the input signal IN high pressure negative electricity voltage protection circuit 1 realizes battery charging shutdown
Protection.In actual use, influence of the logic height of input signal IN to battery status can be changed by increasing phase inverter, no
It is limited with the present embodiment.
Specifically, as shown in figure 4, becoming patrolling after the phase inverter 15 when the input signal IN is logic low
Height is collected, the first PMOS tube P1 is turned off, the grid end A of the second PMOS tube P2 and the control of the negative voltage pull-down module 12
Voltage at end B processed is dragged down by the current source 11, and the second PMOS tube P2 is opened, and the first NMOS tube N1, described
Second NMOS tube N2 and third NMOS tube N3 shutdown, the output end voltage OC are essentially pulled up to the positive voltage VCC, lithium
The charging metal-oxide-semiconductor MC of battery protection system is opened, and realizes normal battery charging function.
Input signal opens first PMOS tube, and the drain terminal voltage of first PMOS tube is raised, and makes described the
The shutdown of two PMOS tube, negative voltage pull-down module conducting, the output end voltage are pulled down to by the negative voltage pull-down module
Negative voltage, the negative voltage driving external circuit realize negative voltage protection.
Specifically, as shown in figure 4, becoming logic low after the phase inverter 15 when input signal IN is logically high,
Open the first PMOS tube P1, the grid end A of the second PMOS tube P2 and the control terminal B of the negative voltage pull-down module 12
The voltage at place is drawn high by the first PMOS tube P1, the second PMOS tube P2 shutdown, and the first NMOS tube N1, described the
The two NMOS tube N2 and third NMOS tube N3 are opened, and the output end voltage OC pulled down to the negative voltage V-, lithium electricity
The charging metal-oxide-semiconductor MC shutdown of system is protected in pond, realizes battery charging shutdown protection.
When the positive voltage drops are to 0V, the first PMOS tube shutdown, the drain terminal voltage of first PMOS tube is by institute
Current source pull-down is stated to the negative voltage, the second PMOS tube conducting, negative voltage pull-down module shutdown, the output end
Voltage is pulled to positive voltage by second PMOS tube, and the positive voltage driving charging metal-oxide-semiconductor conducting, which is realized, fills 0V voltage
Electricity.
Specifically, as shown in figure 4, when the voltage between the positive voltage VCC to reference ground GND is 0V, described first
Voltage quilt at PMOS tube P1 shutdown, the grid end A of the second PMOS tube P2 and the control terminal B of the negative voltage pull-down module 12
The current source 11 drags down, and the second PMOS tube P2 is opened, and the first NMOS tube N1, the second NMOS tube N2 and
The third NMOS tube N3 shutdown, the output end voltage OC are essentially pulled up to the positive voltage VCC, and li-ion cell protection system is filled
Electric metal-oxide-semiconductor MC is opened, and realizes that charger charges to 0V battery.
Also the output end voltage can be obtained by the device size in the adjusting negative voltage pull-down module to bear to described
Equivalent pull down resistor required for voltage, in the present embodiment, the value of the equivalent pull down resistor are set as 5K Ω.
High pressure negative electricity voltage protection circuit of the invention and method, have the advantages that
High pressure negative electricity voltage protection circuit of the invention and method use general P-sub technique to realize circuit, do not have to
Develop new technique, in cost and above versatility advantageously.
High pressure negative electricity voltage protection circuit of the invention and method use the 5V low pressure NMOSFET of isolated form instead of big electricity
Resistance, realizes the output pull down resistor of 5K Ω or so, while saving chip area.
The high pressure negative electricity voltage protection circuit and method of invention also achieve the function of 0V battery charging.
In conclusion the present invention provides a kind of high pressure negative electricity voltage protection circuit and method, the high pressure negative voltage protection electricity
Road includes at least: grid end connects the first PMOS tube of input signal, source connection positive voltage；One end connects the first PMOS tube, separately
The current source of one end connection negative voltage；Grid end connects the second PMOS tube of the first PMOS tube drain terminal, source connection positive voltage；One end
The drain terminal, other end connection negative voltage, control terminal for connecting the second PMOS tube are connected to the leakage of the first PMOS tube by current limliting module
The negative voltage pull-down module at end；One end connects the clamper module of the control terminal of negative voltage pull-down module, other end connection negative voltage.
Output end voltage is drawn high to positive voltage when charging, and when carrying out charging shutdown protection, output end voltage is pulled low to negative electricity
Pressure realizes that high pressure negative voltage is protected with this.High pressure negative electricity voltage protection circuit of the invention and method use general P-sub work
Skill realizes circuit, without developing new technique, in cost and above versatility advantageously；Using the 5V low pressure of isolated form
NMOSFET realizes the output pull down resistor of 5K Ω or so instead of big resistance, while saving chip area；It can also be achieved
The function of 0V battery charging.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of high pressure negative electricity voltage protection circuit, which is characterized in that the high pressure negative electricity voltage protection circuit includes at least:
First PMOS tube, current source, the second PMOS tube, negative voltage pull-down module, current limliting module and clamper module；
Wherein, the source of first PMOS tube connects positive voltage, and drain terminal connects the current source, and grid end connects input signal；
One end of the current source connects first PMOS tube, and the other end connects negative voltage；
The source of second PMOS tube connects the positive voltage, and drain terminal connects the negative voltage pull-down module, and grid end connects institute
State the first PMOS tube drain terminal and the current limliting module；
One end of the negative voltage pull-down module connects the drain terminal of second PMOS tube as output end, described in other end connection
Negative voltage, control terminal are connected to the drain terminal of first PMOS tube by the current limliting module, and the negative voltage pull-down module is used
In the voltage for pulling down the output end；
One end of the clamper module connects the control terminal of the negative voltage pull-down module, and the other end connects the negative voltage, uses
In the control terminal voltage for limiting the negative voltage pull-down module.
2. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: first PMOS tube and described
Two PMOS tube are high voltage PMOS FET.
3. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: the current source is resistance or high pressure
Depletion type MOS FET.
4. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: the negative voltage pull-down module includes
Multiple concatenated NMOS.
5. high pressure negative electricity voltage protection circuit according to claim 4, it is characterised in that: the NMOS is isolated form low pressure
NMOSFET。
6. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: the current limliting module is resistance or height
Press depletion type MOS FET.
7. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: further include being connected to the output end
And the back-to-back diode between the negative voltage pull-down module control terminal.
8. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: the clamper module is low pressure
MOSFET, clamp voltage are not more than 5V.
9. high pressure negative electricity voltage protection circuit according to claim 1, it is characterised in that: the positive voltage is relative to reference
Working range be 0V~5.5V, the negative voltage relative to reference ground working range be -30V~0V.
10. a kind of high pressure negative voltage guard method is protected using high pressure negative voltage as claimed in any one of claims 1 to 9 wherein
Circuit, which is characterized in that the high pressure negative voltage guard method includes:
Input signal turns off the first PMOS tube, and the drain terminal voltage of first PMOS tube is dragged down by current source, makes the 2nd PMOS
Pipe conducting, negative voltage pull-down module shutdown, output end voltage are pulled to positive voltage, the positive electricity by second PMOS tube
Pressure driving external circuit works normally；
Input signal opens first PMOS tube, and the drain terminal voltage of first PMOS tube is raised, and makes described second
PMOS tube shutdown, negative voltage pull-down module conducting, the output end voltage is pulled down to negative by the negative voltage pull-down module
Voltage, the negative voltage driving external circuit realize negative voltage shutdown and protection.
11. high pressure negative voltage guard method according to claim 10, it is characterised in that:
Further include 0V battery charging function: when the positive voltage drops are to 0V, the first PMOS tube shutdown, the first PMOS
The drain terminal voltage of pipe is by the current source pull-down to the negative voltage, drawing-die under the second PMOS tube conducting, the negative voltage
Block shutdown, the output end voltage are pulled to positive voltage, the positive voltage driving charging metal-oxide-semiconductor conducting by second PMOS tube
Realize the charging to 0V voltage.
12. high pressure negative voltage guard method according to claim 10, it is characterised in that: can be by adjusting the negative voltage
Device size in pull-down module obtains equivalent pull down resistor required for the output end voltage to the negative voltage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107302215A (en) * | 2017-07-12 | 2017-10-27 | 长沙方星腾电子科技有限公司 | A kind of multisection lithium battery protects chip circuit |
| CN107727923A (en) * | 2017-08-29 | 2018-02-23 | 宁德时代新能源科技股份有限公司 | High-voltage sampling circuit and battery management system |
| CN108695568B (en) * | 2018-05-18 | 2024-05-03 | 深圳市拓邦锂电池有限公司 | Battery monitoring management system |
| CN111654085B (en) * | 2020-06-17 | 2022-09-02 | 上海艾为电子技术股份有限公司 | Charging circuit and electronic equipment |
| CN113258641B (en) * | 2021-05-26 | 2021-10-22 | 江苏长晶科技有限公司 | Battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor |
| CN114914992B (en) * | 2022-06-14 | 2023-09-19 | 无锡力芯微电子股份有限公司 | Dead battery pull-down module of high pressure resistant |
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| CN103746347A (en) * | 2014-01-28 | 2014-04-23 | 无锡中星微电子有限公司 | Battery protection chip and battery system |
| CN104779589A (en) * | 2015-03-31 | 2015-07-15 | 无锡中星微电子有限公司 | Battery protection circuit and system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8148946B2 (en) * | 2008-10-10 | 2012-04-03 | Mitsumi Electric Co., Ltd. | Battery pack having protection circuit for secondary battery |
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2015
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959436A (en) * | 1997-02-04 | 1999-09-28 | Seiko Instruments Inc. | Charge and discharge control circuit having low voltage detecting means for preventing charging of an abnormal cell |
| CN101356706A (en) * | 2006-09-19 | 2009-01-28 | 株式会社理光 | Back-gate voltage generator circuit, four-terminal back gate switching FET, and charge and discharge protection circuit using same |
| CN103746347A (en) * | 2014-01-28 | 2014-04-23 | 无锡中星微电子有限公司 | Battery protection chip and battery system |
| CN104779589A (en) * | 2015-03-31 | 2015-07-15 | 无锡中星微电子有限公司 | Battery protection circuit and system |
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| CN106329487A (en) | 2017-01-11 |
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