CN106298644A - The preparation method of semiconductor device - Google Patents
The preparation method of semiconductor device Download PDFInfo
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- CN106298644A CN106298644A CN201610896067.7A CN201610896067A CN106298644A CN 106298644 A CN106298644 A CN 106298644A CN 201610896067 A CN201610896067 A CN 201610896067A CN 106298644 A CN106298644 A CN 106298644A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 238000005530 etching Methods 0.000 claims abstract description 75
- 239000002184 metal Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000010410 layer Substances 0.000 claims description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000006978 adaptation Effects 0.000 abstract description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 210000001557 animal structure Anatomy 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Micromachines (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Present invention is disclosed the preparation method of a kind of semiconductor device, in the step etching the side that described first wafer substrate deviates from described first wafer dielectric layer, remove described first wafer substrate of part, form the first opening, owing to the etching selection ratio of described first wafer substrate with described etches sacrificial structure is less than the etching selection ratio of described first wafer substrate and described first wafer dielectric layer, the described etches sacrificial structure exposed by described first opening may proceed to be etched away, the second opening is formed in the bottom of described first opening, described second opening exposes described lead-in wire metal structure.The etching selection being formed by controlling described etches sacrificial structure with described first wafer substrate of described second opening, self adaptation removes what described etches sacrificial structure was formed, it is not necessary to prepare extra mask pattern, such that it is able to reduce light shield, reduces preparation cost.
Description
Technical field
The present invention relates to technical field of semiconductor preparation, particularly relate to the preparation method of a kind of semiconductor device.
Background technology
Along with electronic equipment and memorizer develop towards miniaturization and slimming, volume and thickness to chip there has also been more
High requirement.The three-dimensionally integrated of wafer is a kind of scheme effectively reducing chip volume and thickness, this technology by two or
The chip that multiple functions are identical or different is integrated by bonding, and this being integrated in keeps raising while chip volume
The performance of chip；Shorten the metal interconnection between functional chip so that heating, power consumption, delay are greatly reduced simultaneously；Greatly
Amplitude improves the bandwidth between functional module, improves the performance of chip while keeping prior art node.
But, the way that in prior art, wafer is three-dimensionally integrated is complicated, and processing step is various, and at least needs three layers of light
Cover, preparation cost is high.
Summary of the invention
It is an object of the invention to, it is provided that the preparation method of a kind of semiconductor device, preparation cost can be reduced.
For solving above-mentioned technical problem, the present invention provides the preparation method of a kind of semiconductor device, including:
The first wafer substrate and the first wafer dielectric layer, institute that one first wafer, described first wafer include stacking are provided
Stating and be provided with lead-in wire metal structure and etches sacrificial structure in the first wafer dielectric layer, described etches sacrificial structure is positioned at described
First wafer dielectric layer exists towards the surface of described first wafer substrate side, described lead-in wire metal structure and etches sacrificial structure
Upright projection in same level is the most least partially overlapped；
Etch described first wafer substrate and deviate from the side of described first wafer dielectric layer, described first wafer substrate and institute
State the etching selection ratio etching selection less than described first wafer substrate with described first wafer dielectric layer of etches sacrificial structure
Ratio, removes described first wafer substrate of part, forms the first opening, and removes the etching in the most described first wafer dielectric layer
Sacrificing structure, form the second opening in the bottom of described first opening, described second opening exposes described lead-in wire metal structure；
A metal level is deposited in described first opening and the second opening；And
Metal level described in selective etch, to form a metal gasket being electrically connected with described lead-in wire metal structure.
Further, in the preparation method of described semiconductor device, described first wafer substrate also includes etching stopping
Structure, described etch stop structure is positioned at described first wafer substrate surface towards described first wafer dielectric layer side, and
It is positioned at around described etches sacrificial structure.
Further, in the preparation method of described semiconductor device, described etches sacrificial structure and described first wafer
The etching selection ratio of substrate is less than the etching selection ratio of described etch stop structure with described first wafer substrate.
Further, in the preparation method of described semiconductor device, the material of described etch stop structure be oxide,
Nitride or carbide.
Further, in the preparation method of described semiconductor device, described etch stop structure is shallow groove isolation structure.
Further, in the preparation method of described semiconductor device, described lead-in wire metal level and etching sacrificial layer pass through
Described second wafer dielectric layer insulate mutually.
Further, in the preparation method of described semiconductor device, deviate from described etching described second wafer substrate
The step of the side of the second wafer dielectric layer includes:
The side deviating from described first wafer dielectric layer in described first wafer substrate forms the first mask pattern；
Perform etching with described first mask pattern for mask, described first wafer substrate and described etches sacrificial structure
Etching selection ratio, less than the etching selection ratio of described first wafer substrate and described first wafer dielectric layer, removes part described the
One wafer substrate, removes described first wafer substrate of part, forms the first opening, and remove in described first wafer dielectric layer
Etches sacrificial structure, forms the second opening in the bottom of described first opening；
For mask, described first wafer dielectric layer is performed etching with described first opening and the second opening, make described second
Opening exposes described lead-in wire metal structure.
Further, in the preparation method of described semiconductor device, the sidewall of described first opening is formed with protection side
Wall.
Further, in the preparation method of described semiconductor device, the preparation method of described semiconductor device also includes；
Deviate from before the side of described first wafer dielectric layer forms the first mask pattern in described first wafer substrate,
Described second wafer substrate deviates from the side of described second wafer dielectric layer and forms the first protective layer；
Perform etching with described first mask pattern for mask and with described first opening and the second opening for mask to institute
State between the step that the first wafer dielectric layer performs etching, formed at described first opening and the sidewall of the second opening and diapire
One second protective layer；
With described first opening and the second opening for mask described first wafer dielectric layer is performed etching time, at least remove
Second protective layer of described second opening diapire, and retain the second protective layer of the sidewall of described first opening, described to be formed
Protection side wall.
Further, in the preparation method of described semiconductor device, described first parameatal first wafer substrate
In be formed with insulation system.
Further, in the preparation method of described semiconductor device, the characteristic size of described second opening is less than described
The characteristic size of the first opening.
Further, in the preparation method of described semiconductor device, the material of described etching sacrificial layer be polysilicon or
Monocrystal silicon, described first wafer substrate is silicon substrate.
Further, in the preparation method of described semiconductor device, deviate from described etching described second wafer substrate
Before the step of the side of the second wafer dielectric layer, also include:
Described first wafer and one being supported substrate be bonded together, wherein, described second wafer dielectric layer is towards described
Support substrate is arranged.
Further, in the preparation method of described semiconductor device, described support substrate be substrate of glass, silicon base or
Second wafer.
Further, in the preparation method of described semiconductor device, described second wafer includes the second wafer of stacking
Substrate and the second wafer dielectric layer, described first wafer dielectric layer and described second wafer dielectric layer face each other setting.
Further, in the preparation method of described semiconductor device, deviate from described etching described first wafer substrate
Before the step of the side of the first wafer dielectric layer, also include:
The side that described first wafer substrate deviates from described first wafer dielectric layer carries out thinning.
Further, in the preparation method of described semiconductor device, the thickness of thinning rear described first wafer substrate is 2
μm～30 μm.
Further, in the preparation method of described semiconductor device, the step of metal level described in selective etch includes:
Once formation second mask pattern of described first wafer substrate is deviated from described metal level；
Carry out metal level etching for mask to described with described second mask pattern, form described metal gasket.
Compared with prior art, the preparation method of the semiconductor device that the present invention provides has the advantage that
In the preparation method of described semiconductor device, deviate from described first wafer Jie etching described first wafer substrate
In the step of the side of matter layer, remove described first wafer substrate of part, form the first opening, due to described first wafer substrate
With the etching selection ratio of described etches sacrificial structure less than described first wafer substrate and the etching of described first wafer dielectric layer
Selecting ratio, the described etches sacrificial structure exposed by described first opening may proceed to be etched away, at described first opening
Second opening is formed on bottom, and described second opening exposes described lead-in wire metal structure.Being formed by of described second opening
Controlling the etching selection of described etches sacrificial structure and described first wafer substrate, self adaptation removes described etches sacrificial structure shape
Become, it is not necessary to prepare extra mask pattern, such that it is able to reduce light shield, reduce preparation cost.
Accompanying drawing explanation
Fig. 1 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention；
Fig. 2 to Figure 10 be the semiconductor device of one embodiment of the invention preparation method in the schematic diagram of device architecture.
Detailed description of the invention
Below in conjunction with schematic diagram, the preparation method of the semiconductor device of the present invention is described in more detail, Qi Zhongbiao
Show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, it is widely known that description below is appreciated that for those skilled in the art, and
It is not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make to due to the fact that unnecessary details and chaotic.Will be understood that opening in any practical embodiments
In Faing, it is necessary to make a large amount of implementation detail to realize the specific objective of developer, such as according to relevant system or relevant business
Limit, an embodiment change into another embodiment.Additionally, it should think that this development is probably complexity and consuming
Time, but it is only routine work to those skilled in the art.
The core concept of the present invention is, it is provided that the preparation method of a kind of semiconductor device, as it is shown in figure 1, include as follows
Step:
Step S11, it is provided that one first wafer, described first wafer includes that the first wafer substrate of stacking and the first wafer are situated between
Matter layer, is provided with lead-in wire metal structure and etches sacrificial structure, described etches sacrificial structure in described first wafer dielectric layer
It is positioned at the described first wafer dielectric layer surface towards described first wafer substrate side, described lead-in wire metal structure and etching sacrificial
Domestic animal structure upright projection in same level is the most least partially overlapped；
Step S12, etches described first wafer substrate and deviates from the side of described first wafer dielectric layer, described first wafer
Substrate is less than described first wafer substrate and described first wafer dielectric layer with the etching selection ratio of described etches sacrificial structure
Etching selection ratio, removes described first wafer substrate of part, forms the first opening, and removes the most described first wafer dielectric layer
In etches sacrificial structure, form the second opening in the bottom of described first opening, described second opening exposes described lead-in wire
Metal structure；
Step S13, deposits a metal level in described first opening and the second opening；And
Step S14, metal level described in selective etch, with the gold forming and described lead-in wire metal structure is electrically connected with
Belong to liner.
In the step etching the side that described first wafer substrate deviates from described first wafer dielectric layer, remove part institute
State the first wafer substrate, form the first opening, due to the etching selection of described first wafer substrate Yu described etches sacrificial structure
Than the etching selection ratio less than described first wafer substrate Yu described first wafer dielectric layer, exposed by described first opening
Described etches sacrificial structure may proceed to be etched away, and forms the second opening, described second opening in the bottom of described first opening
Expose described lead-in wire metal structure.Being formed by of described second opening controls described etches sacrificial structure and described first
The etching selection of wafer substrate, self adaptation removes what described etches sacrificial structure was formed, it is not necessary to prepare extra mask pattern, from
And light shield can be reduced, reduce preparation cost.
Referring to the drawings the present invention the most more particularly described below in the following passage.Want according to following explanation and right
Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-
Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
Below in conjunction with Fig. 2 to Figure 10, illustrating the preparation method of the semiconductor device of the present invention, Fig. 2 to Figure 10 is this
The schematic diagram of device architecture in the preparation method of the semiconductor device inventing an embodiment.
In the preparation method of described semiconductor device, first, step S11 is carried out, as in figure 2 it is shown,
Step S11, it is provided that one first wafer 100, described first wafer 100 includes the first wafer substrate 110 He of stacking
First wafer dielectric layer 120, described first wafer substrate 110 is Semiconductor substrate, in the present embodiment, described first wafer lining
The end 110 is silicon substrate.Metal interconnecting wires is set in described first wafer dielectric layer 120, and, described first wafer dielectric layer 120
In be provided with the lead-in wire metal structure 121 for electrically drawing and etches sacrificial structure 122, described etches sacrificial structure 122
It is positioned at the described first wafer dielectric layer 120 surface towards described first wafer substrate 110 side, described lead-in wire metal structure
121 and the etches sacrificial structure 122 upright projection in same level the most least partially overlapped, the most described lead-in wire metal structure
121 is relative with etches sacrificial structure 122 position in vertical direction, general, the feature chi of described lead-in wire metal structure 121
Very little more than the characteristic size with etches sacrificial structure 122.
Wherein, described first wafer substrate 110 and the etching selection ratio of described etches sacrificial structure 122 are less than described first
Wafer substrate 110 and the etching selection ratio of described first wafer dielectric layer 120, general, described first wafer dielectric layer 120
Material is oxide, and in the present embodiment, described first wafer substrate 110 is silicon substrate, so, it is also preferred that the left described etching is sacrificial
The material of domestic animal layer 121 is polysilicon or monocrystal silicon, and described polysilicon or monocrystal silicon are close and described with the etch rate of silicon substrate
Polysilicon or monocrystal silicon are bigger with the etch rate difference of described first wafer dielectric layer 120.
It is also preferred that the left described lead-in wire metal level 121 is mutually exhausted by described second wafer dielectric layer 120 with etching sacrificial layer 122
Edge, the most described etching sacrificial layer 122 is positioned at described lead-in wire metal level 121, and to deviate from the side of described first wafer substrate 110 (described
Etching sacrificial layer 121 is positioned at the side in front), described lead-in wire metal level 121 and etching sacrificial layer 121 can be according to conventional systems
Standby technique is prepared, and such as, described etching sacrificial layer 121 can be prepared according to the technique preparing grid, described lead-in wire metal
Layer 122 can be prepared according to the technique preparing interconnection layer.
Preferably.In order to control the etching depth of the first opening, described first wafer substrate 110 also includes that etching stopping is tied
Structure 111, described etch stop structure 111 is positioned at described first wafer substrate 110 towards described first wafer dielectric layer 120 side
Surface, and be positioned at described etches sacrificial structure 122 around.Described etches sacrificial structure 122 and described first wafer substrate
The etching selection ratio of 110 is less than the etching selection ratio of described etch stop structure 111 with described first wafer substrate 110, to protect
Demonstrate,prove the etching depth of the first opening.Preferably, the material of described etch stop structure 111 is oxide, nitride or carbide,
Oxide, nitride or carbide are big with the etch rate difference of monocrystal silicon/polysilicon, and oxide, nitride or carbide
Big with the etch rate difference of silicon substrate, it is also preferred that the left described etch stop structure 111 is shallow groove isolation structure, often can use
The shallow grooved-isolation technique of rule prepares described etch stop structure 111.
Afterwards, described first wafer 100 is supported with one substrate and is bonded together with 200, wherein, described second wafer medium
Layer 120 is arranged towards described support substrate 200.It is also preferred that the left described support substrate 200 is substrate of glass, silicon base or the second crystalline substance
Circle.In the present embodiment, described support substrate 200 is the second wafer, as in figure 2 it is shown, described second wafer 200 includes stacking
Second wafer substrate 210 and the second wafer dielectric layer 220, described first wafer dielectric layer 120 and described second wafer dielectric layer
220 face each other setting.
Wherein, described second wafer dielectric layer 220 can also include interconnection structure, described first wafer 100 and second
Wafer 200 can realize circuit by hybrid bonded or silicon through hole TSV and interconnect, and this is for it will be appreciated by those skilled in the art that
, do not repeat at this.
Then, the side that described first wafer substrate 110 deviates from described first wafer dielectric layer 120 carries out thinning, subtracts
After thin, the thickness of described first wafer substrate 110 is 2 μm～30 μm, such as 5 μm, 10 μm, 15 μm, 20 μm, 25 μm.
In the present embodiment, in order to realize the insulation of follow-up metal level and described first wafer substrate 110, it is also preferred that the left
The first protective layer 310 is formed in the side that described first wafer substrate 110 is deviated from described first wafer dielectric layer 120.
Then, carry out step S12, etch described first wafer substrate 110 and deviate from the one of described first wafer dielectric layer 120
Side, it is also preferred that the left in the present embodiment, described step S12 includes:
Sub-step S121: as it is shown on figure 3, deviate from described first wafer dielectric layer 120 in described first wafer substrate 110
Side forms the first mask pattern 410, when preparing described first mask pattern 410, needs one layer of light shield；
Sub-step S122: as shown in Figure 4, performs etching with described first mask pattern 410 for mask, removes part described
First wafer substrate 110, forms the first opening 510；Due to described first wafer substrate 110 and described etches sacrificial structure 122
Etching selection ratio less than the etching selection ratio of described first wafer substrate 110 with described first wafer dielectric layer 120, i.e. at this
In etching process, etching reactant (such as etching gas) may proceed to as described in the first opening 510 expose as described in etches sacrificial
Structure 122 performs etching, as it is shown in figure 5, form the second opening 520, described second opening in the bottom of described first opening 510
The characteristic size of 520 is less than the characteristic size of described first opening 510.Described second opening 520 be formed by control institute
Stating the etching selection of etches sacrificial structure 122 and described first wafer substrate 110, self adaptation removes described etches sacrificial structure
122 formation, it is not necessary to prepare extra mask pattern, such that it is able to reduce light shield, reduce preparation cost.Further, in this process
In, described etch stop structure 111 can efficiently control the stopping of the bottom of described first opening 510 for shallow groove isolation structure
Position；
It is also preferred that the left between sub-step S122 and sub-step S123, as shown in Figure 6, at described first opening 510 and second
The sidewall of opening 520 and diapire form one second protective layer 320, and the material of described second protective layer 320 is insulant；
Sub-step S123: as it is shown in fig. 7, brilliant to described first for mask with described first opening 510 and the second opening 520
Circle dielectric layer 120 performs etching so that the degree of depth of described second opening 520 increases, and makes described second opening 520 expose described
Lead-in wire metal structure 121.In the process, described etch stop structure 111 can efficiently control institute for shallow groove isolation structure
State the stop position of the bottom of the first opening 510.Meanwhile, the second protective layer of described second opening 520 diapire is at least removed
320, and retain the second protective layer 320 of the sidewall of described first opening 510, to form described protection side wall 320；
Afterwards, carry out step S13, as shown in Figure 8, in described first opening 510 and the second opening 520, deposit a metal
Layer 600 ', wherein, described second protective layer 320 is possible to prevent metal to enter described first wafer substrate 110.
Subsequently, carrying out step S14, metal level 600 ' described in selective etch, to form one and described lead-in wire metal knot
The metal gasket that structure 121 is electrically connected with, concrete, step S14 includes:
Sub-step S141: as it is shown in figure 9, deviate from a shape of described first wafer substrate 110 at described metal level 600 '
Become the second mask pattern 420, when preparing described second mask pattern 420, need one layer of light shield；
Sub-step S142: as shown in Figure 10, carries out metal level 600 ' for mask to described with described second mask pattern 420
Etching, forms described metal gasket 600, and the electricity of described lead-in wire metal level 122 is drawn by described metal gasket 600.
Presently preferred embodiments of the present invention as it appears from the above, but the present invention is not limited to above-described embodiment, such as, however it is not limited to logical
Crossing described second protective layer 320 is possible to prevent metal to enter described first wafer substrate 110, in other embodiments, it is also possible to
The first wafer substrate 110 around described first opening 510 is formed insulation system, such as deep groove isolation structure, can also
Prevent metal from affecting the electrical property of device architecture in described first wafer substrate 110.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (18)
1. the preparation method of a semiconductor device, it is characterised in that including:
The first wafer substrate and the first wafer dielectric layer that one first wafer, described first wafer include stacking be provided, described
Being provided with lead-in wire metal structure and etches sacrificial structure in one wafer dielectric layer, described etches sacrificial structure is positioned at described first
Wafer dielectric layer is towards the surface of described first wafer substrate side, and described lead-in wire metal structure and etches sacrificial structure are same
Upright projection on horizontal plane is the most least partially overlapped；
Etch described first wafer substrate and deviate from the side of described first wafer dielectric layer, described first wafer substrate and described quarter
The etching selection ratio of erosion sacrifice structure, less than the etching selection ratio of described first wafer substrate with described first wafer dielectric layer, is gone
Except described first wafer substrate of part, form the first opening, and remove the etches sacrificial in the most described first wafer dielectric layer
Structure, forms the second opening in the bottom of described first opening, and described second opening exposes described lead-in wire metal structure；
A metal level is deposited in described first opening and the second opening；And
Metal level described in selective etch, to form a metal gasket being electrically connected with described lead-in wire metal structure.
2. the preparation method of semiconductor device as claimed in claim 1, it is characterised in that described first wafer substrate also includes
Etch stop structure, described etch stop structure is positioned at described first wafer substrate towards described first wafer dielectric layer side
Surface, and be positioned at around described etches sacrificial structure.
3. the preparation method of semiconductor device as claimed in claim 2, it is characterised in that described etches sacrificial structure is with described
The etching selection ratio of the first wafer substrate is less than the etching selection ratio of described etch stop structure with described first wafer substrate.
4. the preparation method of semiconductor device as claimed in claim 3, it is characterised in that the material of described etch stop structure
For oxide, nitride or carbide.
5. the preparation method of semiconductor device as claimed in claim 3, it is characterised in that described etch stop structure is shallow slot
Isolation structure.
6. the preparation method of the semiconductor device as described in any one in claim 1 to 5, it is characterised in that described lead-in wire
Metal level is insulated by described second wafer dielectric layer mutually with etching sacrificial layer.
7. the preparation method of semiconductor device as claimed in claim 6, it is characterised in that etching described second wafer substrate
The step of the side deviating from described second wafer dielectric layer includes:
The side deviating from described first wafer dielectric layer in described first wafer substrate forms the first mask pattern；
Perform etching with described first mask pattern for mask, described first wafer substrate and the etching of described etches sacrificial structure
Select the ratio etching selection ratio less than described first wafer substrate Yu described first wafer dielectric layer, remove part described first brilliant
Circle substrate, removes described first wafer substrate of part, forms the first opening, and remove the etching in described first wafer dielectric layer
Sacrifice structure, form the second opening in the bottom of described first opening；
For mask, described first wafer dielectric layer is performed etching with described first opening and the second opening, make described second opening
Expose described lead-in wire metal structure.
8. the preparation method of semiconductor device as claimed in claim 7, it is characterised in that the sidewall of described first opening is formed
Protected side wall.
9. the preparation method of semiconductor device as claimed in claim 8, it is characterised in that the preparation side of described semiconductor device
Method also includes:
Deviate from before the side of described first wafer dielectric layer forms the first mask pattern in described first wafer substrate, described
Second wafer substrate deviates from the side of described second wafer dielectric layer and forms the first protective layer；
Perform etching with described first mask pattern for mask and with described first opening and the second opening for mask to described
Between the step that one wafer dielectric layer performs etching, form one the at described first opening and the sidewall of the second opening and diapire
Two protective layers；
With described first opening and the second opening for mask described first wafer dielectric layer is performed etching time, at least remove described
Second protective layer of the second opening diapire, and retain the second protective layer of the sidewall of described first opening, to form described protection
Side wall.
10. the preparation method of semiconductor device as claimed in claim 7, it is characterised in that described first parameatal the
One wafer substrate is formed with insulation system.
The preparation method of semiconductor device as described in any one in 11. such as claim 1 to 5, it is characterised in that described second
The characteristic size of opening is less than the characteristic size of described first opening.
The preparation method of semiconductor device as described in any one in 12. such as claim 1 to 5, it is characterised in that described etching
The material of sacrifice layer is polysilicon or monocrystal silicon, and described first wafer substrate is silicon substrate.
The preparation method of semiconductor device as described in any one in 13. such as claim 1 to 5, it is characterised in that in etching institute
Before stating the step of the side that the second wafer substrate deviates from described second wafer dielectric layer, also include:
Described first wafer and one being supported substrate be bonded together, wherein, described second wafer dielectric layer is towards described support
Substrate is arranged.
The preparation method of 14. semiconductor device as claimed in claim 13, it is characterised in that described support substrate is glass base
The end, silicon base or the second wafer.
The preparation method of 15. semiconductor device as claimed in claim 13, it is characterised in that described second wafer includes stacking
The second wafer substrate and the second wafer dielectric layer, described first wafer dielectric layer and described second wafer dielectric layer face each other
Arrange.
The preparation method of semiconductor device as described in any one in 16. such as claim 1 to 5, it is characterised in that in etching institute
Before stating the step of the side that the first wafer substrate deviates from described first wafer dielectric layer, also include:
The side that described first wafer substrate deviates from described first wafer dielectric layer carries out thinning.
The preparation method of 17. semiconductor device as claimed in claim 16, it is characterised in that described first wafer lining after thinning
The thickness at the end is 2 μm～30 μm.
The preparation method of semiconductor device as described in any one in 18. such as claim 1 to 5, it is characterised in that selectivity is carved
The step losing described metal level includes:
Once formation second mask pattern of described first wafer substrate is deviated from described metal level；
Carry out metal level etching for mask to described with described second mask pattern, form described metal gasket.
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |