CN106252419A - Thin film transistor (TFT) and manufacture method, array base palte and display device - Google Patents
Thin film transistor (TFT) and manufacture method, array base palte and display device Download PDFInfo
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- CN106252419A CN106252419A CN201610849607.6A CN201610849607A CN106252419A CN 106252419 A CN106252419 A CN 106252419A CN 201610849607 A CN201610849607 A CN 201610849607A CN 106252419 A CN106252419 A CN 106252419A
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- fixed charge
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- 239000010409 thin film Substances 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 239000000463 material Substances 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 17
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims description 6
- 240000002853 Nelumbo nucifera Species 0.000 claims description 6
- 235000006510 Nelumbo pentapetala Nutrition 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical group [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910000510 noble metal Inorganic materials 0.000 abstract description 11
- 238000002161 passivation Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 19
- 238000000059 patterning Methods 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 239000007769 metal material Substances 0.000 description 14
- 238000001259 photo etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000010408 film Substances 0.000 description 11
- 230000008859 change Effects 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of thin film transistor (TFT) and manufacture method, array base palte and display device, belong to Display Technique field.Described thin film transistor (TFT) includes: underlay substrate；Underlay substrate is formed fixed charge structure；Being formed with active layer, source electrode, drain and gate on the underlay substrate being formed with fixed charge structure, active layer is connected with source electrode and drain electrode respectively；Wherein, electric charge in fixed charge structure is fixed charge, fixed charge structure includes: the first fixed charge block and the second fixed charge block, source electrode orthographic projection on the first fixed charge block is positioned at the first fixed charge block region, drain electrode orthographic projection on the second fixed charge block is positioned at the second fixed charge block region, and fixed charge structure contacts with active layer.The present invention, without using the noble metal of high work function as source, drain electrode, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
Description
Technical field
The present invention relates to Display Technique field, particularly to a kind of thin film transistor (TFT) and manufacture method thereof, array base palte and
Display device.
Background technology
Along with the development in Display Technique field, carbon nano-tube material is due to the electric property of its excellence, through frequently as active
The material of layer, is applied to film transistor device.In order to ensure proper device operation, need the source of film transistor device, leakage
Formed between pole and active layer and have between the source of good Ohmic contact, i.e. thin film transistor (TFT), drain electrode and CNT active layer
There is low metal contact resistance.Therefore, how to form good Ohmic contact, the problem becoming people's extensive concern.
In prior art, generally using palladium (Pd), the noble metal of the high work function such as gold (Au) is as film transistor device
Source, drain electrode, form good Ohmic contact.
During realizing the present invention, inventor finds that prior art at least there is problems in that
In prior art, use the noble metal source as film transistor device of the high work functions such as Pd, Au, drain electrode, come
Forming good Ohmic contact, cost of manufacture is higher.
Summary of the invention
In order to solve to use the noble metal of high work function as source, drain electrode, the problem that the cost of manufacture that causes is high, the present invention
Embodiment provides a kind of thin film transistor (TFT) and manufacture method, array base palte and display device.Described technical scheme is as follows:
First aspect, it is provided that a kind of thin film transistor (TFT), described thin film transistor (TFT) includes:
Underlay substrate；
Described underlay substrate is formed fixed charge structure；
The underlay substrate being formed with described fixed charge structure is formed active layer, source electrode, drain and gate, described
Active layer is connected with described source electrode and described drain electrode respectively；
Wherein, the electric charge in described fixed charge structure is fixed charge, and described fixed charge structure includes: first fixes
Electric charge block and the second fixed charge block, the orthographic projection on described first fixed charge block of the described source electrode is positioned at described first and fixes
In electric charge block region, described drain electrode orthographic projection on described second fixed charge block is positioned at described second fixed charge block
In region, and described fixed charge structure contacts with described active layer.
Optionally, the electric charge in described fixed charge structure is negative charge, and the material of described fixed charge structure is three oxygen
Change two aluminum.
Optionally, the electric charge in described fixed charge structure is positive charge, and the material of described fixed charge structure is nitridation
Silicon.
Optionally, described underlay substrate is formed with cushion；
Described cushion is formed the first via and the second via；
The described underlay substrate be formed with described cushion is formed described fixed charge structure, described fixed charge
Structure and described cushion are positioned at same layer, and wherein, described first fixed charge block is positioned at described first via, and described second
Fixed charge block is positioned at described second via；
The underlay substrate being formed with described fixed charge structure is formed with described active layer；
The underlay substrate being formed with described active layer is formed described source electrode and described drain electrode；
The underlay substrate being formed with described source electrode and described drain electrode is sequentially formed with gate insulation layer and described grid.
Second aspect, it is provided that a kind of array base palte, described array base palte includes: arbitrary described thin film in first aspect
Transistor.
The third aspect, it is provided that a kind of display floater, described display floater includes: the array base palte described in second aspect.
Fourth aspect, it is provided that the manufacture method of a kind of thin film transistor (TFT), described manufacture method includes:
Underlay substrate is formed fixed charge structure；
The underlay substrate being formed with described fixed charge structure is formed with active layer, source electrode, drain and gate, described in have
Active layer is connected with described source electrode and described drain electrode respectively；
Wherein, the electric charge in described fixed charge structure is fixed charge, and described fixed charge structure includes: first fixes
Electric charge block and the second fixed charge block, the orthographic projection on described first fixed charge block of the described source electrode is positioned at described first and fixes
In electric charge block region, described drain electrode orthographic projection on described second fixed charge block is positioned at described second fixed charge block
In region, and described fixed charge structure contacts with described active layer.
Optionally, the electric charge in described fixed charge structure is negative charge, and the material of described fixed charge structure is three oxygen
Change two aluminum.
Optionally, the electric charge in described fixed charge structure is positive charge, and the material of described fixed charge structure is nitridation
Silicon.
Optionally, described on underlay substrate, form fixed charge structure, described be formed with described fixed charge structure
Underlay substrate on be formed with active layer, source electrode, drain and gate, described active layer is respectively with described source electrode and described drain electrode even
Connect, including:
Described underlay substrate is formed cushion；
Described cushion is formed the first via and the second via；
Forming described fixed charge structure on the described underlay substrate be formed with described cushion, described fixed charge is tied
Structure and described cushion are positioned at same layer, and wherein, described first fixed charge block is positioned at described first via, and described second is solid
Determine electric charge block and be positioned at described second via；
The underlay substrate being formed with described fixed charge structure forms described active layer；
The underlay substrate being formed with described active layer is formed described source electrode and described drain electrode；
The underlay substrate being formed with described source electrode and described drain electrode sequentially forms gate insulation layer and described grid.
The technical scheme that the embodiment of the present invention provides has the benefit that
The thin film transistor (TFT) of embodiment of the present invention offer and manufacture method, array base palte and display device, by lining
Form fixed charge structure on substrate, the active layer region with source, drain contact is carried out electrostatically-doped, change active layer
Fermi level height and carrier concentration so that between source, drain electrode and active layer, form good Ohmic contact.Without using height
The noble metal of work function, as source, drain electrode, can form good Ohmic contact between source, drain electrode and active layer, reduce
The manufacturing cost of thin film transistor (TFT).
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below required for make
Accompanying drawing be briefly described, it should be apparent that, below describe in accompanying drawing be only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of thin-film transistor structure schematic diagram that the present invention one illustrative examples provides；
Fig. 2 is the another kind of thin-film transistor structure schematic diagram that the present invention one illustrative examples provides；
Fig. 3 is a kind of method for fabricating thin film transistor flow chart that the present invention one illustrative examples provides；
Fig. 4 is the another kind of method for fabricating thin film transistor flow chart that the present invention one illustrative examples provides.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is the structural representation of a kind of thin film transistor (TFT) that the embodiment of the present invention provides, as it is shown in figure 1, this thin film is brilliant
Body pipe includes:
Underlay substrate 11.
Underlay substrate 11 is formed fixed charge structure 12.
The underlay substrate 11 be formed with fixed charge structure 12 is formed active layer 13, source electrode 14, drain electrode 15 and grid
Pole 16, active layer 13 is connected with source electrode 14 and drain electrode 15 respectively.Wherein, active layer 13 can be made up of CNT.
Further, the electric charge in fixed charge structure 12 is fixed charge, and fixed charge structure 12 includes: first fixes
Electric charge block 121 and the second fixed charge block 122, the source electrode 14 orthographic projection on the first fixed charge block 121 is positioned at first and fixes
In electric charge block 121 region, drain electrode 15 orthographic projections on the second fixed charge block 122 are positioned at the second fixed charge block 122
In region, and fixed charge structure 12 contacts with active layer 13.
In sum, the thin film transistor (TFT) that the embodiment of the present invention provides, tie by forming fixed charge on underlay substrate
Structure, carries out electrostatically-doped to the active layer region with source, drain contact, and the fermi level height and the carrier that change active layer are dense
Degree so that form good Ohmic contact between source, drain electrode and active layer.Without use the noble metal of high work function as source,
Drain electrode, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
It should be noted that in the thin-film transistor structure shown in Fig. 1, grid and gate insulation layer are positioned on source, drain electrode,
This structure is referred to as top gate structure, and in actual applications, grid and gate insulation layer can also be positioned under source, drain electrode, concrete
Structure is as shown in Figure 2.In Fig. 2, other structures are referred to Fig. 1, and this is not repeated by the embodiment of the present invention.
Wherein, the electric charge in fixed charge structure can be negative charge, and the material of this fixed charge structure can be three oxygen
Change two aluminum；Further, the electric charge in fixed charge structure can also be positive charge, and the material of this fixed charge structure can be
Silicon nitride.Concrete, the when of forming p-type Ohmic contact between needs source, drain electrode and active layer, can will have negative charge
Aluminium sesquioxide be set to fixed charge structure；When forming N-type Ohmic contact between needs source, drain electrode and active layer
Wait, the silicon nitride with positive charge can be set to fixed charge structure.
Fig. 1 is when the thin film transistor (TFT) of embodiment of the present invention offer is the structure during thin film transistor (TFT) using top gate structure
Schematic diagram, as it is shown in figure 1, be formed with cushion 17 on underlay substrate 11, the material of this cushion can be silicon oxide
(SiOx)；This cushion 17 is formed the first via and the second via；On the underlay substrate 11 being formed with cushion 17
Being formed with fixed charge structure 12, this fixed charge structure 12 and cushion 17 are positioned at same layer, so so that shape afterwards
The active layer become is smooth one layer, is conducive to reducing section poor.Concrete, the first fixed charge block 121 is positioned at the first via,
Second fixed charge block 122 is positioned at the second via.
Further, the underlay substrate 11 be formed with fixed charge structure 12 is formed with active layer 13；It is being formed
Source electrode 14 and drain electrode 15 it is formed with on the underlay substrate 11 of active layer 13；It is being formed with source electrode 14 and the underlay substrate 11 of drain electrode 15
On be sequentially formed with gate insulation layer 18 and grid 16；The underlay substrate 11 be formed with grid 16 is formed passivation layer 19.
Further, passivation layer 19 being formed with at least one via, each via is filled with metal material, and this is at least one years old
Individual via connects with at least one in source electrode 14, drain electrode 15 and grid 16.That is to say, passivation layer 19 can be formed one or
Multiple vias, example, passivation layer could be formed with 3 vias, source electrode 14 can be connected with data wire by a via,
Drain electrode 15 can be connected with pixel electrode by a via, and grid 16 can be connected with holding wire by a via；Actual
In application, grid and holding wire can be arranged with layer, and source electrode and data wire can be arranged with layer, now, only need to arrange a mistake
Hole realizes the connection of drain electrode and pixel electrode.
Example, in the thin film transistor (TFT) shown in Fig. 1, passivation layer is provided with metal material and source electrode, drain electrode,
Three vias that grid is respectively communicated with, wherein, be filled in the metal material of the first via 201 through passivation layer and gate insulation layer with
Source electrode connects, and the metal material being filled in the second via 202 connects through passivation layer with grid, is filled in the 3rd via 203
Metal material connects through passivation layer and gate insulation layer with drain electrode.
In the thin film transistor (TFT) shown in Fig. 2, grid is arranged with layer with holding wire, and passivation layer is provided with metal material
Two vias that material is respectively communicated with source electrode, drain electrode, are filled in the metal material of the first via 201 through passivation layer with source electrode even
Logical, the metal material being filled in the 3rd via 203 connects through passivation layer with drain electrode.Wherein, this metal material can be oxidation
Indium stannum is (English: Indium Tin Oxide；It is called for short: ITO).
It should be noted that the thin film transistor (TFT) shown in Fig. 1 and Fig. 2 simply schematically illustrates, all essences at Fig. 1 and Fig. 2
Within god and principle, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
In sum, the thin film transistor (TFT) that the embodiment of the present invention provides, tie by forming fixed charge on underlay substrate
Structure, carries out electrostatically-doped to the active layer region with source, drain contact, and the fermi level height and the carrier that change active layer are dense
Degree so that form good Ohmic contact between source, drain electrode and active layer.Without use the noble metal of high work function as source,
Drain electrode, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
Fig. 3 is the flow chart of the manufacture method of a kind of thin film transistor (TFT) that the embodiment of the present invention provides, this thin film transistor (TFT)
Manufacture method can apply to manufacture the embodiment of the present invention provide thin film transistor (TFT).The manufacture method of this thin film transistor (TFT) can
To include following several step:
Step 301, on underlay substrate formed fixed charge structure.
Step 301, on the underlay substrate being formed with fixed charge structure, it is formed with active layer, source electrode, drain and gate, has
Active layer is connected with source electrode and drain electrode respectively.
Wherein, the electric charge in fixed charge structure is fixed charge, and this fixed charge structure includes: the first fixed charge block
With the second fixed charge block, source electrode orthographic projection on the first fixed charge block is positioned at the first fixed charge block region,
Drain electrode orthographic projection on the second fixed charge block is positioned at the second fixed charge block region.
In sum, the method for fabricating thin film transistor that the embodiment of the present invention provides, solid by being formed on underlay substrate
Determine charge structure, the active layer region with source, drain contact carried out electrostatically-doped, change active layer fermi level height and
Carrier concentration so that form good Ohmic contact between source, drain electrode and active layer.Without using the noble metal of high work function
As source, drain electrode, good Ohmic contact can be formed between source, drain electrode and active layer, reduce the system of thin film transistor (TFT)
Cause this.
Fig. 4 is the flow chart of the manufacture method of the another kind of thin film transistor (TFT) that the embodiment of the present invention provides, this film crystal
The manufacture method of pipe can apply to manufacture the thin film transistor (TFT) that the embodiment of the present invention provides.The manufacture method of this thin film transistor (TFT)
Can include following several step:
Step 401, on underlay substrate formed fixed charge structure.
Optionally, the making material of this underlay substrate includes the transparent materials such as glass, silicon chip, quartz and plastics, preferably
For glass.
Example, as it is shown in figure 1, when the thin film transistor (TFT) of embodiment of the present invention offer is the thin film crystalline substance using top gate structure
During body pipe, cushion can be formed on underlay substrate, form via on the buffer layer, shape on the cushion be formed with via
Become fixed charge structure.
Concrete, can be sunk by PECVD on underlay substrate under conditions of 350 degrees Celsius
Area method is (English: Plasma Enhanced Chemical Vapor Deposition；It is called for short: PECVD) form cushion, should
The thickness of cushion can be 100 nanometers (nm)；Then by a patterning processes on the cushion being positioned on underlay substrate
Forming via, this patterning processes may include that photoetching coats, exposes, develops, etches and photoresist lift off.Concrete, first
Coated by photoetching, expose, the position defining fixed charge structure on the buffer layer of developing, then shelled by etching, photoresist
From forming via.Wherein, this etching technics can be in the environment of carbon tetrafluoride and oxygen, the dry etching carried out；Enter one
Step ground, forms fixed charge layer by the way of deposition, then to this fixed charge layer by a composition work
Skill forms the fixed charge structure being positioned at cushion via, and this patterning processes may include that photoetching coats, exposes, shows
Shadow, etching and photoresist lift off.Wherein, this etching technics can be that the dry method carried out in the environment of carbon tetrafluoride and oxygen is carved
Erosion.
Example, as in figure 2 it is shown, when the thin film transistor (TFT) that the embodiment of the present invention provides is common thin film transistor (TFT),
Can form gate metal figure on underlay substrate, wherein, this gate metal figure includes: grid and holding wire.Formed
There is formation gate insulation layer on the underlay substrate of gate metal figure, the underlay substrate be formed with gate insulation layer is formed fixing electricity
Lotus structure.
Concrete, can on underlay substrate one of which formation grid by deposit, applying, in the various ways such as sputtering
Pole metal level, then forms gate metal figure to this gate metal layer by a patterning processes, and this patterning processes can
To include: photoetching coats, exposes, develops, etches and photoresist lift off；Further, by depositing, applying, sputtering etc. multiple
One of which in mode forms layer gate insulating film layer, then by a patterning processes, this layer gate insulating film layer is formed gate insulation
Layer, this patterning processes may include that photoetching coats, exposes, develops, etches and photoresist lift off；Further, by heavy
One layer of fixed charge layer of long-pending formation, the thickness range of this fixed charge layer can be 50nm～100nm, this
Bright embodiment illustrates as a example by thickness is as 100nm.Then to this fixed charge layer by a patterning processes shape
Becoming fixed charge structure, this patterning processes may include that photoetching coats, exposes, develops, etches and photoresist lift off.Its
In, this etching technics can be in the environment of carbon tetrafluoride and oxygen, the dry etching carried out.
Step 402, on the underlay substrate being formed with fixed charge structure, it is formed with active layer.
Concrete, by its in the various ways such as dip-coating, spin coating on the underlay substrate being formed with fixed charge structure
Middle one is formed with active layer film layer, then by a patterning processes, this active tunic layer is formed with active layer, this composition work
Skill includes: photoetching coats, exposes, develops, etches and photoresist lift off.Wherein, this etching technics can be the environment at oxygen
Under the reactive ion etching that carries out (English: Reactive Ion Etching；It is called for short: RIE).
Step 403, formation source, drain electrode on the underlay substrate be formed with active layer.
Example, as it is shown in figure 1, when the thin film transistor (TFT) of embodiment of the present invention offer is the thin film crystalline substance using top gate structure
During body pipe, source, drain electrode can be formed on the underlay substrate be formed with active layer, formed on underlay substrate active, that drain
Form gate insulation layer, the underlay substrate be formed with gate insulation layer is formed grid.
Concrete, can on the underlay substrate be formed with active layer by depositing, applying, in the various ways such as sputtering
One of which forms source, drain metal layer, then by a patterning processes, this source, drain metal layer is formed source, drain electrode, should
Patterning processes may include that photoetching coats, exposes, develops, etches and photoresist lift off；Further, by PECVD shape
Becoming gate insulation layer, wherein, the material of this gate insulation layer can be SiOx, and the thickness of this gate insulation layer can be 100nm；Further
Ground, forms gate metal layer by the way of sputtering, deposition, and wherein, the material of this gate metal layer can be molybdenum (Mo), these grid
The thickness of pole metal level can be 220nm, then by a patterning processes, this gate metal layer is formed grid, this structure
Figure technique may include that photoetching coats, exposes, develops, etches and photoresist lift off.
Example, as in figure 2 it is shown, when the thin film transistor (TFT) that the embodiment of the present invention provides is common thin film transistor (TFT),
Source, drain electrode can be formed on the underlay substrate be formed with active layer.
Concrete, can on the underlay substrate be formed with active layer by depositing, applying, in the various ways such as sputtering
One of which forms source, drain metal layer, and wherein, this source, the material of drain metal layer can be copper (Cu) or nickel (Ni), should
Source, the thickness of drain metal layer can be 100nm, then by a patterning processes, this source, drain metal layer formed source, leakage
Pole, this patterning processes may include that photoetching coats, exposes, develops, etches and photoresist lift off.
Step 404, formed active, drain electrode underlay substrate on formed passivation layer.
Concrete, form passivation layer, the thickness of this passivation layer by PECVD being formed on underlay substrate active, that drain
Can be 300nm.Wherein, the material of this passivation layer can be silicon nitride (SiNx).
Step 405, on the passivation layer being positioned on underlay substrate formed via.
Example, as it is shown in figure 1, when the thin film transistor (TFT) of embodiment of the present invention offer is the thin film crystalline substance using top gate structure
During body pipe, the first via the 201, the 3rd via 203 and connected with source electrode, drain electrode, grid respectively can be formed over the passivation layer
Second via 202.
Example, as in figure 2 it is shown, when the thin film transistor (TFT) that the embodiment of the present invention provides is common thin film transistor (TFT),
The first via 201 and the 3rd via 203 connected with source electrode, drain electrode respectively can be formed over the passivation layer.
Concrete, on the passivation layer being positioned on underlay substrate, form via by a patterning processes, this composition
Technique may include that photoetching coats, exposes, develops, etches and photoresist lift off.
Step 406, in via filler metal material.
Concrete, by the way of sputtering, deposit metal material in via over the passivation layer, wherein, this metal material can
Thinking ITO, the thickness of this metal material can be 135nm.Then the metal material deposited is carried out a patterning processes to complete
Manufacturing process, this patterning processes may include that photoetching coats, exposes, develops, etches and photoresist lift off.
In sum, the method for fabricating thin film transistor that the embodiment of the present invention provides, solid by being formed on underlay substrate
Determine charge structure, the active layer region with source, drain contact carried out electrostatically-doped, change active layer fermi level height and
Carrier concentration so that form good Ohmic contact between source, drain electrode and active layer.Without using the noble metal of high work function
As source, drain electrode, good Ohmic contact can be formed between source, drain electrode and active layer, reduce the system of thin film transistor (TFT)
Cause this.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, and the method for foregoing description
Concrete steps, the corresponding process being referred in previous embodiment, do not repeat them here.
The embodiment of the present invention additionally provides a kind of array base palte, and it is thin that this array base palte includes that aforementioned any embodiment provides
Film transistor.Specifically, this array base palte includes underlay substrate, wherein, and the underlay substrate on this array base palte and film crystal
The underlay substrate of pipe is same underlay substrate.Holding wire, data wire, pixel electrode and aforementioned thin can be provided with on this underlay substrate
Film transistor, the drain electrode of this thin film transistor (TFT) can be connected with pixel electrode layer, and the grid of thin film transistor (TFT) can be with holding wire
Connecting, the source electrode of thin film transistor (TFT) can be connected with data wire.
In sum, the array base palte that the embodiment of the present invention provides, by forming fixed charge structure on underlay substrate,
Active layer region with source, drain contact is carried out electrostatically-doped, changes fermi level height and the carrier concentration of active layer,
Make to be formed between source, drain electrode and active layer good Ohmic contact.Without using the noble metal of high work function as source, leakage
Pole, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
Based on identical inventive concept, the embodiment of the present invention additionally provides a kind of display device, before this display device includes
State the array base palte that embodiment provides.This display device generally includes array base palte and display base plate, example, array base palte and
Box is shaped after adding liquid crystal by display base plate, combines with backlight module etc. and forms this display device.
In the specific implementation, the display device that the embodiment of the present invention provides can be mobile phone, panel computer, television set, show
Show any product with display function or the parts such as device, notebook computer, DPF, navigator.
In sum, the display device that the embodiment of the present invention provides, by forming fixed charge structure on underlay substrate,
Active layer region with source, drain contact is carried out electrostatically-doped, changes fermi level height and the carrier concentration of active layer,
Make to be formed between source, drain electrode and active layer good Ohmic contact.Without using the noble metal of high work function as source, leakage
Pole, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (10)
1. a thin film transistor (TFT), it is characterised in that including:
Underlay substrate；
Described underlay substrate is formed fixed charge structure；
The underlay substrate being formed with described fixed charge structure is formed active layer, source electrode, drain and gate, described active
Layer is connected with described source electrode and described drain electrode respectively；
Wherein, the electric charge in described fixed charge structure is fixed charge, and described fixed charge structure includes: the first fixed charge
Block and the second fixed charge block, the orthographic projection on described first fixed charge block of the described source electrode is positioned at described first fixed charge
In block region, described drain electrode orthographic projection on described second fixed charge block is positioned at described second fixed charge block place
In region, and described fixed charge structure contacts with described active layer.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that the electric charge in described fixed charge structure is negative electricity
Lotus, the material of described fixed charge structure is aluminium sesquioxide.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that the electric charge in described fixed charge structure is positive electricity
Lotus, the material of described fixed charge structure is silicon nitride.
4. according to the arbitrary described thin film transistor (TFT) of claims 1 to 3, it is characterised in that
Described underlay substrate is formed with cushion；
Described cushion is formed the first via and the second via；
The described underlay substrate be formed with described cushion is formed described fixed charge structure, described fixed charge structure
Being positioned at same layer with described cushion, wherein, described first fixed charge block is positioned at described first via, and described second fixes
Electric charge block is positioned at described second via；
The underlay substrate being formed with described fixed charge structure is formed with described active layer；
The underlay substrate being formed with described active layer is formed described source electrode and described drain electrode；
The underlay substrate being formed with described source electrode and described drain electrode is sequentially formed with gate insulation layer and described grid.
5. an array base palte, it is characterised in that including: the arbitrary described thin film transistor (TFT) of Claims 1-4.
6. a display device, it is characterised in that this display device includes the array base palte described in claim 5.
7. the manufacture method of a thin film transistor (TFT), it is characterised in that including:
Underlay substrate is formed fixed charge structure；
The underlay substrate being formed with described fixed charge structure is formed active layer, source electrode, drain and gate, described active layer
It is connected with described source electrode and described drain electrode respectively；
Wherein, the electric charge in described fixed charge structure is fixed charge, and described fixed charge structure includes: the first fixed charge
Block and the second fixed charge block, the orthographic projection on described first fixed charge block of the described source electrode is positioned at described first fixed charge
In block region, described drain electrode orthographic projection on described second fixed charge block is positioned at described second fixed charge block place
In region, and described fixed charge structure contacts with described active layer.
Manufacture method the most according to claim 7, it is characterised in that the electric charge in described fixed charge structure is negative electricity
Lotus, the material of described fixed charge structure is aluminium sesquioxide.
Manufacture method the most according to claim 7, it is characterised in that the electric charge in described fixed charge structure is positive electricity
Lotus, the material of described fixed charge structure is silicon nitride.
10. according to the arbitrary described manufacture method of claim 7 to 9, it is characterised in that described formation on underlay substrate is fixed
Charge structure, described is formed with active layer, source electrode, drain and gate on the underlay substrate being formed with described fixed charge structure,
Described active layer is connected with described source electrode and described drain electrode respectively, including:
Described underlay substrate is formed cushion；
Described cushion is formed the first via and the second via；
The described underlay substrate be formed with described cushion forms described fixed charge structure, described fixed charge structure with
Described cushion is positioned at same layer, and wherein, described first fixed charge block is positioned at described first via, the described second fixing electricity
Lotus block is positioned at described second via；
The underlay substrate being formed with described fixed charge structure forms described active layer；
The underlay substrate being formed with described active layer is formed described source electrode and described drain electrode；
The underlay substrate being formed with described source electrode and described drain electrode sequentially forms gate insulation layer and described grid.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106991956A (en) * | 2017-06-05 | 2017-07-28 | 京东方科技集团股份有限公司 | A kind of image element circuit and its driving method and its preparation method, display device |
| CN107978631A (en) * | 2017-12-27 | 2018-05-01 | 上海大学 | A kind of thin film transistor (TFT) film layer, manufacturing method and apparatus |
| CN114068703A (en) * | 2020-07-31 | 2022-02-18 | 北京华碳元芯电子科技有限责任公司 | Transistor and preparation method |
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| CN1906770A (en) * | 2004-01-23 | 2007-01-31 | 惠普开发有限公司 | Transistor including a deposited channel region having a doped portion |
| CN103299445A (en) * | 2011-01-13 | 2013-09-11 | 国际商业机器公司 | Radiation hardened transistors based on graphene and carbon nanotubes |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1906770A (en) * | 2004-01-23 | 2007-01-31 | 惠普开发有限公司 | Transistor including a deposited channel region having a doped portion |
| CN103299445A (en) * | 2011-01-13 | 2013-09-11 | 国际商业机器公司 | Radiation hardened transistors based on graphene and carbon nanotubes |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106991956A (en) * | 2017-06-05 | 2017-07-28 | 京东方科技集团股份有限公司 | A kind of image element circuit and its driving method and its preparation method, display device |
| US11081047B2 (en) | 2017-06-05 | 2021-08-03 | Boe Technology Group Co., Ltd. | Pixel structure, driving method therefor and preparation method therefor, and display apparatus |
| CN107978631A (en) * | 2017-12-27 | 2018-05-01 | 上海大学 | A kind of thin film transistor (TFT) film layer, manufacturing method and apparatus |
| CN107978631B (en) * | 2017-12-27 | 2024-04-30 | 上海大学 | Thin film transistor film layer, manufacturing method and device |
| CN114068703A (en) * | 2020-07-31 | 2022-02-18 | 北京华碳元芯电子科技有限责任公司 | Transistor and preparation method |
| CN114068703B (en) * | 2020-07-31 | 2024-03-19 | 北京华碳元芯电子科技有限责任公司 | Transistor and preparation method |
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