CN106230438A - A kind of capacitance mismatch for production line analog-digital converter tests System and method for - Google Patents
A kind of capacitance mismatch for production line analog-digital converter tests System and method for Download PDFInfo
- Publication number
- CN106230438A CN106230438A CN201610632854.0A CN201610632854A CN106230438A CN 106230438 A CN106230438 A CN 106230438A CN 201610632854 A CN201610632854 A CN 201610632854A CN 106230438 A CN106230438 A CN 106230438A
- Authority
- CN
- China
- Prior art keywords
- input
- negative
- circuit
- capacitance
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a kind of capacitance mismatch for production line analog-digital converter and test System and method for, described system includes signal port, flash adc circuit, MDAC circuit and test injection circuit, described signal port is connected with flash adc circuit and MDAC circuit respectively, the outfan of flash adc circuit is connected with MDAC circuit, and described test injection circuit is connected with flash adc circuit.The present invention is when specifically testing, and internal system circuit is successively in sample phase and amplification stage；Being connected with common-mode signal at sample phase, input signal vinp and vinn, first kind switch Guan Bi, Equations of The Second Kind disconnects, and sampling capacitance is attached with input signal, and test injection circuit produces control signal and sends into flash adc circuit；At amplification stage, Equations of The Second Kind switch Guan Bi, the first kind switches off, sampling capacitance according to the output of flashADC with the most just or negative reference voltage is attached；In the middle of whole test process, sampling capacitance is not required to the switch of special connection common mode signal.
Description
Technical field
The present invention relates to a kind of capacitance mismatch for production line analog-digital converter and test System and method for.
Background technology
Production line analog-digital converter uses the structure of plural serial stage to realize, and the output of upper level is as the input of next stage.
Electric capacity is all used to carry out the sampling of input signal and the output of residual signals in the middle of the circuit structure of every one-level.Internal capacitance presses merit
Sampling capacitance and feedback capacity can be divided into, ideally, be fixed ratio between each sampling capacitance and feedback capacity,
But due to the difference of manufacturing process, operating temperature and running voltage, the ratio between each sampling capacitance and feedback capacity can go out
Existing difference, here it is capacitance mismatch.Capacitance mismatch can cause residual error output and the actual value of the every one-level of production line analog-digital converter
There is deviation, cause the dynamic range of analog to digital conversion circuit output result and signal to noise ratio substantially to reduce.
The test of current existing capacitance mismatch is all to test sampling capacitance one by one, and other non-test sampling capacitances need
Individually to switch connection common mode, so on circuit structure, sampling capacitance is at amplification stage need during except meeting normal work
Connecting outside two switches of positive and negative reference, in addition it is also necessary to extra switch is attached with common mode, this switch increased can be led
Cause signal load during normal work and become big, for the production line analog-digital converter of high-speed, high precision, can be to the foundation of signal
Bring and have a strong impact on.Survey therefore, it is necessary to design a kind of capacitance mismatch being applicable to high-speed high-precision flow line analog-digital converter
Method for testing.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of electric capacity for production line analog-digital converter
Mismatch test System and method for.
It is an object of the invention to be achieved through the following technical solutions: a kind of electric capacity for production line analog-digital converter
Mismatch test system, including signal port, flash adc circuit, MDAC circuit and test injection circuit, described signal
Port is connected with flash adc circuit and MDAC circuit respectively, and the outfan of flash adc circuit is connected with MDAC circuit, institute
The test injection circuit stated is connected with flash adc circuit.
Described signal port includes the first differential signal end and the second differential signal end；First differential signal end with
The positive polarity input of flash adc circuit connects, and the second differential signal end connects with the negative polarity input of flash adc circuit
Connect；First differential signal end is used for input signal vinp, and the second differential signal end is used for input signal vinn.
Described MDAC circuit includes Differential Input operational amplifier, positive pole sampling capacitance group, negative pole sampling capacitance group, just
Pole feedback capacity group and negative feedback capacitance group；
Described positive pole sampling capacitance group includes multiple positive pole sampling capacitance；Positive pole sampling capacitance the first end is believed with the first difference respectively
The positive polarity input of number end and MADC connects, the second end of positive pole sampling capacitance and the positive polarity of Differential Input operational amplifier
Input connects；
Described negative pole sampling capacitance group includes multiple negative pole sampling capacitance, and the first end of described negative pole sampling capacitance is respectively with first
The negative polarity input of differential signal end and MADC connects, the second end of negative pole sampling capacitance and Differential Input operational amplifier
Negative polarity input connects；
Described positive pole feedback capacity group includes multiple positive pole feedback capacity, the first end of described positive pole feedback capacity and Differential Input
The positive polarity input of operational amplifier connects, the second end of positive pole feedback capacity and the positive polarity of Differential Input operational amplifier
Outfan connects；
Described negative feedback capacitance group includes multiple negative feedback electric capacity, the first end of described negative feedback electric capacity and Differential Input
The negative polarity input of operational amplifier connects, the second end of negative feedback electric capacity and the negative polarity of Differential Input operational amplifier
Outfan connects.
First end of described positive pole sampling capacitance is connected with the first differential signal end by first kind switch, and positive pole is sampled
First end of electric capacity is connected with the positive polarity input of MADC also by Equations of The Second Kind switch；
Described negative pole sampling capacitance is connected with the second differential signal input by first kind switch, the first of negative pole sampling capacitance
Hold and be connected with the negative polarity input of MADC also by Equations of The Second Kind switch.
The positive polarity input of described MADC includes that multiple positive pole input channel, each positive pole input channel both correspond to one
Individual positive pole sampling capacitance and the drive test trial signal coming from flash adc circuit；Described positive pole input channel is for according to note
The positive negative reference voltage of test signal behavior entered；
The negative polarity input of described MADC includes multiple negative pole input channel, and each negative pole input channel corresponds to a negative pole
Sampling capacitance and from the road reference voltage with flash adc circuit；Described negative pole input channel is for according to sampling electricity
The positive negative reference voltage of test signal behavior held.
Described a kind of capacitance mismatch for production line analog-digital converter tests the method for testing of system, including sampling step
Rapid S1 and amplification procedure S2；
Described sampling step S1 includes following sub-step:
S11. input signal vinp and vinn are connected with common-mode signal, and first kind switch Guan Bi, Equations of The Second Kind switches off；
S12. sampling capacitance connects with corresponding differential signal input, and test injection circuit produces control signal and sends into
Flash adc circuit；
Described amplification procedure S2 includes:
S21. by Equations of The Second Kind switch Guan Bi, the first kind switches off；
S22. the test signal that sampling capacitance exports according to flashADC circuit, is the most just selecting or negative reference voltage is being carried out
Connect.
The test signal of the flashADC circuit output described in step S22 is when being low level, positive pole sampling capacitance with just
Reference voltage connects, and negative polarity sampling capacitance is connected with negative reference voltage, and the test signal of the output of flashADC circuit is high
During level, positive pole sampling capacitance is connected with negative reference voltage, and negative pole sampling capacitance is connected with reference voltage.
The invention has the beneficial effects as follows: when specifically testing, internal system circuit is successively in sample phase and amplifies rank
Section；Being connected with common-mode signal at sample phase, input signal vinp and vinn, first kind switch Guan Bi, Equations of The Second Kind disconnects, sampling
Electric capacity is attached with input signal, and test injection circuit produces control signal and sends into flash adc circuit；Amplifying
Stage, Equations of The Second Kind switch Guan Bi, the first kind switches off, sampling capacitance according to the output of flashADC with corresponding the most just or negative ginseng
Examine voltage to be attached；In the middle of whole test process, sampling capacitance is not required to the switch of special connection common mode signal.
Accompanying drawing explanation
Fig. 1 is the system principle diagram of the present invention；
Fig. 2 is MDAC Circuits System block diagram；
Fig. 3 is the schematic diagram of test signal poll.
Detailed description of the invention
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
The following stated.
As it is shown in figure 1, a kind of capacitance mismatch for production line analog-digital converter tests system, including signal port,
Flash adc circuit, MDAC circuit and test injection circuit, described signal port respectively with flash adc circuit and
MDAC circuit connect, the outfan of flash adc circuit is connected with MDAC circuit, described test injection circuit and
Flash adc circuit connects.
Described signal port includes the first differential signal end and the second differential signal end；First differential signal end with
The positive polarity input of flash adc circuit connects, and the second differential signal end connects with the negative polarity input of flash adc circuit
Connect；First differential signal end is used for input signal vinp, and the second differential signal end is used for input signal vinn.
Described MDAC circuit includes Differential Input operational amplifier, positive pole sampling capacitance group, negative pole sampling capacitance group, just
Pole feedback capacity group and negative feedback capacitance group；
Described positive pole sampling capacitance group includes multiple positive pole sampling capacitance；Positive pole sampling capacitance the first end is believed with the first difference respectively
The positive polarity input of number end and MADC connects, the second end of positive pole sampling capacitance and the positive polarity of Differential Input operational amplifier
Input connects；
Described negative pole sampling capacitance group includes multiple negative pole sampling capacitance, and the first end of described negative pole sampling capacitance is respectively with first
The negative polarity input of differential signal end and MADC connects, the second end of negative pole sampling capacitance and Differential Input operational amplifier
Negative polarity input connects；
Described positive pole feedback capacity group includes multiple positive pole feedback capacity, the first end of described positive pole feedback capacity and Differential Input
The positive polarity input of operational amplifier connects, the second end of positive pole feedback capacity and the positive polarity of Differential Input operational amplifier
Outfan connects；
Described negative feedback capacitance group includes multiple negative feedback electric capacity, the first end of described negative feedback electric capacity and Differential Input
The negative polarity input of operational amplifier connects, the second end of negative feedback electric capacity and the negative polarity of Differential Input operational amplifier
Outfan connects.
First end of described positive pole sampling capacitance by first kind switch 1 be connected with the first differential signal end (i.e. with
Signal vinp connects), the first end of positive pole sampling capacitance connects also by the positive polarity input of Equations of The Second Kind switch 2 with MADC
Connect；
Described negative pole sampling capacitance is connected with the second differential signal input (i.e. with signal vinn even by first kind switch 1
Connect), the first end of negative pole sampling capacitance is connected with the negative polarity input of MADC also by Equations of The Second Kind switch 2.
The positive polarity input of described MADC includes that multiple positive pole input channel, each positive pole input channel both correspond to one
Individual positive pole sampling capacitance and the drive test trial signal coming from flash adc circuit；Described positive pole input channel is for according to note
The positive negative reference voltage of test signal behavior entered；
The negative polarity input of described MADC includes multiple negative pole input channel, and each negative pole input channel corresponds to a negative pole
Sampling capacitance and from the road reference voltage with flash adc circuit；Described negative pole input channel is for according to sampling electricity
The positive negative reference voltage of test signal behavior held.
Described a kind of capacitance mismatch for production line analog-digital converter tests the method for testing of system, and its feature exists
In: include sampling step S1 and amplification procedure S2；
Described sampling step S1 includes following sub-step:
S11. input signal vinp and vinn are connected with common-mode signal, the first kind 1 switch Guan Bi, Equations of The Second Kind switch 2 disconnection；
S12. sampling capacitance connects with corresponding differential signal input, and test injection circuit produces control signal and sends into
Flash adc circuit；
Described amplification procedure S2 includes:
S21. by Equations of The Second Kind switch 2 Guan Bi, first kind switch 1 disconnection；
S22. the test signal that sampling capacitance exports according to flashADC circuit, is the most just selecting or negative reference voltage is being carried out
Connect.
The test signal of the flashADC circuit output described in step S22 is when being low level, positive pole sampling capacitance with just
Reference voltage connects, and negative polarity sampling capacitance is connected with negative reference voltage, and the test signal of the output of flashADC circuit is high
During level, positive pole sampling capacitance is connected with negative reference voltage, and negative pole sampling capacitance is connected with reference voltage.
Specifically, the output of flashADC circuit and input differential signal vinp, vinn are unrelated, are completely controlled by test letter
Number injection circuit, C1=D1, C2=D2 ..., Cm=Dm, test signal and sampling capacitance one_to_one corresponding；As it is shown on figure 3, test letter
When number being low level, MDAC positive ends correspondence sampling capacitance amplification stage with just with reference to being attached, MDAC negative polarity end
Corresponding sampling capacitance is attached with negative reference at amplification stage；When test signal is high level, MDAC positive ends correspondence is adopted
Sample electric capacity is attached with negative reference at amplification stage, and MDAC negative polarity end correspondence sampling capacitance enters with just reference at amplification stage
Row connects.
All sampling capacitances connect common mode in sample phase by input signal vinp, vinn, and amplification stage is respectively sampled electricity
Hold the test signal according to injecting and connect positive negative reference voltage accordingly, repeatedly tested by poll test signal；It is different from
Existing method of testing needs measured capacitance to be connected with positive and negative reference respectively one by one, and other non-measured capacitance connect the side of common mode
Formula, the present invention need not sampling capacitance is connected common mode electrical level, eliminates unnecessary switch, and its circuit overhead is less and will not
When increasing normal work, the load of signal path, is more suitably applied in the middle of the production line analog-digital converter of high-speed, high precision.
Embodiment one, has the circuit of M sampling capacitance respectively for MDAC positive-negative polarity end, tests signal demand poll M
Secondary.In order to be removed by the DC offset in the middle of circuit in the middle of calculating process, test signal demand step-by-step negates, so altogether
Need poll 2*M time；Specifically:
MDAC positive-negative polarity end is had respectively to the circuit of M sampling capacitance, need altogether the test signal of M-bit, each ratio
Special test signal only has 0 and 1 two state to be attached with negative reference or just reference for controlling corresponding sampling capacitance；?
In the middle of the process of test signal poll, the number of 0 and 1 is all constant, the MDAC that the concrete number of 0 and 1 needs according to test
Circuit output signal amplitude determines；With the number of 0 during test signal poll for i example, a kind of mode such as Fig. 3 institute of signal poll
Showing, it is assumed that when test signal is low level, MDAC positive ends correspondence sampling capacitance is attached with just reference at amplification stage,
MDAC negative polarity end correspondence sampling capacitance is attached with negative reference at amplification stage；When test signal is high level, MDAC is just
Polar end correspondence sampling capacitance is attached with negative reference at amplification stage, and MDAC negative polarity end correspondence sampling capacitance is amplifying rank
Duan Yuzheng is with reference to being attached, and M time poll can obtain M test result, can calculate M to sampling capacitance value with homographic solution, to M
The test signal step-by-step of secondary poll negates and will obtain M test result, and calculates M another group to sampling capacitance accordingly
Two corresponding for every a pair sampling capacitance class values are subtracted each other by value, i.e. can obtain this to electric capacity without the test result of direct current offset.
Claims (7)
1. one kind for production line analog-digital converter capacitance mismatch test system, it is characterised in that: include signal port,
Flash adc circuit, MDAC circuit and test injection circuit, described signal port respectively with flash adc circuit and
MDAC circuit connect, the outfan of flash adc circuit is connected with MDAC circuit, described test injection circuit and
Flash adc circuit connects.
A kind of capacitance mismatch for production line analog-digital converter the most according to claim 1 tests system, and its feature exists
In: described signal port includes the first differential signal end and the second differential signal end；First differential signal end and flash ADC
The positive polarity input of circuit connects, and the second differential signal end is connected with the negative polarity input of flash adc circuit；First is poor
Sub-signal end is used for input signal vinp, and the second differential signal end is used for input signal vinn.
A kind of capacitance mismatch for production line analog-digital converter the most according to claim 1 tests system, and its feature exists
In: described MDAC circuit includes that Differential Input operational amplifier, positive pole sampling capacitance group, negative pole sampling capacitance group, positive pole are anti-
Feedback capacitance group and negative feedback capacitance group；
Described positive pole sampling capacitance group includes multiple positive pole sampling capacitance；Positive pole sampling capacitance the first end is believed with the first difference respectively
The positive polarity input of number end and MADC connects, the second end of positive pole sampling capacitance and the positive polarity of Differential Input operational amplifier
Input connects；
Described negative pole sampling capacitance group includes multiple negative pole sampling capacitance, and the first end of described negative pole sampling capacitance is respectively with first
The negative polarity input of differential signal end and MADC connects, the second end of negative pole sampling capacitance and Differential Input operational amplifier
Negative polarity input connects；
Described positive pole feedback capacity group includes multiple positive pole feedback capacity, the first end of described positive pole feedback capacity and Differential Input
The positive polarity input of operational amplifier connects, the second end of positive pole feedback capacity and the positive polarity of Differential Input operational amplifier
Outfan connects；
Described negative feedback capacitance group includes multiple negative feedback electric capacity, the first end of described negative feedback electric capacity and Differential Input
The negative polarity input of operational amplifier connects, the second end of negative feedback electric capacity and the negative polarity of Differential Input operational amplifier
Outfan connects.
A kind of capacitance mismatch for production line analog-digital converter the most according to claim 1 tests system, and its feature exists
In: the first end of described positive pole sampling capacitance is connected with the first differential signal end by first kind switch, positive pole sampling capacitance
The first end also by Equations of The Second Kind switch be connected with the positive polarity input of MADC；
Described negative pole sampling capacitance is connected with the second differential signal input by first kind switch, the first of negative pole sampling capacitance
Hold and be connected with the negative polarity input of MADC also by Equations of The Second Kind switch.
A kind of capacitance mismatch for production line analog-digital converter the most according to claim 1 tests system, and its feature exists
In: the positive polarity input of described MADC includes that multiple positive pole input channel, each positive pole input channel are just both corresponding to one
Pole sampling capacitance and the drive test trial signal coming from flash adc circuit；Described positive pole input channel is for according to injection
The test positive negative reference voltage of signal behavior；
The negative polarity input of described MADC includes multiple negative pole input channel, and each negative pole input channel corresponds to a negative pole
Sampling capacitance and from the road reference voltage with flash adc circuit；Described negative pole input channel is for according to sampling electricity
The positive negative reference voltage of test signal behavior held.
6. test system according to a kind of capacitance mismatch for production line analog-digital converter described in any one in claim 1 ~ 5
The method of testing of system, it is characterised in that: include sampling step S1 and amplification procedure S2；
Described sampling step S1 includes following sub-step:
S11. input signal vinp and vinn are connected with common-mode signal, and first kind switch Guan Bi, Equations of The Second Kind switches off；
S12. sampling capacitance connects with corresponding differential signal input, and test injection circuit produces control signal and sends into
Flash adc circuit；
Described amplification procedure S2 includes:
S21. by Equations of The Second Kind switch Guan Bi, the first kind switches off；
S22. the test signal that sampling capacitance exports according to flashADC circuit, is the most just selecting or negative reference voltage is being carried out
Connect.
A kind of capacitance mismatch for production line analog-digital converter the most according to claim 6 tests the test side of system
Method, it is characterised in that: when the test signal of the flashADC circuit output described in step S22 is low level, positive pole sampling electricity
Holding and be connected with reference voltage, negative polarity sampling capacitance is connected with negative reference voltage, the test letter of the output of flashADC circuit
When number being high level, positive pole sampling capacitance is connected with negative reference voltage, and negative pole sampling capacitance is connected with reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610632854.0A CN106230438A (en) | 2016-08-04 | 2016-08-04 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610632854.0A CN106230438A (en) | 2016-08-04 | 2016-08-04 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106230438A true CN106230438A (en) | 2016-12-14 |
Family
ID=57547524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610632854.0A Pending CN106230438A (en) | 2016-08-04 | 2016-08-04 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106230438A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110098836A (en) * | 2018-01-31 | 2019-08-06 | 长沙泰科阳微电子有限公司 | A kind of MDAC structure suitable for pipeline ADC |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
| CN1599254A (en) * | 2004-08-31 | 2005-03-23 | 东南大学 | Capacity mismatch calibrating device |
| CN101222230A (en) * | 2008-01-24 | 2008-07-16 | 上海萌芯电子科技有限公司 | Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error |
| CN101777917A (en) * | 2010-01-14 | 2010-07-14 | 上海迦美信芯通讯技术有限公司 | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof |
| CN101814920A (en) * | 2010-05-05 | 2010-08-25 | 余浩 | Analog-digital converter with sample hold and MDAC (Multiplying Digital-to-Analog Conversion) sharing capacitance and operational amplifier in time sharing way |
| CN101834606A (en) * | 2009-03-09 | 2010-09-15 | 复旦大学 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
| CN102255615A (en) * | 2010-05-20 | 2011-11-23 | 复旦大学 | Microsoft data access component (MDAC) structure applied to pipeline analogue-to-digital converter |
| CN102594352A (en) * | 2012-03-02 | 2012-07-18 | 西北工业大学 | Sample hold circuit and method for expanding dynamic range of streamline analog to digital converter using sample hold circuit |
| CN102983863A (en) * | 2012-12-18 | 2013-03-20 | 天津大学 | First-stage circuit structure of pipelined analog-to-digital converter |
| CN103703686A (en) * | 2011-06-10 | 2014-04-02 | 密克罗奇普技术公司 | Modified dynamic element matching for reduced latency in a pipeline analog to digital converter |
| CN103762982A (en) * | 2014-01-16 | 2014-04-30 | 东南大学 | Capacitance mismatch fast calibrating circuit of analog-digital converter and calibrating method |
| CN104124969A (en) * | 2013-04-26 | 2014-10-29 | 上海华虹宏力半导体制造有限公司 | Pipelined analog-to-digital converter |
| CN104363019A (en) * | 2014-09-18 | 2015-02-18 | 电子科技大学 | Pipeline analog-to-digital converter and capacitance mismatch error calibration method thereof |
-
2016
- 2016-08-04 CN CN201610632854.0A patent/CN106230438A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
| CN1599254A (en) * | 2004-08-31 | 2005-03-23 | 东南大学 | Capacity mismatch calibrating device |
| CN101222230A (en) * | 2008-01-24 | 2008-07-16 | 上海萌芯电子科技有限公司 | Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error |
| CN101834606A (en) * | 2009-03-09 | 2010-09-15 | 复旦大学 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
| CN101777917A (en) * | 2010-01-14 | 2010-07-14 | 上海迦美信芯通讯技术有限公司 | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof |
| CN101814920A (en) * | 2010-05-05 | 2010-08-25 | 余浩 | Analog-digital converter with sample hold and MDAC (Multiplying Digital-to-Analog Conversion) sharing capacitance and operational amplifier in time sharing way |
| CN102255615A (en) * | 2010-05-20 | 2011-11-23 | 复旦大学 | Microsoft data access component (MDAC) structure applied to pipeline analogue-to-digital converter |
| CN103703686A (en) * | 2011-06-10 | 2014-04-02 | 密克罗奇普技术公司 | Modified dynamic element matching for reduced latency in a pipeline analog to digital converter |
| CN102594352A (en) * | 2012-03-02 | 2012-07-18 | 西北工业大学 | Sample hold circuit and method for expanding dynamic range of streamline analog to digital converter using sample hold circuit |
| CN102983863A (en) * | 2012-12-18 | 2013-03-20 | 天津大学 | First-stage circuit structure of pipelined analog-to-digital converter |
| CN104124969A (en) * | 2013-04-26 | 2014-10-29 | 上海华虹宏力半导体制造有限公司 | Pipelined analog-to-digital converter |
| CN103762982A (en) * | 2014-01-16 | 2014-04-30 | 东南大学 | Capacitance mismatch fast calibrating circuit of analog-digital converter and calibrating method |
| CN104363019A (en) * | 2014-09-18 | 2015-02-18 | 电子科技大学 | Pipeline analog-to-digital converter and capacitance mismatch error calibration method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110098836A (en) * | 2018-01-31 | 2019-08-06 | 长沙泰科阳微电子有限公司 | A kind of MDAC structure suitable for pipeline ADC |
| CN110098836B (en) * | 2018-01-31 | 2024-03-01 | 长沙泰科阳微电子有限公司 | MDAC structure suitable for assembly line ADC |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101484334B1 (en) | Common-mode insensitive sampler | |
| CN102098048B (en) | Switched-capacitor input circuit and analog-to-digital converter including the same | |
| CN109085422B (en) | High-precision synchronous acquisition system and method for monomer current of parallel power battery pack | |
| CN109120268A (en) | A kind of dynamic comparer offset voltage calibration method | |
| CN101764612A (en) | Multi-stage comparator | |
| CN102751956B (en) | Switched capacitor common-mode feedback structure | |
| CN102098049A (en) | Switched-capacitor input circuit and analog-to-digital converter including the same | |
| CN101227190A (en) | Capacitor averaging converter | |
| CN106124840A (en) | Current detection circuit | |
| CN102893528A (en) | Sample-and-hold circuit and a/d conversion device | |
| WO2016138806A1 (en) | Method for using current dac to eliminate dc offset in variable-gain amplifier circuit | |
| EP2437268B1 (en) | Single-ended to differential buffer circuit and method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs | |
| CN108021172A (en) | A kind of high bandwidth input isolation sampling and precision calibration circuit and method | |
| CN111983316B (en) | ISO detection method and device | |
| CN106680690B (en) | Clock driving method for single-ended input and differential output applied to ATE (automatic test equipment) test | |
| CN109212448B (en) | Self-stabilizing zero circuit | |
| CN106230438A (en) | A kind of capacitance mismatch for production line analog-digital converter tests System and method for | |
| CN102324940B (en) | Multiplication-type A/D (Analog/Digital) converter capable of correcting limited gain error | |
| US10425097B2 (en) | Sample-and-hold amplifier with switchable candidate capacitors | |
| US10530381B2 (en) | Operational amplifier with switchable candidate capacitors | |
| US10536160B2 (en) | Pipelined analog-to-digital converter having operational amplifier shared by different circuit stages | |
| CN113791331B (en) | Input signal amplitude detection circuit with adjustable output signal range and method thereof | |
| CN103281081A (en) | Capacitive-digital switching circuit based on sigma-delta modulator | |
| CN114839580A (en) | Common mode voltage calibration method | |
| CN205608161U (en) | Be applied to full difference mould data acquisition appearance and converting circuit of battery monitoring chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161214 |