CN106226715A - Resonance digital receives system - Google Patents
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Abstract
磁共振数字接收系统,涉及磁共振数字信号处理。设有磁共振接收线圈、前置放大器、模数转换器、抽取滤波器、混频器、频率合成器、CIC滤波器、FIR滤波器、补偿滤波器、FPGA、存储器、上位机;磁共振接收线圈依次与前置放大器、模数转换器、抽取滤波器相连,抽取滤波器的输出端分别与第一、第二混频器的输入端相连,频率合成器的输出端分别与第一、第二混频器的输入端相连,第一混频器的输出端依次与第一CIC滤波器、第一FIR滤波器和第一补偿滤波器的输入端相连,第二混频器的输出端依次与第二CIC滤波器、第二FIR滤波器和第二补偿滤波器的输入端相连,第一、第二补偿滤波器的输出端分别与FPGA相连。
A magnetic resonance digital receiving system relates to magnetic resonance digital signal processing. It is equipped with magnetic resonance receiving coil, preamplifier, analog-to-digital converter, decimation filter, mixer, frequency synthesizer, CIC filter, FIR filter, compensation filter, FPGA, memory, host computer; magnetic resonance receiving The coil is connected to the preamplifier, the analog-to-digital converter, and the decimation filter in turn, the output terminals of the decimation filter are respectively connected to the input terminals of the first and second mixers, and the output terminals of the frequency synthesizer are respectively connected to the first and second mixers. The input terminals of the two mixers are connected, the output terminals of the first mixer are connected with the input terminals of the first CIC filter, the first FIR filter and the first compensation filter successively, and the output terminals of the second mixer are successively connected. It is connected with the input terminals of the second CIC filter, the second FIR filter and the second compensation filter, and the output terminals of the first and second compensation filters are respectively connected with FPGA.
Description
技术领域technical field
本发明涉及磁共振数字信号处理,尤其是涉及一种磁共振数字接收系统。The invention relates to magnetic resonance digital signal processing, in particular to a magnetic resonance digital receiving system.
背景技术Background technique
随着软件无线电技术的发展和成熟,软件无线电技术正在被应用于磁共振数字信号处理领域。磁共振数字接收机常采用基于软件无线电中频数字化原理的数字中频接收机结构,FID(自由感应衰减)射频信号由磁共振接收线圈接收,经由模数转换器重采样过后转换为数字信号,再进行数字正交解调,并经过抽取滤波处理,最终得到较低速率的FID数字信号。With the development and maturity of software radio technology, software radio technology is being applied in the field of magnetic resonance digital signal processing. Magnetic resonance digital receivers often adopt a digital intermediate frequency receiver structure based on the principle of software radio intermediate frequency digitization. The FID (free induction decay) radio frequency signal is received by the magnetic resonance receiving coil, converted into a digital signal after resampling by an analog-to-digital converter, and then digitalized. Orthogonal demodulation, and after decimation and filtering, the FID digital signal at a lower rate is finally obtained.
CIC(级联积分梳状)滤波器具有实现结构简单、适合高倍率抽取等特点,因而被广泛应用于磁共振接收机的抽取滤波领域。然而,为了更加有效地应用重采样技术以达到提高接收机信噪比的目的,尤其是在静磁场强度较高的应用场合中,此时CIC滤波器将工作在较高速率下(可高达数百兆Hz),这对器件的运算速度和稳定性提出了更高的要求;同时由于于CIC滤波器的积分器是位于抽取之前的结构,如此高速率的工作速度将使得积分器的运算负担增加,接收机的功耗随之增加。另外,传统的接收系统通常将用于数字下变频的混频器放置在模数转换器之后,在磁共振数字接收中应用重采样技术将会使得混频器工作在较高的频率下,对混频器的硬件工作稳定性造成压力,对混频器的性能提出了较高的要求。CIC (Cascaded Integral Comb) filter has the characteristics of simple structure and suitable for high-magnification decimation, so it is widely used in the field of decimation filtering of magnetic resonance receivers. However, in order to apply resampling technology more effectively to achieve the purpose of improving the signal-to-noise ratio of the receiver, especially in applications with high static magnetic field strength, the CIC filter will work at a higher rate (up to several Hundreds of megahertz), which puts forward higher requirements on the operation speed and stability of the device; at the same time, because the integrator of the CIC filter is located before the structure of the decimation, such a high-speed working speed will make the integrator's computing burden increases, the power consumption of the receiver increases accordingly. In addition, the traditional receiving system usually places the mixer for digital down-conversion after the analog-to-digital converter, and the application of resampling technology in magnetic resonance digital reception will make the mixer work at a higher frequency. The hardware stability of the mixer creates pressure, which puts forward higher requirements on the performance of the mixer.
中国专利CN103135079A公开一种磁共振信号的接收方法,将接收线圈阵列中的线圈单元划分为不同的线圈单元组;对每个线圈单元,建立载频与该线圈单元组中各线圈单元所接收信号之间的对应关系;根据所述对应关系,对该线圈单元组中所有线圈单元接收的信号进行低噪声放大、滤波及混频,得到承载在同一信道的各对应载频上的中频信号;对所述中频信号进行放大及滤波后,输出给模数转换单元进行数字化采样,得到数字域信号。Chinese patent CN103135079A discloses a method for receiving magnetic resonance signals. The coil units in the receiving coil array are divided into different coil unit groups; for each coil unit, the carrier frequency and the signal received by each coil unit in the coil unit group are established Correspondence between them; according to the correspondence, low-noise amplification, filtering and frequency mixing are performed on the signals received by all the coil units in the coil unit group to obtain intermediate frequency signals carried on respective corresponding carrier frequencies of the same channel; After the intermediate frequency signal is amplified and filtered, it is output to an analog-to-digital conversion unit for digital sampling to obtain a digital domain signal.
发明内容Contents of the invention
为了改善CIC滤波器应用在磁共振数字信号处理时存在的不足,本发明的目的在于提供一种磁共振数字接收系统。In order to improve the shortcomings of the application of CIC filters in the processing of magnetic resonance digital signals, the purpose of the present invention is to provide a magnetic resonance digital receiving system.
本发明设有磁共振接收线圈、前置放大器、模数转换器、多相分解改进的抽取滤波器、第一混频器、第二混频器、直接数字式频率合成器、第一CIC滤波器、第二CIC滤波器、第一FIR(有限长单位冲击响应)滤波器、第二FIR滤波器、第一补偿滤波器、第二补偿滤波器、FPGA(现场可编程门阵列)、存储器、上位机;The invention is provided with a magnetic resonance receiving coil, a preamplifier, an analog-to-digital converter, a decimation filter improved by polyphase decomposition, a first mixer, a second mixer, a direct digital frequency synthesizer, and a first CIC filter device, the second CIC filter, the first FIR (finite-length unit impulse response) filter, the second FIR filter, the first compensation filter, the second compensation filter, FPGA (field programmable gate array), memory, upper computer;
所述磁共振接收线圈的输出端与前置放大器的输入端相连,前置放大器的输出端与模数转换器的输入端相连,模数转换器的输出端与多相分解改进的抽取滤波器的输入端相连,多相分解改进的抽取滤波器的输出端分别与第一混频器的输入端和第二混频器的输入端相连,直接数字式频率合成器的输出端分别与第一混频器的输入端和第二混频器的输入端相连,第一混频器的输出端与第一CIC滤波器的输入端相连,第一CIC滤波器的输出端与第一FIR滤波器的输入端相连,第一FIR滤波器的输出端与第一补偿滤波器的输入端相连,第二混频器的输出端与第二CIC滤波器的输入端相连,第二CIC滤波器的输出端与第二FIR滤波器的输入端相连,第二FIR滤波器的输出端与第二补偿滤波器的输入端相连,第一补偿滤波器的输出端和第二补偿滤波器的输出端分别与FPGA的输入端相连,FPGA分别与上位机和存储器双向连接。The output end of the magnetic resonance receiving coil is connected to the input end of the preamplifier, the output end of the preamplifier is connected to the input end of the analog-to-digital converter, and the output end of the analog-to-digital converter is connected to the multiphase decomposition improved decimation filter The input end of the polyphase decomposition improved decimation filter is connected with the input end of the first mixer and the input end of the second mixer respectively, and the output end of the direct digital frequency synthesizer is connected with the first mixer respectively. The input terminal of the mixer is connected with the input terminal of the second mixer, the output terminal of the first mixer is connected with the input terminal of the first CIC filter, and the output terminal of the first CIC filter is connected with the first FIR filter The input end of the first FIR filter is connected to the input end of the first compensation filter, the output end of the second mixer is connected to the input end of the second CIC filter, and the output of the second CIC filter End is connected with the input end of the second FIR filter, the output end of the second FIR filter is connected with the input end of the second compensation filter, the output end of the first compensation filter and the output end of the second compensation filter are respectively connected with The input terminals of the FPGA are connected, and the FPGA is bidirectionally connected with the upper computer and the memory respectively.
所述前置放大器的输出端与模数转换器输入端之间可设有带通滤波器。A band-pass filter may be provided between the output end of the preamplifier and the input end of the analog-to-digital converter.
本发明采用了多相分解改进的抽取滤波器,将整体抽取滤波器的工作速度降低。又为了改善多相分解滤波器抽取倍率较低、滤波系数修改不灵活等缺点,同时充分发挥CIC滤波器实现结构简单、抽取倍率较高等优点,本发明采用了在多相分解改进的抽取滤波器与CIC滤波器相结合的结构。为了改善传统方法将用于数字下变频的混频器放置在模数转换器之后而存在的不足,本发明采用将混频器放置于多相分解改进的抽取滤波器之后,使得混频器远离模数转换器,从而缓解混频器压力,降低了混频器工作频率。本发明大大降低了磁共振数字接收系统的一些关键模块的工作频率,提高了实时处理能力,更有效地满足于高静磁场环境和高倍率重采样技术。The invention adopts the decimation filter improved by polyphase decomposition, and reduces the working speed of the whole decimation filter. In order to improve the disadvantages such as low polyphase decomposition filter decimation rate and inflexible filter coefficient modification, and give full play to the advantages of CIC filter with simple structure and high extraction rate, the present invention adopts the decimation filter improved in polyphase decomposition A structure combined with a CIC filter. In order to improve the shortcomings of the traditional method of placing the mixer for digital down-conversion after the analog-to-digital converter, the invention adopts the method of placing the mixer after the decimation filter improved by polyphase decomposition, so that the mixer is far away from the Analog-to-digital converters, thereby relieving the mixer pressure and reducing the mixer operating frequency. The invention greatly reduces the working frequency of some key modules of the magnetic resonance digital receiving system, improves the real-time processing capability, and satisfies the high static magnetic field environment and high-magnification resampling technology more effectively.
附图说明Description of drawings
图1为本发明实施例的组成框图。FIG. 1 is a composition block diagram of an embodiment of the present invention.
图2为多相分解改进的抽取滤波器的原理框图。Fig. 2 is the functional block diagram of the decimation filter improved by polyphase decomposition.
具体实施方式detailed description
参见图1,本发明设有磁共振接收线圈1、前置放大器2、模数转换器4、多相分解改进的抽取滤波器5、第一混频器6、第二混频器7、直接数字式频率合成器8、第一CIC滤波器9、第二CIC滤波器10、第一FIR(有限长单位冲击响应)滤波器11、第二FIR滤波器12、第一补偿滤波器13、第二补偿滤波器14、FPGA(现场可编程门阵列)15、存储器16、上位机17;Referring to Fig. 1, the present invention is provided with magnetic resonance receiving coil 1, preamplifier 2, analog-to-digital converter 4, polyphase decomposition improved decimation filter 5, first mixer 6, second mixer 7, direct Digital frequency synthesizer 8, the first CIC filter 9, the second CIC filter 10, the first FIR (finite length unit impulse response) filter 11, the second FIR filter 12, the first compensation filter 13, the first Two compensation filters 14, FPGA (Field Programmable Gate Array) 15, memory 16, upper computer 17;
所述磁共振接收线圈1接收磁共振射频信号输入,磁共振接收线圈1的输出端与前置放大器2的输入端相连,前置放大器2的输出端与模数转换器4的输入端相连,模数转换器4的输出端与多相分解改进的抽取滤波器5的输入端相连,多相分解改进的抽取滤波器5的输出端分别与第一混频器6的输入端和第二混频器7的输入端相连,直接数字式频率合成器8的输出端分别与第一混频器6的输入端和第二混频器7的输入端相连,第一混频器6的输出端与第一CIC滤波器9的输入端相连,第一CIC滤波器9的输出端与第一FIR滤波器11的输入端相连,第一FIR滤波器11的输出端与第一补偿滤波器13的输入端相连,第二混频器7的输出端与第二CIC滤波器10的输入端相连,第二CIC滤波器10的输出端与第二FIR滤波器12的输入端相连,第二FIR滤波器12的输出端与第二补偿滤波器14的输入端相连,第一补偿滤波器13的输出端和第二补偿滤波器14的输出端分别与FPGA 15的输入端相连,FPGA 15分别与上位机16和存储器17双向连接。The magnetic resonance receiving coil 1 receives the magnetic resonance radio frequency signal input, the output end of the magnetic resonance receiving coil 1 is connected to the input end of the preamplifier 2, and the output end of the preamplifier 2 is connected to the input end of the analog-to-digital converter 4, The output end of the analog-to-digital converter 4 is connected with the input end of the decimation filter 5 improved by polyphase decomposition, and the output end of the decimation filter 5 improved by polyphase decomposition is connected with the input end of the first mixer 6 and the second mixer respectively. The input terminal of the frequency converter 7 is connected, the output terminal of the direct digital frequency synthesizer 8 is connected with the input terminal of the first mixer 6 and the input terminal of the second mixer 7 respectively, and the output terminal of the first mixer 6 Be connected with the input end of the first CIC filter 9, the output end of the first CIC filter 9 is connected with the input end of the first FIR filter 11, the output end of the first FIR filter 11 is connected with the first compensation filter 13 The input end is connected, and the output end of the second mixer 7 is connected with the input end of the second CIC filter 10, and the output end of the second CIC filter 10 is connected with the input end of the second FIR filter 12, and the second FIR filter The output terminal of the device 12 is connected with the input terminal of the second compensation filter 14, the output terminal of the first compensation filter 13 and the output terminal of the second compensation filter 14 are connected with the input terminal of the FPGA 15 respectively, and the FPGA 15 is respectively connected with the upper Machine 16 and memory 17 are bidirectionally connected.
所述前置放大器2的输出端与模数转换器4输入端之间可设有带通滤波器3。A band-pass filter 3 may be provided between the output end of the preamplifier 2 and the input end of the analog-to-digital converter 4 .
在图1中,标记ssin(n)为第一混频器6的数字本振信号,标记scos(n)为第二混频器7的数字本振信号;I(n)为同相的FID数字基带信号,Q(n)为正交的FID数字基带信号。In Fig. 1, the mark s sin (n) is the digital local oscillator signal of the first mixer 6, and the mark s cos (n) is the digital local oscillator signal of the second mixer 7; I (n) is in-phase FID digital baseband signal, Q(n) is an orthogonal FID digital baseband signal.
本发明提出了一种磁共振数字接收系统。利用N阶CIC滤波器设计多相分解改进的抽取滤波器。传统的N阶CIC滤波器传递函数为:The invention proposes a magnetic resonance digital receiving system. A decimation filter improved by polyphase decomposition is designed by using N-order CIC filter. The traditional N-order CIC filter transfer function is:
H(z)=[(1-z-R)/(1-z-1)]N,H(z)=[(1-z- R )/(1-z -1 )] N ,
其中R为抽取因子。假设Where R is the extraction factor. suppose
R=2KM,R=2 K M,
其中K和M为正整数,则传递函数H(z)可分解为非递归部分Where K and M are positive integers, the transfer function H(z) can be decomposed into non-recursive parts
和递归部分and the recursive part
从表达式中可以容易看出,H1(z)是个抽取因子为2K的滤波器,为抽取因子为M的滤波器。先对递归部分做恒等变换,其结构相当于H2(z)级联上抽取因子为M的抽取器,其中It can be easily seen from the expression that H 1 (z) is a filter with a decimation factor of 2 K , is a filter with a decimation factor of M. recursive part first Do the identity transformation, its structure is equivalent to the decimator whose decimation factor is M on the H 2 (z) cascade, where
H2(z)=[(1-z-M)/(1-z-1)]N。H 2 (z)=[(1-z- M )/(1-z -1 )] N .
再对非递归部分H1(z)做多相分解得到Then do multiphase decomposition on the non-recursive part H 1 (z) to get
其中Ei(z)为第i(i=0,1,...,2K-1)条多相支路的多相成分,表达式为Where E i (z) is the polyphase component of the i (i=0,1,...,2 K -1) polyphase branch, the expression is
Ei(z)=(ai0+ai1z-1+...+ai(N-1)z1-N),E i (z)=(a i0 +a i1 z -1 +...+a i(N-1) z 1-N ),
其中系数aij(j=0,...,N-1)由N和K共同决定。从而得到2K条多相分解支路,第i条多相支路由一个延时单元z-i级联多相成分再级联上抽取因子为2K的抽取器。再对每条多相支路进行Nobel恒等变换,得到第i条多相支路的结构为由一个延时单元zi级联上抽取因子为2K的抽取器再级联多相成分Ei(z);而其中延时单元zi又可以采用在第i-1条支路延时的基础上级联上单位延时单元z-1的结构,因此延时单元zi都可以由单位延时单元z-1等价替换。将每一路的多相支路的结果通过一个累加器累加,其结果等价于经过多相分解后的非递归部分H1(z)。由此,将多相分解后的非递归部分级联上H2(z)再级联上抽取因子为M的抽取器,便可以得到多相分解改进的抽取滤波器结构,如图2所示。The coefficients a ij (j=0,...,N-1) are jointly determined by N and K. Thus, 2 K multiphase decomposition branches are obtained, and the i-th multiphase branch is cascaded with a delay unit z -i multiphase components A decimator with a decimation factor of 2K is then cascaded. Then perform Nobel identity transformation on each polyphase branch, and the structure of the i-th polyphase branch is obtained by cascading an decimator with a decimation factor of 2 K on a delay unit z i and then cascading the polyphase component E i (z); and wherein the delay unit z i can adopt the structure of the unit delay unit z- 1 cascaded on the basis of the delay of the i-1 branch, so the delay unit z i can be formed by the unit The delay unit z -1 is equivalently replaced. The result of each polyphase branch is accumulated through an accumulator, and the result is equivalent to the non-recursive part H 1 (z) after polyphase decomposition. Therefore, the non-recursive part after polyphase decomposition is cascaded to H 2 (z) and then cascaded to a decimator with a decimation factor of M to obtain an improved decimation filter structure for polyphase decomposition, as shown in Figure 2 .
下面描述接收系统完整的工作流程:The complete workflow of the receiving system is described below:
FID射频信号由磁共振接收线圈接收获得FID模拟中频信号,经过前置放大器放大至适合模数转换器采样的幅值。之后通过带通滤波器滤除带外噪声,再利用模数转换器对FID模拟中频信号进行L倍重采样(通常L大于2)得到FID数字中频信号,假设其采样速率Fs。之后将FID数字中频信号送入多相分解改进的抽取滤波器,抽取倍数为The FID radio frequency signal is received by the magnetic resonance receiving coil to obtain the FID analog intermediate frequency signal, which is amplified by the preamplifier to an amplitude suitable for sampling by the analog-to-digital converter. Afterwards, the out-of-band noise is filtered out by a band-pass filter, and then the analog-to-digital converter is used to resample the FID analog IF signal by L times (usually L is greater than 2) to obtain the FID digital IF signal, assuming its sampling rate F s . After that, the FID digital intermediate frequency signal is sent to the decimation filter improved by polyphase decomposition, and the decimation factor is
R=2KM,R=2 K M,
其中K和M为正整数,2K倍抽取由其多相分解后的非递归部分完成,M倍抽取由递归部分完成。Where K and M are positive integers, 2 K times extraction is completed by the non-recursive part after multiphase decomposition, and M times extraction is completed by the recursive part.
因为本磁共振数字接收系统采用数字正交解调技术,因此需要得到同相和正交两路FID数字基带信号。将经过多相分解改进的抽取滤波器抽取后的FID数字中频信号分成两路,分别输入到第一混频器和第二混频器,其中第一混频器用于数字下变频得到同相FID数字基带信号,第二混频器用于数字下变频得到正交FID数字基带信号。第一混频器和第二混频器的数字本振信号均由直接数字式频率合成器生成。从原理上,输入第一混频器的数字本振信号ssin(n)应当与磁共振数字发射系统的数字本振信号st(n)同频同相,而输入第二混频器的数字本振信号scos(n)应当与ssin(n)同频,相位相差90度。在本接收系统中,由于第一混频器和第二混频器位于多相分解改进的抽取滤波器之后,此处假设某次发射所需的模拟载波信号的频率为fc,则直接数字式频率合成器生成的数字本振信号为Because this magnetic resonance digital receiving system adopts digital quadrature demodulation technology, it is necessary to obtain two FID digital baseband signals of in-phase and quadrature. The FID digital intermediate frequency signal extracted by the decimation filter improved by polyphase decomposition is divided into two channels, which are respectively input to the first mixer and the second mixer, wherein the first mixer is used for digital down-conversion to obtain in-phase FID digital For the baseband signal, the second mixer is used for digital down-conversion to obtain an orthogonal FID digital baseband signal. Both the digital local oscillator signals of the first mixer and the second mixer are generated by a direct digital frequency synthesizer. In principle, the digital local oscillator signal s sin (n) input to the first mixer should be the same frequency and phase as the digital local oscillator signal s t (n) of the magnetic resonance digital transmission system, while the digital local oscillator signal input to the second mixer The local oscillator signal s cos (n) should be at the same frequency as s sin (n), but out of phase by 90 degrees. In this receiving system, since the first mixer and the second mixer are located after the polyphase decomposition improved decimation filter, it is assumed here that the frequency of the analog carrier signal required for a certain transmission is f c , then the direct digital The digital local oscillator signal generated by the type frequency synthesizer is
st(n)=sin(2πfcn),s t (n)=sin(2πf c n),
于是可得直接数字式频率合成器输入到第一混频器的数字本振信号为Therefore, the digital local oscillator signal input to the first mixer by the direct digital frequency synthesizer can be obtained as
ssin(n)=sin(2πfc2KMn/Fs),s sin (n) = sin(2πf c 2 K Mn/F s ),
直接数字式频率合成器输入到第二混频器的数字本振信号为The digital local oscillator signal input from the direct digital frequency synthesizer to the second mixer is
scos(n)=cos(2πfc2KMn/Fs)。s cos (n)=cos(2πf c 2 K Mn/F s ).
第一混频器输出速率为Fs/(2KM)的同相FID数字基带信号I1(n),第二混频器输出速率为Fs/(2KM)的正交FID数字基带信号Q1(n)。The first mixer outputs the in-phase FID digital baseband signal I 1 (n) with a rate of F s /(2 K M), and the second mixer outputs a quadrature FID digital baseband with a rate of F s /(2 K M) Signal Q 1 (n).
将I1(n)输入至第一CIC滤波器进行第二级抽取,抽取倍数为D,抽取后的信号送入第一FIR滤波器消除多余的频率成分,之后再输入到第一补偿滤波器,以修正由于前两级抽取滤波器通带不平坦产生的幅值失真;最终输出同相的FID数字基带信号I(n),其速率为Fs/(2KMD)。将Q1(n)输入至第二CIC滤波器进行第二级抽取,抽取倍数为D,抽取后的信号送入第二FIR滤波器消除多余的频率成分,之后再输入到第二补偿滤波器,以修正由于前两级抽取滤波器通带不平坦产生的幅值失真;最终输出正交的FID数字基带信号Q(n),其速率为Fs/(2KMD)。将I(n)和Q(n)信号并行输入至FPGA,由FPGA进行第三次抽取滤波、K空间重构、压缩编码、与向上位机传输FID数据等一系列信号处理。同时FPGA将压缩编码后的同相FID数字基带信号和正交的FID数字基带信号存储在存储器内,以便于此后操作员多次重复读取FID数据信息。Input I 1 (n) to the first CIC filter for second-stage decimation, the decimation factor is D, and the extracted signal is sent to the first FIR filter to eliminate redundant frequency components, and then input to the first compensation filter , to correct the amplitude distortion caused by the uneven passband of the first two stages of decimation filters; finally output the in-phase FID digital baseband signal I(n), and its rate is F s /(2 K MD). Input Q 1 (n) to the second CIC filter for second-stage decimation, the decimation factor is D, and the extracted signal is sent to the second FIR filter to eliminate redundant frequency components, and then input to the second compensation filter , to correct the amplitude distortion caused by the uneven passband of the first two stages of decimation filters; the final output is the quadrature FID digital baseband signal Q(n), and its rate is F s /(2 K MD). The I(n) and Q(n) signals are input to the FPGA in parallel, and the FPGA performs a series of signal processing such as the third decimation filter, K space reconstruction, compression coding, and transmission of FID data to the upper computer. At the same time, the FPGA stores the compressed and encoded in-phase FID digital baseband signal and the quadrature FID digital baseband signal in the memory, so that the operator can repeatedly read the FID data information many times later.
本发明采用多相分解改进的抽取滤波器配合CIC滤波器的结构,将抽取的位置向前移动,从而缓解了CIC滤波器中积分器的压力,降低抽取硬件的速度性能要求。同时将混频器放置于多向分解改进的抽取滤波器之后,降低了混频器的工作频率。本发明大大降低了磁共振数字接收系统的一些关键模块的工作频率,提高了实时处理能力,更有效地满足于高静磁场环境和高倍率重采样技术。The invention adopts the polyphase decomposition improved decimation filter to cooperate with the structure of the CIC filter to move the position of decimation forward, thereby alleviating the pressure of the integrator in the CIC filter and reducing the speed performance requirement of the decimation hardware. At the same time, the mixer is placed after the decimation filter improved by multi-directional decomposition, which reduces the working frequency of the mixer. The invention greatly reduces the working frequency of some key modules of the magnetic resonance digital receiving system, improves the real-time processing capability, and satisfies the high static magnetic field environment and high-magnification resampling technology more effectively.
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