CN106206432A - Array base palte, the manufacture method of array base palte and display device - Google Patents
Array base palte, the manufacture method of array base palte and display device Download PDFInfo
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- CN106206432A CN106206432A CN201610676827.3A CN201610676827A CN106206432A CN 106206432 A CN106206432 A CN 106206432A CN 201610676827 A CN201610676827 A CN 201610676827A CN 106206432 A CN106206432 A CN 106206432A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 192
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 94
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 69
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 230000005540 biological transmission Effects 0.000 claims description 91
- 238000002834 transmittance Methods 0.000 claims description 41
- 238000002161 passivation Methods 0.000 claims description 28
- 230000002093 peripheral effect Effects 0.000 claims description 27
- 239000010408 film Substances 0.000 claims description 22
- 238000004380 ashing Methods 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 238000009413 insulation Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009738 saturating Methods 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of array base palte, the manufacture method of array base palte and display device, belong to Display Technique field.The method includes: form the via for connecting two metal levels on underlay substrate；Use mask plate, the underlay substrate be formed with this via is formed target electrode metal level, after making this target electrode metal level of formation, it is filled with photoresist in this via, thus reduce the degree of depth of via on this underlay substrate, improve the flatness on this array base palte surface, reduce the operation difficulty forming alignment film on array base palte surface.
Description
Technical field
The present invention relates to Display Technique field, particularly to a kind of array base palte, the manufacture method of array base palte and display
Device.
Background technology
Display panels generally comprise array base palte, color membrane substrates and be formed at this array base palte and color membrane substrates it
Between liquid crystal layer.
In correlation technique, in order to ensure that liquid crystal molecule along being correctly oriented arrangement, and can form certain tilt angle,
Need to form one layer of uniform alignment film at array base palte and color membrane substrates near the one side of liquid crystal layer respectively.
But, owing to the subregion on array base palte needs to form gate metal layer, gate insulation layer, active layer, source and drain
The thin film transistor (TFT) patterns such as pole metal level, wherein, gate metal layer includes that grid, source-drain electrode metal level include source electrode and drain electrode.
This source electrode needs to be connected with pixel electrode by via, and the grid in binding region (also referred to as bonding region) needs to pass through
Via is connected with drive circuit, and these vias make the surface irregularity of array base palte, increases and is formed on array base palte surface
The operation difficulty of alignment film, easily occurs that orientation is bad.
Summary of the invention
The problem that during in order to solve to form alignment film in correlation technique on array base palte surface, operation difficulty is bigger, the present invention
Provide a kind of array base palte, the manufacture method of array base palte and display device.Described technical scheme is as follows:
First aspect, it is provided that the manufacture method of a kind of array base palte, described method includes:
Underlay substrate is formed the via for connecting two metal levels；
Use mask plate, the underlay substrate being formed with described via is formed target electrode metal level, makes described in formation
After target electrode metal level, being filled with photoresist in described via, described mask plate includes transparency carrier, on described transparency carrier
Being formed with the transmission region that at least three light transmittance is different, the different transmission region of described at least three light transmittance includes that first is saturating
Light region and the second transmission region；
Wherein, the orthographic projection on described underlay substrate of described first transmission region and the binding district on described underlay substrate
In territory and non-via area, the region of target electrode metal level to be formed is overlapping, and described second transmission region is at described substrate base
Orthographic projection on plate is overlapping with the via region on described underlay substrate.
Optionally, described target electrode metal level includes: public electrode, the first overlap joint electrode and the second overlap joint electrode, its
In, described public electrode and described first overlap joint electrode are positioned at the viewing area on described underlay substrate, described second overlap joint electricity
Pole is positioned at the outer peripheral areas on described underlay substrate, the described via formed on underlay substrate for connecting two metal levels,
Including:
Forming thin film transistor (TFT) TFT and pixel electrode on underlay substrate, described TFT includes: grid, source electrode and drain electrode；
The underlay substrate being formed with TFT and pixel electrode is formed passivation layer；
The underlay substrate being formed with described passivation layer is formed the first via and the second via；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described lining
Outer peripheral areas on substrate, described first overlap joint electrode is for connecting described pixel electrode and described by described first via
Source electrode, described second overlap joint electrode is used for connecting described grid and described source electrode by described second via, or, described second
Overlap joint electrode is for connecting described grid and described drain electrode by described second via.
Optionally, described target electrode metal level includes: pixel electrode and the 3rd overlap joint electrode, described pixel electrode is positioned at
Viewing area on described underlay substrate, described 3rd overlap joint electrode is positioned at the outer peripheral areas on described underlay substrate, described
The via for connecting two metal levels is formed on underlay substrate, including:
Forming TFT and public electrode on underlay substrate, described TFT includes: grid, source electrode and drain electrode；
The underlay substrate being formed with TFT and public electrode is formed passivation layer；
The underlay substrate being formed with described passivation layer is formed the first via and the second via；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described lining
Outer peripheral areas on substrate, described first via is used for connecting described pixel electrode and described source electrode, described 3rd overlap joint electricity
Pole is used for connecting described grid and described source electrode by described second via, or, described 3rd overlap joint electrode is for by institute
State the second via and connect described grid and described drain electrode.
Optionally, described employing mask plate, the underlay substrate being formed with described via is formed target electrode metal level,
Including:
The underlay substrate being formed with described via coats conductive film；
Use described mask plate, described conductive film is passed sequentially through photoresist and applies, expose, develop, etch and photoetching
Glue ashing operation forms described target electrode metal level.
Optionally, described transparency carrier is formed with three different transmission regions of light transmittance,
The light transmittance of described first transmission region is 50%；
The light transmittance of described second transmission region is 0, and described photoresist is positive photoresist, except institute on described transparency carrier
Stating the region outside the first transmission region and described second transmission region is full transmission region, the light transmittance of described full transmission region
It is 100%,
Or, the light transmittance of described second transmission region is 100%, and described photoresist is negative photoresist, described transparent
On substrate, the region in addition to described first transmission region and described second transmission region is light tight region, described light tight district
The light transmittance in territory is 0.
Optionally, the described mask plate of described employing, described conductive film is passed sequentially through photoresist apply, expose, develop,
Etching and photoresist ashing operation form described target electrode metal level, including:
Use described mask plate, described conductive film is passed sequentially through photoresist apply, expose, develop, wet etching and
Photoresist ashing operation forms described target electrode metal level.
Second aspect, it is provided that a kind of array base palte, described array base palte includes: underlay substrate；
The via for connecting two metal levels it is formed with on described underlay substrate；
It is formed on the underlay substrate of described via and is formed with target electrode metal level；It is filled with photoetching in described via
Glue.
Optionally, described target electrode metal level includes: the public electrode of the viewing area being positioned on described underlay substrate
Electrode, and the second overlap joint electrode of the outer peripheral areas being positioned on described underlay substrate is overlapped with first；
Being formed with TFT and pixel electrode on described underlay substrate, described TFT includes: grid, source electrode and drain electrode；
It is formed on the underlay substrate of described TFT and described pixel electrode and is formed with passivation layer；
Being formed on the underlay substrate of described passivation layer and be formed with described via, described via includes: the first via and
Two vias；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described lining
Outer peripheral areas on substrate, described first overlap joint electrode is for connecting described pixel electrode and described by described first via
Source electrode, described second overlap joint electrode is used for connecting described grid and described source electrode by described second via, or, described second
Overlap joint electrode is for connecting described grid and described drain electrode by described second via.
Optionally, described target electrode metal level includes: the pixel electrode of the viewing area being positioned on described underlay substrate,
And the 3rd overlap joint electrode of the outer peripheral areas being positioned on described underlay substrate；
Being formed with TFT and public electrode on described underlay substrate, described TFT includes: grid, source electrode and drain electrode；
It is formed on the underlay substrate of described TFT and described public electrode and is formed with passivation layer；
Being formed on the underlay substrate of described passivation layer and be formed with described via, described via includes: the first via and
Two vias；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described lining
Outer peripheral areas on substrate, described first via is used for connecting described pixel electrode and described source electrode, described 3rd overlap joint electricity
Pole is used for connecting described grid and described source electrode by described second via, or, described 3rd overlap joint electrode is for by institute
State the second via and connect described grid and described drain electrode.
The third aspect, it is provided that a kind of display device, described display device includes: the array base as described in second aspect
Plate.
Fourth aspect, it is provided that a kind of mask plate, described mask plate includes: transparency carrier；
Being formed with the transmission region that at least three light transmittance is different on described transparency carrier, described at least three light transmittance is not
Same transmission region includes the first transmission region and the second transmission region；
Described mask plate, for forming target electrode metal level on the underlay substrate be formed with via, makes the described mesh of formation
After mark electrode metal layer, in described via, it is filled with photoresist；
Wherein, the orthographic projection on described underlay substrate of described first transmission region and the binding district on described underlay substrate
In territory and non-via area, the region of target electrode metal level to be formed is overlapping, and described second transmission region is at described substrate base
Orthographic projection on plate is overlapping with the via region on described underlay substrate.
Optionally, described transparency carrier is formed with three different transmission regions of light transmittance,
The light transmittance of described first transmission region is 50%；
The light transmittance of described second transmission region is 0, and described photoresist is positive photoresist, except institute on described transparency carrier
Stating the region outside the first transmission region and described second transmission region is full transmission region, the light transmittance of described full transmission region
It is 100%,
Or, the light transmittance of described second transmission region is 100%, and described photoresist is negative photoresist, described transparent
On substrate, the region in addition to described first transmission region and described second transmission region is light tight region, described light tight district
The light transmittance in territory is 0.
The technical scheme that the embodiment of the present invention provides has the benefit that
The invention provides a kind of array base palte, the manufacture method of array base palte and display device, the method includes: at lining
The via for connecting two metal levels is formed on substrate；Use mask plate, shape on the underlay substrate be formed with this via
Become target electrode metal level, owing to including the transmission region that at least three light transmittance is different on this mask plate, and wherein this first
Transmission region orthographic projection on described underlay substrate treats shape in the binding region on this underlay substrate and non-via area
The region becoming target electrode metal level is overlapping, the orthographic projection on this underlay substrate of second transmission region and this via region
Overlap, after making this target electrode metal level of formation, can be filled with photoresist, thus improve this array base palte table in this via
The flatness in face, reduces the operation difficulty forming alignment film on array base palte surface.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below required for make
Accompanying drawing be briefly described, it should be apparent that, below describe in accompanying drawing be only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is the flow chart of the manufacture method of a kind of array base palte that the embodiment of the present invention provides；
Fig. 2-1 is a kind of via formed on underlay substrate for connecting two metal levels that the embodiment of the present invention provides
Flow chart；
Fig. 2-2 is that a kind of of embodiment of the present invention offer forms showing of TFT, pixel electrode and passivation layer on underlay substrate
It is intended to；
Fig. 2-3 is a kind of schematic diagram forming the first via on underlay substrate that the embodiment of the present invention provides；
Fig. 2-4 is a kind of schematic diagram forming the second via on underlay substrate that the embodiment of the present invention provides；
Fig. 2-5 is a kind of flow chart forming target electrode metal level on underlay substrate that the embodiment of the present invention provides；
Fig. 2-6 is a kind of schematic diagram using mask plate to be exposed operation that the embodiment of the present invention provides；
Fig. 2-7 is a kind of underlay substrate of embodiment of the present invention offer schematic diagram after etching procedure；
Fig. 2-8 be the embodiment of the present invention provide a kind of underlay substrate on viewing area after photoresist ashing operation
Schematic diagram；
Fig. 2-9 be the embodiment of the present invention provide a kind of underlay substrate on outer peripheral areas after photoresist ashing operation
Schematic diagram；
Fig. 2-10 is that the another kind that the embodiment of the present invention provides is formed for connecting two metal levels on underlay substrate
The flow chart of via；
Fig. 2-11 be the embodiment of the present invention provide another kind of underlay substrate on viewing area through photoresist ashing operation
After schematic diagram.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is the flow chart of the manufacture method of a kind of array base palte that the embodiment of the present invention provides, as it is shown in figure 1, the party
Method may include that
Step 101, on underlay substrate formed for connect two metal levels via.
Step 102, employing mask plate, form target electrode metal level on the underlay substrate be formed with this via, make shape
After becoming this target electrode metal level, in this via, it is filled with photoresist.
This mask plate includes transparency carrier, and this transparency carrier is formed the transmission region that at least three light transmittance is different,
The different transmission region of this at least three light transmittance includes the first transmission region and the second transmission region；Wherein, this first printing opacity
Region orthographic projection on this underlay substrate and target to be formed in the binding region on this underlay substrate and non-via area
The region of electrode metal layer is overlapping, this second transmission region orthographic projection on this underlay substrate and the via on this underlay substrate
Region is overlapping.
In sum, the invention provides the manufacture method of a kind of array base palte, due to by the method at underlay substrate
After upper formation target electrode metal level, this underlay substrate can be filled with photoetching in the via connecting two metal levels
Glue, thus improve the flatness on this array base palte surface, reduce the operation difficulty forming alignment film on array base palte surface.
In embodiments of the present invention, on the one hand, to use the senior super dimension field switch of high aperture (English: High
opening rate Advanced-Super Dimensional Switching；It is called for short: as a example by array base palte HADS), should
Target electrode metal level in array base palte may include that public electrode, first overlap joint electrode and second overlap joint electrode, wherein,
The viewing area that this public electrode and the first overlap joint electrode are positioned on underlay substrate, this second overlap joint electrode is positioned on underlay substrate
Outer peripheral areas, with reference to Fig. 2-1, above-mentioned steps 101 specifically may include that
Step 1011a, on underlay substrate, form TFT and pixel electrode.
In embodiments of the present invention, use the senior super dimension field switch of tradition (English: Advanced-Super
Dimensional Switching；It is called for short: when ADS) technique manufactures HADS array base palte, with reference to Fig. 2-2, can be at substrate base
Pixel electrode 11, grid 12, gate insulation layer 13, active layer 14, source electrode 15 and drain electrode 16, wherein, source is first sequentially formed on plate 10
Pole 15 and drain electrode 16 can be formed by a patterning step, and this grid 12, source electrode 15 and drain electrode 16 can form one
TFT。
Step 1012a, on the underlay substrate being formed with TFT and pixel electrode formed passivation layer.
With reference to Fig. 2-2, one layer of passivation layer can be formed on the underlay substrate 10 be formed with TFT and pixel electrode 11 again
17。
Step 1013a, on the underlay substrate be formed with this passivation layer, form the first via and the second via.
In embodiments of the present invention, in order to realize the electrical connection of pixel electrode and source electrode in viewing area, and external zones
The connection (that is to say, source electrode or drain electrode are connected with grid cabling) of territory inner grid and source electrode or grid and drain electrode, in addition it is also necessary to
The underlay substrate be formed with this passivation layer is formed the first via for connecting pixel electrode and source electrode, and is used for connecting
Grid and source electrode or grid and the second via of drain electrode, wherein, this is used for connecting grid and source electrode or grid and drain electrode
Second via is referred to as transfer hole.
Example, Fig. 2-3 is the sectional view of underlay substrate viewing area, and as Figure 2-3,17a is permissible for this first via
Being positioned at the viewing area on this underlay substrate 10, the first overlap joint electrode in this target electrode metal level can be by this first mistake
Hole 17a connects this pixel electrode 11 and this source electrode 15, it can be seen that owing to needing the picture of source electrode 15 with bottom from Fig. 2-3
Element electrode 11 connects, and therefore this first via 17a needs through passivation layer 17 and gate insulation layer 13, and this first via 17a's is deep
Degree is relatively deep, technology difficulty when forming alignment film has been significantly greatly increased, has easily occurred that orientation is bad.
Fig. 2-4 is the sectional view of underlay substrate outer peripheral areas, and as in Figure 2-4, this second via 17b may be located at this lining
Outer peripheral areas on substrate 10, this second via 17b is used for connecting this grid 12 and this source electrode 15, or, it is used for connecting grid
Pole 12 and drain electrode, owing to being formed without TFT in outer peripheral areas, therefore the electrode 15 in this Fig. 2-4 can be that source electrode can also be
Drain electrode.The second overlap joint electrode in this target electrode metal level can connect this grid and source-drain electrode by this second via 17b.
Further, above-mentioned steps 102 can be performed: at the underlay substrate 10 being formed with this first via and the second via
Upper formation target electrode metal level, for using the array base palte of HADS technology, this target electrode metal level can include public
Electrode, the first overlap joint electrode and the second overlap joint electrode.Concrete, as shown in Figure 2-5, above-mentioned steps 102 specifically may include that
Step 1021, on the underlay substrate be formed with this via coat conductive film.
With reference to Fig. 2-6, can be 700 by magnetron sputtering apparatus plating thickness on the underlay substrate 10 being formed with via
The transparent conductive film 18 of angstrom (A), such as tin indium oxide ito thin film.
Step 1022, employing mask plate, pass sequentially through photoresist and apply, expose, develop, etch and light this conductive film
Photoresist ashing operation forms this target electrode metal level.
Use mask plate apply by photoresist, expose, develop, etch and the formation target electrode of the operation such as photoresist ashing
During metal level, with reference to Fig. 2-6, need first to be formed with on the underlay substrate 10 of conductive film 18 coating photoresist 19 at this, then
Use mask plate 20 that this photoresist 19 is exposed.
Mask plate 20 from Fig. 2-6 it can be seen that employed in the embodiment of the present invention includes transparency carrier 21, and this is transparent
Three different transmission regions of light transmittance it are formed with: 22,23 and 24 on substrate 21, wherein, the light transmittance of the first transmission region 22
It is 50%, the orthographic projection on this underlay substrate 10 of this first transmission region 22 and the binding region on this underlay substrate
In (bonding region) and non-via area, the region of target electrode metal level to be formed is overlapping.This bonding region is positioned at
The periphery of this array base palte, is provided with the via for connecting grid cabling and drive circuit in this bonding region；When this lining
When on substrate, the photoresist of coating is positive photoresist, the light transmittance of this second transmission region 23 can be 0, this second printing opacity
The region 23 orthographic projection on this underlay substrate 10 with the via on this underlay substrate (i.e. for being connected pixel electrode and source electrode
First via, and be used for connecting grid and source electrode, or grid and the second via of drain electrode) region is overlapping.With reference to figure
2-6, on this transparency carrier 21, the region in addition to this first transmission region 22 and this second transmission region 23 is full transmission region
24, the light transmittance of this full transmission region 24 is 100%.
After using mask plate 20 that the photoresist 19 on this underlay substrate 10 is exposed, this photoresist can be carried out development behaviour
Make, owing in this mask plate 20, the light transmittance of the first transmission region is 50%, higher than the second transmission region, in developing process,
Part photoresist corresponding to the first transmission region can be dissolved by the developing, and corresponds to the photoresist of the second transmission region the most not
Can dissolve, therefore after developing procedure, with reference to Fig. 2-7, corresponding to the first transmission region (mesh to be formed in the most non-via area
The mark region of electrode metal layer and bonding region) the thinner thickness of photoresist 192, and corresponding to the second transmission region
The thickness of the photoresist 191 of (i.e. via region) is thicker.
After developing procedure completes, initially with the operation of wet etching, to transparent conductive film the most covered by photoresist
18 perform etching, and are then ashed the photoresist 19 on underlay substrate 10 so that corresponding to the light of the first transmission region 22
Photoresist is completely removed, to form this target electrode metal level；And due to corresponding to the second transmission region 23 (i.e. via location
Territory) photoresist thickness thicker, after photoresist ashing operation, the photoresist in this region also have part residual, therefore, can
So that this via being used for connecting source electrode and pixel electrode, and it is filled with one in the via connecting grid and source-drain electrode
Determine the photoresist of thickness, rather than the gate metal cabling in target electrode metal level in via area and bonding region is then
Can be completely exposed.
With reference to Fig. 2-8, the viewing area on underlay substrate is after above-mentioned photoresist ashing operation, and this is formed with via
The target electrode metal level formed on underlay substrate 10 includes public electrode 18a and first overlap joint electrode 18b, and this public electrode
18a does not electrically connects with this first overlap joint electrode 18b, and this public electrode 18a can be multiple strip electrode, this first overlap joint electrode
18b is connected with this pixel electrode 11 by this first via 17a, thus realizes connecting pixel electrode 11 and the effect of source electrode 15.
With reference to Fig. 2-9, the outer peripheral areas on underlay substrate is after above-mentioned photoresist ashing operation, and this is formed with the underlay substrate of via
This target electrode metal level formed on 10 also includes the second overlap joint electrode 18c, this second overlap joint electrode 18c by this second
Via 17b is connected with grid 12 and source electrode 15 respectively, thus realizes connecting grid 12 and the effect of source electrode 15.
Further, from Fig. 2-8 and Fig. 2-9 it can be seen that after forming this target electrode metal level, in the first via 17a with
And second via 17b be also filled with certain thickness photoresist 19a, thus effectively reduce this first via 17a and the second mistake
The degree of depth of hole 17b, improves the flatness on this array base palte surface.
If it should be noted that the photoresist of coating is negative photoresist on this underlay substrate, then this second transmission region
Light transmittance can be 100%, on this transparency carrier, the region in addition to this first transmission region and this second transmission region can
Thinking light tight region, the light transmittance in this light tight region is 0.
Also, it should be noted understand, due to the via on this underlay substrate 10 with reference to Fig. 2-6, Fig. 2-8 and Fig. 2-9
It is likely in region be formed in partial target electrode metal layer, such as Fig. 2-8, a part of the second overlap joint electrode 18b
It is positioned at this first via 17a, therefore, when this via region is also formed with target electrode metal level, passes through mask
When plate forms this target electrode metal level, the first transmission region of this mask plate orthographic projection needs on underlay substrate and substrate
Binding region on substrate, and on underlay substrate, in non-via area, the region of target electrode metal level to be formed is overlapping, because of
This, this underlay substrate is after photoresist ashing operation, and the top of the target electrode metal level being positioned at via area also covers
There is photoresist.
In embodiments of the present invention, on the other hand, as a example by the array base palte using ADS technique, this target electrode metal
Layer may include that pixel electrode and the 3rd overlap joint electrode, and wherein, this pixel electrode is positioned at the viewing area on underlay substrate, should
The outer peripheral areas that 3rd overlap joint electrode is positioned on underlay substrate, with reference to Fig. 2-10, above-mentioned steps 101 specifically may include that
Step 1011b, on underlay substrate, form TFT and public electrode.
With reference to above-mentioned steps 1011a and Fig. 2-11, the electrode 11 now formed on this underlay substrate 10 can be public
Electrode.
Step 1012b, on the underlay substrate being formed with TFT and public electrode formed passivation layer.
The process that implements of step 1012b is referred to above-mentioned steps 1012a.
Step 1013b, on the underlay substrate be formed with this passivation layer, form the first via and the second via.
Understand with reference to Fig. 2-11, owing to, in the array base palte of employing ADS technique, public electrode is positioned at bottom, pixel electrode
Be positioned at top layer, therefore when being formed for connecting the first via 17a of source electrode 15 and pixel electrode 18d, this first via 17a without
Gate insulation layer 13 need to be penetrated, compared to the array base palte of employing HADS technique, the first mistake in the array base palte of this employing ADS technique
The degree of depth in hole is shallower.
After forming this first via and the second via, above-mentioned steps 102 can be performed and form this target electrode metal
Layer, this target electrode metal level can include the 3rd overlap joint electricity in pixel electrode and the peripherally located region being positioned at viewing area
Pole.As shown in figs. 2-11, after forming this pixel electrode 18d, it is filled with photoresist 19a in this first via 17a, therefore reduces
The degree of depth of this first via 17a, improves the flatness on array base palte surface.
Wherein, such as Fig. 2-11, this first via 17a is positioned at the viewing area on this underlay substrate 10, and such as Fig. 2-9, this is years old
Two via 17b are positioned at the outer peripheral areas on this underlay substrate, and this first via 17a is used for connecting this pixel electrode 18d and this source
Pole 15, the 3rd overlap joint electrode 18c is used for connecting this grid 12 and this source electrode 15 by the second via 17b, or, connect this grid
Pole and this drain electrode.
In sum, the invention provides the manufacture method of a kind of array base palte, due to by the method at underlay substrate
After upper formation target electrode metal level, this underlay substrate can be filled with photoetching in the via connecting two metal levels
Glue, thus improve the flatness on this array base palte surface, reduce the operation difficulty forming alignment film on array base palte surface.
Embodiments providing a kind of array base palte, with reference to Fig. 2-8, Fig. 2-9 or Fig. 2-11, this array base palte is permissible
Including: underlay substrate 10.
It is formed with the via for connecting two metal levels on this underlay substrate 10, such as, Fig. 2-8 is used for connect source electrode
15 and the via 17a of pixel electrode 11；It is formed on the underlay substrate 10 of this via and is formed with target electrode metal level.With reference to figure
It is filled with photoresist 19a in 2-8, Fig. 2-9 and Fig. 2-11, the first via 17a and the second via 17b.
In sum, the invention provides a kind of array base palte, owing to forming target electrode metal level on underlay substrate
After, this underlay substrate can be filled with photoresist in the via connecting two metal levels, thus improve this array base
The flatness on plate surface, reduces the operation difficulty forming alignment film on array base palte surface.
In embodiments of the present invention, on the one hand, with reference to Fig. 2-8, this target electrode metal level may include that and is positioned at substrate base
The public electrode 18a of the viewing area on plate 10 and first overlap joint electrode 18b, with reference to Fig. 2-9, this target electrode metal level also may be used
To include the second overlap joint electrode 18c in peripherally located region.
Being formed with TFT and pixel electrode on this underlay substrate 10, this TFT includes: grid 12, source electrode 15 and drain electrode 16；Shape
Become to have and be formed with passivation layer 17 on the underlay substrate of this TFT and this pixel electrode 11；It is formed with the underlay substrate of this passivation layer 17
On be formed with this via, this via may include that the first via 17a and the second via (not shown in Fig. 2-8).
Wherein, with reference to Fig. 2-8 and Fig. 2-9, this first via 17a is positioned at the viewing area on this underlay substrate 10, and this is the years old
Two via 17b are positioned at the outer peripheral areas on this underlay substrate 10；This first overlap joint electrode 18b is for by this first via 17a
Connecting this pixel electrode 11 and this source electrode 15, this second overlap joint electrode 18c is for connecting this grid 12 by this second via 17b
With this source electrode 15, or, this second overlap joint electrode 18c for by this second via 17b connect this grid 12 and drain electrode.
On the other hand, with reference to Fig. 2-11, this target electrode metal level includes: be positioned at the picture of viewing area on underlay substrate 10
Element electrode 18d, and in Fig. 2-9, it is positioned at the 3rd overlap joint electrode 18c of outer peripheral areas on underlay substrate 10.
Being formed with TFT and public electrode 11 on this underlay substrate, this TFT includes: grid 12, source electrode 15 and drain electrode 16；Shape
Become to have and be formed with passivation layer 17 on the underlay substrate 10 of this TFT and this public electrode 11；It is formed with the underlay substrate of this passivation layer
Being formed with this via on 10, this via may include that the first via 17a and the second via (not shown in Fig. 2-11).
Wherein, this first via 17a is positioned at the viewing area on this underlay substrate 10, and this second via is positioned at this substrate base
Outer peripheral areas on plate, this first via 17a is used for connecting this pixel electrode 18d and this source electrode 15, and the 3rd overlap joint electrode is used
In connecting this grid and this source electrode by this second via, or, the 3rd overlap joint electrode is for connecting by this second via
This grid and this drain electrode.
In sum, the invention provides a kind of array base palte, owing to forming target electrode metal level on underlay substrate
After, this underlay substrate can be filled with photoresist in the via connecting two metal levels, thus improve this array base
The flatness on plate surface, reduces the operation difficulty forming alignment film on array base palte surface.
Embodiments provide a kind of display device, this display device may include that as Fig. 2-8, Fig. 2-9 or Fig. 2-
Array base palte shown in 11.This display device can be: liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display
Any product with display function or the parts such as device, notebook computer, DPF, navigator.
Further, the embodiment of the present invention additionally provides a kind of mask plate, and as shown in figures 2-6, this mask plate 20 can wrap
Include: transparency carrier 21.
Being formed with, on this transparency carrier 21, the transmission region that at least three light transmittance is different, this at least three light transmittance is different
Transmission region include the first transmission region 22 and the second transmission region 23.
This mask plate 20, for forming target electrode metal level on the underlay substrate 10 be formed with via, makes this mesh of formation
After mark electrode metal layer, in this via (the such as first via 17a), it is filled with photoresist 19a.
Wherein, the orthographic projection on this underlay substrate 10 of this first transmission region 22 and the binding district on this underlay substrate 10
In territory and non-via area, the region of target electrode metal level to be formed is overlapping, and this second transmission region 23 is at this underlay substrate
On orthographic projection (be used for being connected picture in viewing area on such as underlay substrate 10 with the via region on this underlay substrate 11
Element electrode and the via of source electrode) overlapping.
Optionally, as shown in figures 2-6, this transparency carrier 21 is formed with three different transmission regions of light transmittance: 22,23
With 24.
Wherein, the light transmittance of this first transmission region 22 is 50%；The light transmittance of this second transmission region 23 is 0, now,
The photoresist used when forming this target electrode metal level on underlay substrate is positive photoresist, and this transparency carrier 21 removes
Region outside this first transmission region 22 and this second transmission region 23 is full transmission region 24, this full transmission region 24 saturating
Light rate is 100%.
Or, the light transmittance of this first transmission region 22 is 50%, and the light transmittance of this second transmission region 23 is 100%,
Now, the photoresist used when forming this target electrode metal level on underlay substrate is negative photoresist, this transparency carrier
On 21, the region in addition to this first transmission region 22 and this second transmission region 23 is light tight region 24, this light tight region
The light transmittance of 24 is 0.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (10)
1. the manufacture method of an array base palte, it is characterised in that described method includes:
Underlay substrate is formed the via for connecting two metal levels；
Use mask plate, the underlay substrate being formed with described via is formed target electrode metal level, makes the described target of formation
After electrode metal layer, being filled with photoresist in described via, described mask plate includes transparency carrier, and described transparency carrier is formed
Having the transmission region that at least three light transmittance is different, the different transmission region of described at least three light transmittance includes the first transparent area
Territory and the second transmission region；
Wherein, the binding region on the orthographic projection on described underlay substrate of described first transmission region and described underlay substrate with
And the region of target electrode metal level to be formed is overlapping in non-via area, described second transmission region is on described underlay substrate
Orthographic projection overlapping with the via region on described underlay substrate.
Method the most according to claim 1, it is characterised in that described target electrode metal level includes: public electrode, first
Overlap joint electrode and the second overlap joint electrode, wherein, described public electrode and described first overlap joint electrode are positioned on described underlay substrate
Viewing area, described second overlap joint electrode is positioned at the outer peripheral areas on described underlay substrate, described is formed on underlay substrate
For connecting the via of two metal levels, including:
Forming thin film transistor (TFT) TFT and pixel electrode on underlay substrate, described TFT includes: grid, source electrode and drain electrode；
The underlay substrate being formed with TFT and pixel electrode is formed passivation layer；
The underlay substrate being formed with described passivation layer is formed the first via and the second via；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described substrate base
Outer peripheral areas on plate, described first overlap joint electrode is for connecting described pixel electrode and described source by described first via
Pole, described second overlap joint electrode is used for connecting described grid and described source electrode by described second via, or, described second takes
Receiving electrode is for connecting described grid and described drain electrode by described second via.
Method the most according to claim 1, it is characterised in that described target electrode metal level includes: pixel electrode and
Three overlap joint electrodes, described pixel electrode is positioned at the viewing area on described underlay substrate, and described 3rd overlap joint electrode is positioned at described
Outer peripheral areas on underlay substrate, the described via formed on underlay substrate for connecting two metal levels, including:
Forming TFT and public electrode on underlay substrate, described TFT includes: grid, source electrode and drain electrode；
The underlay substrate being formed with TFT and public electrode is formed passivation layer；
The underlay substrate being formed with described passivation layer is formed the first via and the second via；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described substrate base
Outer peripheral areas on plate, described first via is used for connecting described pixel electrode and described source electrode, and described 3rd overlap joint electrode is used
In connecting described grid and described source electrode by described second via, or, described 3rd overlap joint electrode is for by described the
Two vias connect described grid and described drain electrode.
Method the most according to claim 1, it is characterised in that described employing mask plate, at the lining being formed with described via
Target electrode metal level is formed on substrate, including:
The underlay substrate being formed with described via coats conductive film；
Use described mask plate, described conductive film is passed sequentially through photoresist and applies, expose, develop, etch and photoresist ash
Chemical industry sequence forms described target electrode metal level.
5. according to the arbitrary described method of Claims 1-4, it is characterised in that be formed with three printing opacities on described transparency carrier
The transmission region that rate is different,
The light transmittance of described first transmission region is 50%；
The light transmittance of described second transmission region is 0, and described photoresist is positive photoresist, except described the on described transparency carrier
Region outside one transmission region and described second transmission region is full transmission region, and the light transmittance of described full transmission region is
100%,
Or, the light transmittance of described second transmission region is 100%, and described photoresist is negative photoresist, described transparency carrier
Upper region in addition to described first transmission region and described second transmission region is light tight region, described light tight region
Light transmittance is 0.
Method the most according to claim 4, it is characterised in that the described mask plate of described employing, depends on described conductive film
Secondary applied by photoresist, expose, develop, etch and photoresist ashing operation forms described target electrode metal level, including:
Use described mask plate, described conductive film is passed sequentially through photoresist apply, expose, develop, wet etching and photoetching
Glue ashing operation forms described target electrode metal level.
7. an array base palte, it is characterised in that described array base palte includes:
Underlay substrate；
The via for connecting two metal levels it is formed with on described underlay substrate；
It is formed on the underlay substrate of described via and is formed with target electrode metal level；
It is filled with photoresist in described via.
Array base palte the most according to claim 7, it is characterised in that described target electrode metal level includes: be positioned at described
The public electrode of the viewing area on underlay substrate and the first overlap joint electrode, and it is positioned at the outer peripheral areas on described underlay substrate
Second overlap joint electrode；
Being formed with TFT and pixel electrode on described underlay substrate, described TFT includes: grid, source electrode and drain electrode；
It is formed on the underlay substrate of described TFT and described pixel electrode and is formed with passivation layer；
Being formed on the underlay substrate of described passivation layer and be formed with described via, described via includes: the first via and the second mistake
Hole；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described substrate base
Outer peripheral areas on plate, described first overlap joint electrode is for connecting described pixel electrode and described source by described first via
Pole, described second overlap joint electrode is used for connecting described grid and described source electrode by described second via, or, described second takes
Receiving electrode is for connecting described grid and described drain electrode by described second via.
Array base palte the most according to claim 7, it is characterised in that described target electrode metal level includes: be positioned at described
The pixel electrode of the viewing area on underlay substrate, and the 3rd overlap joint electricity of the outer peripheral areas being positioned on described underlay substrate
Pole；
Being formed with TFT and public electrode on described underlay substrate, described TFT includes: grid, source electrode and drain electrode；
It is formed on the underlay substrate of described TFT and described public electrode and is formed with passivation layer；
Being formed on the underlay substrate of described passivation layer and be formed with described via, described via includes: the first via and the second mistake
Hole；
Wherein, described first via is positioned at the viewing area on described underlay substrate, and described second via is positioned at described substrate base
Outer peripheral areas on plate, described first via is used for connecting described pixel electrode and described source electrode, and described 3rd overlap joint electrode is used
In connecting described grid and described source electrode by described second via, or, described 3rd overlap joint electrode is for by described the
Two vias connect described grid and described drain electrode.
10. a display device, it is characterised in that described display device includes: the array as described in claim 7 to 9 is arbitrary
Substrate.
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