CN106206301A - The forming method of MOS transistor - Google Patents
The forming method of MOS transistor Download PDFInfo
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- CN106206301A CN106206301A CN201510215853.1A CN201510215853A CN106206301A CN 106206301 A CN106206301 A CN 106206301A CN 201510215853 A CN201510215853 A CN 201510215853A CN 106206301 A CN106206301 A CN 106206301A
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Abstract
A kind of forming method of MOS transistor, including: Semiconductor substrate is provided；Form grid structure on the semiconductor substrate；Source electrode material layer and drain material layer is formed in the Semiconductor substrate of described grid structure both sides；Described Semiconductor substrate, grid structure, source electrode material layer and drain material layer are formed first medium layer；Expose the first source electrode through hole of source electrode material layer bottom being formed in described first medium layer and the first drain electrode through hole of drain material layer is exposed in bottom；Etching removes part source electrode material layer and the part drain material layer of the first drain electrode via bottoms of the first source electrode via bottoms；Remaining source electrode material layer and remaining drain material layer are formed metal silicide layer.The method using the present invention can reduce source-drain contact resistance and parasitic series resistance further, to improve the performance of the transistor being subsequently formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the forming method of MOS transistor.
Background technology
Along with IC integrated level constantly increases, device size is needed persistently to reduce by this example.But, device work
Make voltage sometimes to remain unchanged so that actual MOS device electric field intensity inside high constantly increases.High electric field brings
A series of integrity problems so that device performance degeneration.Such as, posting between MOS transistor source-drain area
Raw series resistance can make equivalent operation voltage decline.Especially, it is reduced to one when dimensions of semiconductor devices
When determining degree, source and drain dead resistance has exceeded channel resistance becomes the important composition of whole device equivalent resistance
Part.For this reason, it may be necessary to use metal silicide effectively reduce source-drain contact resistance and post on source-drain area
Raw series resistance, improves the device performance of MOS transistor with this.
Referring to figs. 1 to Fig. 5, in prior art, there is the p-type fin formula field effect transistor of metal silicide
Forming method is as follows:
With reference to Fig. 1 and Fig. 2, it is provided that Semiconductor substrate 10, described Semiconductor substrate 10 has fin 11.Tool
Body is as follows:
Described Semiconductor substrate 10 includes silicon substrate 101 and the position with the discrete bulge-structure of at least two
Insulating barrier 102 between bulge-structure, insulating barrier 102 is less than described bulge-structure.Higher than insulating barrier 102
Bulge-structure be fin 11.
Then, the grid structure 12 of fin 11 it is developed across.Wherein grid structure 12 includes grid oxide layer 121 He
It is positioned at the grid layer 122 on grid oxide layer 121.
Then, with reference to Fig. 3, formation side wall 13 around grid structure 12.With side wall 13 as mask,
Source electrode 14a and drain electrode 14b is formed in the fin 11 of grid structure 12 both sides.Afterwards, Semiconductor substrate 10,
Dielectric layer 15 is formed on grid structure 12, side wall 13.Source electrode through hole 16a and drain electrode is formed in dielectric layer 15
Through hole 16b.Wherein, source electrode 14a is exposed in the bottom of source electrode through hole 16a, and leakage is exposed in the bottom of drain electrode through hole 16b
Pole 14b.
Then, with reference to Fig. 4, on the source electrode 14a that the bottom of source electrode through hole 16a is exposed, at drain electrode through hole 16b
The drain electrode 14b that exposes of bottom on form titanium coating.Afterwards, titanium coating is made annealing treatment, point
Xing Cheng source metal silicide layer 17a and drain metal silicide layer 17b.
Then, with reference to Fig. 5, use tungsten metal filled source electrode through hole 16a and drain electrode through hole 16b, form source electrode
Contact plunger 18a and drain contact connector 18b.
The performance using the p-type fin formula field effect transistor of the method formation of prior art is the best.
Summary of the invention
The problem that the present invention solves is the p-type fin formula field effect transistor using the method for prior art to be formed
Performance the best.
For solving the problems referred to above, the present invention provides the forming method of a kind of MOS transistor, including:
Semiconductor substrate is provided；
Form grid structure on the semiconductor substrate；
Source electrode material layer and drain material layer is formed in the Semiconductor substrate of described grid structure both sides；
Described Semiconductor substrate, grid structure, source electrode material layer and drain material layer are formed first Jie
Matter layer；
First source electrode through hole and the end of described source electrode material layer is exposed bottom being formed in described first medium layer
The first drain electrode through hole of described drain material layer is exposed in portion；
Etching removes the part source electrode material layer of described first source electrode via bottoms and described first drain electrode through hole
The part drain material layer of bottom；
Remaining source electrode material layer and remaining drain material layer are formed metal silicide layer.
Optionally, before etching removes part source electrode material layer and part drain material layer, to described first
Source electrode material layer that source electrode via bottoms is exposed and the drain material layer that described first drain electrode via bottoms is exposed
Carry out amorphizing ion injection.
Optionally, the injection ionic type that described amorphizing ion injects be germanium, silicon, carbon, nitrogen and argon from
At least one in son.
Optionally, the injection ionic type that described amorphizing ion injects is germanium, and ion implantation energy is big
In being less than or equal to 7keV equal to 2keV, ion implantation dosage is more than or equal to 1E13atom/cm2And be less than
Equal to 1E15atom/cm2。
Optionally, the injection ionic type that described amorphizing ion injects is silicon, and ion implantation energy is big
In being less than or equal to 8keV equal to 2keV, ion implantation dosage is more than or equal to 1E13atom/cm2And be less than
Equal to 1E15atom/cm2。
Optionally, the injection ionic type that described amorphizing ion injects is carbon, and ion implantation energy is big
In being less than or equal to 22keV equal to 2keV, ion implantation dosage is more than or equal to 1E13atom/cm2And it is little
In equal to 1E15atom/cm2。
Optionally, etching removes part source electrode material layer and the first drain electrode through hole of the first source electrode via bottoms
After the part drain material layer of bottom, before forming metal silicide layer, also include remaining source electrode
Material layer and remaining drain material layer make annealing treatment.
Optionally, described in be annealed into laser annealing, the temperature of described annealing be more than or equal to 800 DEG C and
Less than or equal to 1200 DEG C.
Optionally, described etching is wet etching or dry etching.
Optionally, when described etching is wet etching, described wet etching agent is that Tetramethylammonium hydroxide is molten
Liquid.
Optionally, the degree of depth of part source electrode material layer and drain material layer is removed less than or equal to described decrystallized
The degree of depth of ion implanting.
Optionally, described transistor is PMOS, and described source electrode material layer and drain material layer include germanium silicon
Layer；Described transistor is NMOS, and described source electrode material layer and drain material layer include silicon carbide layer.
Optionally, after forming metal silicide layer, with the first drain electrode through hole in described first source electrode through hole
The full second dielectric layer of interior filling, described second dielectric layer is equal with described first medium layer.
Optionally, the second source electrode through hole, institute are formed in the second dielectric layer in described first source electrode through hole
State the second source electrode via bottoms and expose described metal silicide layer；
The second drain electrode through hole, described second leakage is formed in second dielectric layer in described first drain electrode through hole
Pole via bottoms exposes described metal silicide layer.
Optionally, described Semiconductor substrate has fin, and described grid structure is across described fin, and covers
Cover top and the sidewall of described fin；
Source electrode material layer and drain material layer is formed in the fin of described grid structure both sides.
Compared with prior art, technical scheme has the advantage that
Etching removes part source electrode material layer and the portion of the first drain electrode via bottoms of the first source electrode via bottoms
Point drain material layer, can increase formed the metal of metal silicide layer respectively with source electrode material layer, drain electrode
Contact area between material layer.So, on source electrode material layer formed metal silicide layer and leakage
The volume of the metal silicide layer formed on the material layer of pole can increase.Connect such that it is able to reduce source and drain further
Get an electric shock resistance and parasitic series resistance, to improve the performance of the transistor being subsequently formed.
Accompanying drawing explanation
Fig. 1 is the perspective view of the Semiconductor substrate being formed with grid structure of the prior art；
Fig. 2 is the cross-sectional view in AA direction along Fig. 1；
Fig. 3 to Fig. 5 is the p-type fin field effect crystal of the prior art formed after the step of Fig. 2
The section flowage structure schematic diagram of pipe；
Fig. 6 is the stereochemical structure of the Semiconductor substrate being formed with grid structure in the specific embodiment of the invention
Schematic diagram；
Fig. 7 is the cross-sectional view in BB direction along Fig. 6；
Fig. 8 to Figure 16 is the fin field effect of the specific embodiment of the present invention formed after the step of Fig. 7
Answer the section flowage structure schematic diagram of transistor.
Detailed description of the invention
Inventor finds the small volume of the metal silicide layer using the method for prior art to be formed, and reduces
Source-drain contact resistance and the poor effect of parasitic series resistance.
Below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Embodiment one
First, with reference to Fig. 6 and Fig. 7, it is provided that Semiconductor substrate 20, described Semiconductor substrate 20 has fin
Portion 21.
In the present embodiment, described Semiconductor substrate 20 includes the silicon with the discrete bulge-structure of at least two
Substrate 201 and the insulating barrier between bulge-structure 202, insulating barrier 202 is less than described bulge-structure.
It is fin 21 higher than the bulge-structure of insulating barrier 202.Wherein, the material of insulating barrier 202 is silicon oxide.
In other embodiments, described Semiconductor substrate can also be silicon-on-insulator substrate, described insulator
Upper silicon substrate includes bottom silicon layer, the insulating barrier being positioned on bottom silicon layer, the top silicon that is positioned on insulating barrier
Layer.Etching top silicon layer forms fin.
Specifically it is well known to those skilled in the art technology, does not repeats them here.
Then, with continued reference to Fig. 6 and Fig. 7, it is developed across the grid structure 22 of described fin 21.
In the present embodiment, described grid structure 22 includes gate dielectric layer 221 and is positioned at described gate dielectric layer 221
On grid layer 222.When the material of gate dielectric layer 221 is silicon oxide, the material of grid layer 222 is polysilicon.
When the material of gate dielectric layer 221 is high-k gate dielectric layer, the material of grid layer 222 is metal.Wherein, high k
The material of gate dielectric layer is HfO2、Al2O3、ZrO2, HfSiO, HfSiON, HfTaO and HfZrO.
The concrete forming method of grid structure 22 be those skilled in the art know technology.
Then, with continued reference to Fig. 8, the fin of grid structure 22 both sides is carried out LDD ion implanting and Halo
Ion implanting, afterwards, makes annealing treatment, formed LDD ion implanted region (not shown) and Halo from
Sub-injection region (not shown).
After LDD ion implanting and Halo ion implanting, the lattice at the top of fin 21 is impaired, is formed
Dislocation defects.
In the present embodiment, with continued reference to Fig. 8, after forming LDD ion implanted region and Halo ion implanted region,
Side wall 23 is formed around grid structure 22.
The method forming side wall 23 is well known to those skilled in the art technology, does not repeats them here.
After forming side wall 23, with reference to Fig. 9, the fin 21 with side wall 23 as mask, to side wall 23 both sides
Perform etching, form source electrode groove and drain recesses.Afterwards, in source electrode groove, full source electrode material is filled
Layer 24a, fills full drain material layer 24b in drain recesses.In the present embodiment, the fin being subsequently formed
The type of field-effect transistor is p-type, and the material of source electrode material layer 24a and drain material layer 24b is respectively
For germanium silicon layer under, silicon cap (Si cap) layer is at upper lamination.In other embodiments, the fin being subsequently formed
The type of formula field-effect transistor is N-type, and the material of described drain material layer and source electrode material layer is respectively
Silicon carbide layer under, silicon cap layer is at upper lamination.
Afterwards, source electrode material layer 24a and drain material layer 24b is carried out source and drain injection, is correspondingly formed source
Pole and drain electrode.
Then, with continued reference to Fig. 9, at Semiconductor substrate 20, grid structure 22, source electrode material layer 24a
With formation first medium layer 25 on drain material layer 24b.
The material of first medium layer 25 is silicon oxide, carborundum or silicon oxynitride.First medium layer 25 is also
Can be low-k materials or ultralow-k material film, the dielectric constant of described low-k materials be less than or equal to 3, described super
The dielectric constant of low-k materials is less than or equal to 2.7.The forming method of first medium layer 25 is deposition.Specifically
Can be high-density plasma (High Density Plasma, HDP) chemical gaseous phase deposition or height
Depth ratio fills out ditch technique (High Aspect Ratio Process, HARP) or flowing chemistry vapour deposition
(Flowable Chemical Vapor Deposition, FCVD).Use above-mentioned three kinds of method filling capacities
Relatively strong, first medium layer 25 consistency of formation is higher.Certainly, first medium layer 25 can also be
Other depositing operations well known to those skilled in the art, fall within protection scope of the present invention.
Then, with reference to Figure 10, first medium layer 25 forms patterned first mask layer (not shown),
Described patterned first mask layer defines the first source electrode through hole, the position of the first drain electrode through hole and size.
Afterwards, the first mask layer graphically changed is that first medium layer 25 is performed etching, at first medium by mask
The first source electrode through hole 26a and first drain electrode through hole 26b is formed in layer 25.The end of the first source electrode through hole 26a
Source electrode material layer 24a is exposed in portion, and drain material layer 24b is exposed in the bottom of the first drain electrode through hole 26b.
In the present embodiment, when the material of the grid layer 222 in grid structure 22 is aluminum, at first medium
On layer 25 patterned first mask layer be hard mask layer under, photoresist is at upper lamination.Described firmly cover
When film layer is single layer structure, for titanium nitride.In other embodiments, the material of hard mask layer can be nitridation
Boron, silicon nitride or titanium nitride.In other embodiments, hard mask layer can also be laminated construction, described firmly
Mask layer is any two-layer in boron nitride layer, silicon nitride layer or titanium nitride layer or three-decker.
In the present embodiment, hard mask layer is needed to cover grid layer 222 rather than directly use photoresist layer
Covering grid layer 222, reason is as follows:
Owing to the characteristic size of semiconductor device is more and more less, the thickness of photoresist layer is more and more thinner, directly
The photoresist layer graphically changed is mask when performing etching first medium layer 25, and relatively thin photoresist layer exists
First source electrode through hole, the first drain electrode through hole can be completely removed before being formed.Furthermore, in subsequent step,
Need to use oxygen that photoresist is carried out oxidation removal.If photoresist directly overlays the grid that material is aluminum
On pole layer 222, then remove during photoresist in ashing, oxygen can with reactive aluminum and make grid layer
222 aoxidize.
Etching forms the first source electrode through hole 26a, the method for the first drain electrode through hole 26b is that anisotropic dry is carved
Erosion.
It should be noted that the first source electrode through hole 26a, the first drain electrode through hole 26b that the present embodiment is formed are also
It not source electrode through hole and the drain electrode through hole of final size in the fin formula field effect transistor being subsequently formed.
The size of the first source electrode through hole 26a and first drain electrode through hole 26b is more than the source electrode through hole ultimately formed and leakage
The size of pole through hole.If using the first source electrode through hole 26a and first drain electrode through hole 26b as final size
Source electrode through hole and drain electrode through hole, then the source metal connector being correspondingly formed in subsequent process steps, drain electrode
Metal plug distance respectively and between grid structure is too near, and it is brilliant to affect the fin field effect being subsequently formed
The performance of body pipe.
Then, with continued reference to Figure 10, to the source electrode material layer 24a exposed bottom the first source electrode through hole 26a
Amorphizing ion injection is carried out with the drain material layer 24b exposed bottom the first drain electrode through hole 26b.
After amorphizing ion injects, the amorphizing ion being injected into can be at source electrode material layer 24a and drain electrode material
Bed of material 24b is diffused, in source electrode material layer 24a, forms the first amorphizing ion injection region respectively
27a, forms the second amorphizing ion injection region 27b in drain material layer 24b.First amorphizing ion
In source electrode material layer in the 27a of injection region and the second amorphizing ion injection region 27b, drain material layer is non-
Crystallization.The border of the first amorphizing ion injection region 27a and the second amorphizing ion injection region 27b is arc
Shape.
In the present embodiment, described amorphizing ion inject injection ionic type be germanium, silicon, carbon, nitrogen or
At least one in argon ion.
When the injection ionic type that described amorphizing ion injects is germanium, ion implantation energy is for being more than or equal to
4keV is less than or equal to 40keV, and ion implantation dosage is more than or equal to 1E13atom/cm2And be less than or equal to
1E15atom/cm2。
When the injection ionic type that described amorphizing ion injects is silicon, ion implantation energy is for being more than or equal to
2keV is less than or equal to 16keV, and ion implantation dosage is more than or equal to 1E13atom/cm2And be less than or equal to
1E15atom/cm2。
When the injection ionic type that described amorphizing ion injects is carbon, ion implantation energy is for being more than or equal to
2keV is less than or equal to 7keV, and ion implantation dosage is more than or equal to 1E13atom/cm2And be less than or equal to
1E15atom/cm2。
When the injection ionic type that described amorphizing ion injects is nitrogen, ion implantation energy is for being more than or equal to
2keV is less than or equal to 8keV, and ion implantation dosage is more than or equal to 1E13atom/cm2And be less than or equal to
1E15atom/cm2。
When the injection ionic type that described amorphizing ion injects is argon, ion implantation energy is for being more than or equal to
2keV is less than or equal to 22keV, and ion implantation dosage is more than or equal to 1E13atom/cm2And be less than or equal to
1E15atom/cm2。
In the present embodiment, if the ion implantation energy of amorphizing ion injection, implantation dosage are too big, meeting
Destroy the source electrode material layer 24a beyond the first amorphizing ion injection region 27a, the second amorphous can be destroyed equally
Change the drain material layer 24b beyond ion implanted region 27b, thus the fin field effect that impact is subsequently formed is brilliant
The performance of body pipe.If the ion implantation energy that amorphizing ion injects, implantation dosage are the least, it is impossible to have
The volume of the metal silicide that the expansion of effect is subsequently formed.
Then, with reference to Figure 11, etching removes the source electrode material layer in the first amorphizing ion injection region 27a
24a and etching remove the drain material layer 24b in the second amorphizing ion injection region 27b.
In the present embodiment, wet etching agent is used to remove the source electrode material of the first amorphizing ion injection region 27a
Bed of material 24a, forms the first groove 28a.The bottom of the first groove 28a is arc.Use wet etching agent
Remove the drain material layer 24b of the second amorphizing ion injection region 27b, form the second groove 28b.Second
The bottom of groove 28b is also arc.Wherein, wet etching agent be tetramethyl ammonium hydroxide solution (TMAH,
Tetramethy lammonium Hydroxide).Concentration is 2%～18%, and temperature is room temperature (23 DEG C
～30 DEG C).The TMAH solution of above-mentioned condition removes the source electrode material of the first amorphizing ion injection region 27a
The precision of the drain material layer 24b of layer 24a and removal the second amorphizing ion injection region 27b is higher,
The technique removing decrystallized source electrode material layer and drain material layer is more preferably controlled.
It should be understood that in prior art, the fin of grid structure 22 both sides is carried out LDD ion
Inject and during Halo ion implanting, serious lattice damage can be caused in the top of fin 21,
And, follow-up annealing operation also is difficult to repair the top lattice damage of fin 21.Reason is as follows:
For planar transistor, the damage that substrate surface is caused by LDD ion implanting and Halo ion implanting,
Follow-up annealing process can be repaired in time.Because this substrate interior has substantial amounts of monocrystal silicon,
Can spread during annealing and grow at impaired substrate.But, for fin field effect crystal
For pipe, the characteristic size of fin 21 is the least.Fin 21 top LDD ion implanting and Halo from
After son is impaired during injecting, the monocrystal silicon even if making annealing treatment accordingly, in silicon substrate 201
Extremely difficult to the top-direction repairing growth of fin along the bottom of bulge-structure, therefore, silicon substrate 201
In monocrystal silicon be difficult to repairing growth to the top of fin 21.So, in the formation position, top of fin 21
Wrong defect (Twin defect), the performance of the fin formula field effect transistor that impact is subsequently formed.
In the present embodiment, wet etching agent is used to remove the source electrode in the first amorphizing ion injection region 27a
After material layer 24a and etching remove the drain material layer 24b in the second amorphizing ion injection region 27b,
That is impaired fin top is removed, can eliminate dislocation defects, thus improve and be subsequently formed
The performance of fin formula field effect transistor.
In the present embodiment, control wet etching agent and remove the source electrode material of the first amorphizing ion injection region 27a
Bed of material 24a, the second amorphizing ion injection region 27b the thickness of drain material layer 24b more than zero and be less than
The 60% of the degree of depth is injected equal to described amorphizing ion.If the first amorphizing ion is removed in wet etching agent
The source electrode material layer 24a of injection region 27a, the drain material layer 24b of the second amorphizing ion injection region 27b
Thickness too deep, the pn-junction between each ion implanted region before amorphization implantation step can be destroyed, can shadow
Ring trench size.
Further, control wet etching agent and remove the source electrode material of the first amorphizing ion injection region 27a
Bed of material 24a, the second amorphizing ion injection region 27b the thickness of drain material layer 24b equal to described amorphous
Change the 60% of the ion implanting degree of depth.All right maximized elimination dislocation defects,
Then, with continued reference to Figure 11, by the remaining source electrode material in the first amorphizing ion injection region 27a
In the bed of material and the second amorphizing ion injection region 27b, remaining drain material layer makes annealing treatment.
In the present embodiment, acting as of annealing: by remaining in the first amorphizing ion injection region 27a
Remaining noncrystalline state in the source electrode material layer of remaining noncrystalline state and the second amorphizing ion injection region 27b
Drain material layer repair to original monocrystalline state.
In the present embodiment, make annealing treatment and process into laser annealing.Temperature is more than or equal to 800 DEG C and to be less than
In 1200 DEG C.Why select the annealing of above-mentioned condition, be possible not only to well to repair remaining non-
The source electrode material layer 24a of crystalline state and drain material layer 24b, and heat budget is minimum.
In other embodiments, wet etching agent is used to remove the source electrode of the first amorphizing ion injection region 27a
The thickness of the drain material layer 24b of material layer 24a and the second amorphizing ion injection region 27b is equal to described
The degree of depth that amorphizing ion injects, it is possible to omit above-mentioned Laser Annealing Process Steps.Fall within the present invention
Protection domain.But, the technique controlling wet etching so that remove the first amorphizing ion injection region
The thickness of the drain material layer 24b of the source electrode material layer 24a and the second amorphizing ion injection region 27b of 27a
The degree of depth being exactly equal to the injection of described amorphizing ion is the most difficult, and precision is hardly consistent with requiring.Therefore,
Not as first removing partial amorphization source electrode material layer 24a and partial amorphization drain material layer 24b, then will be surplus
Remaining decrystallized source electrode material layer and drain material layer carry out the technique repaired easily, convenient, save worry and
Laborsaving.
In other embodiments, it would however also be possible to employ dry etching removes the source electrode of the first amorphizing ion injection region
Material layer and the drain material layer of the second amorphizing ion injection region.But, relative to wet etching, dry
The method that method etching is removed is relatively fierce, easily to the source electrode material of monocrystalline beyond the first amorphizing ion injection region
Beyond the bed of material, the second amorphizing ion injection region, the drain material layer of monocrystalline causes major injury, even if adopting
It also is difficult to recover impaired source electrode material layer and drain material layer with follow-up laser annealing technique,
Re-form mono-crystalline structures.
In other embodiments, if not carrying out the step of amorphizing ion injection, and directly use other
Wet etching solution or use dry etching method source electrode material layer that the first source electrode via bottoms is exposed and
The drain material layer that first drain electrode via bottoms is exposed carries out part removal, falls within the protection model of the present invention
Enclose.And, the step that laser annealing processes can be omitted.It should be understood that due to not to first
Source electrode material layer that source electrode via bottoms is exposed and the drain material layer that the second source electrode via bottoms is exposed are carried out
Amorphisation, source electrode material layer and drain material layer remain as mono-crystalline structures, the first groove of formation and
The shape being shaped as non-arc of the second groove, and, it may appear that angled construction, not as the first groove and
The arcuate recess surface of the second groove is smooth.The fin formula field effect transistor being subsequently formed is applied electricity
During pressure, easily form voltage break-through.But, the performance of the fin formula field effect transistor of formation also ratio is existing
Technology is good.
Such as, if not carrying out the step of amorphizing ion injection, and Tetramethylammonium hydroxide is directly used
Source electrode material layer that first source electrode via bottoms is exposed by solution and the drain electrode that the first drain electrode via bottoms is exposed
Material layer carries out part removal, the first groove of formation and the second groove be shaped as hexangle type.Hexangle type
The groove of shape has the cutting-edge structures such as horn shape, be not as smooth as the first groove and second groove surfaces of arc
Smooth.
Then, be carried out the first groove and the second groove removing natural oxide (Native Oxide),
Granule (Particles) or metal ion.
Then, with reference to Figure 12, at first medium layer the 25, first source electrode through hole 26a sidewall, the first groove
28a surface, the first drain electrode through hole 26b sidewall, the second groove 28b surface form the first metal layer 29.
Figure 12 only illustrates at the first source electrode through hole 26a sidewall, the first groove 28a surface, the first leakage
Pole through hole 26b sidewall, the second groove 28b surface form the first metal layer 29.
In the present embodiment, the material of described the first metal layer 29 is titanium, forms the side of the first metal layer 29
Method is deposition or sputtering.
Then, the first metal layer 29 is carried out the first quick thermal annealing process (RTA).First short annealing
During process, the first metal layer is formed with the silicon cap layer fusion in source electrode material layer, drain material layer
High resistant phase metal silicide, the composition of this high resistant phase metal silicide is TiSi2。
Then, with reference to Figure 13, by first medium layer the 25, first source electrode through hole 26a sidewall, the first drain electrode
The high resistant phase metal silicide of through hole 26b sidewall and remaining first metal removal.
In the present embodiment, minimizing technology is removed for using APM solution or SPM solution.Wherein, APM
Solution is the mixed solution of ammonia and hydrogen peroxide.APM solution is the mixed solution of sulphuric acid and hydrogen peroxide.By
In, the hydrogen peroxide in APM solution or SPM solution exists and holds labile shortcoming, thus needs constantly
Change APM solution or SPM solution.It is therefore possible to use ozone substitutes APM solution or SPM is molten
Hydrogen peroxide in liquid.Wherein, the flow of ozone is 3～7L/min, and the time being passed through ozone is 6～8min.
In other embodiments, it is also possible to be passed through ozone in APM solution or SPM solution, at this moment, smelly
The flow of oxygen is 5L/min, and the time being passed through ozone is 60～100min.
In the present embodiment, the temperature of the first quick thermal annealing process is less than 500 DEG C, prevents the light on wafer
Photoresist melts, and can also form high resistant phase metal silicide.
Then, with reference to Figure 13, remaining the first metal layer 29 is carried out the second quick thermal annealing process, shape
Become low-resistance phase metal silicide layer.Wherein, low-resistance phase metal silicide layer is final metal silicide layer.
In the present embodiment, the temperature of the second quick thermal annealing process is less than 500 DEG C.Metal silicide layer
Composition is TiSi.Prevent the photoresist on wafer from melting, and high resistant phase metal silicide can also be formed.
During other are implemented, do not carry out the second quick thermal annealing process and fall within protection scope of the present invention.
In other embodiments, when the material of metal is nickel, platinum, platinum-nickel alloy or cobalt, it is also desirable to pass through
The step that first short annealing processes and the second short annealing processes, forms metal silicide layer.
Wherein, the metal silicide layer formed on source electrode material layer is source metal silicide layer 30a,
The metal silicide layer formed on drain material layer is drain metal silicide layer 30b.
Then, with reference to Figure 14, in the first source electrode through hole 26a and first drain electrode through hole 26a, full the is filled
Second medium layer 31, second dielectric layer 31 is equal with first medium layer 25.
In the present embodiment, the forming method of second dielectric layer 31 is: on first medium layer 25, source electrode
Second medium layer material layer is formed on metal silicide layer 30a, drain metal silicide layer 30b.Afterwards,
Second medium layer material layer higher than first medium layer 25 is gone by the method using cmp
Remove, form second dielectric layer 31.
Specifically refer to the forming method of first medium layer 25.
Then, with reference to Figure 15, the second source in the second dielectric layer 31 in the first source electrode through hole 26a, is formed
Pole through hole 32a, forms the second drain electrode through hole 32b in the second dielectric layer 31 in the first source electrode through hole 26b.
Wherein, the second source electrode through hole 32a and second drain electrode through hole 32b is the fin field effect being subsequently formed
The source electrode through hole of transistor final size and drain electrode through hole.Therefore, the second source electrode through hole 32a and second leakage
Pole through hole 32b is smaller in size than the first source electrode through hole 26a and the size of the first source electrode through hole 26b.
Concrete forming method is as follows:
First medium layer 25 and second dielectric layer 31 are formed patterned second mask layer, described figure
Second mask layer of shape defines the second source electrode through hole and the position of the second drain electrode through hole and size.Afterwards,
With described patterned second mask layer as mask, second dielectric layer 31 is performed etching.
Then, with reference to Figure 16, in the second source electrode through hole 32a and second drain electrode through hole 32b, full the is filled
Two metal levels, form source metal connector 33a on source electrode, form drain metal connector 33b in drain electrode.
In the present embodiment, the second metal level can be tungsten metal, and other metals can also be as the present invention's
Protection domain.
In prior art, with reference to Fig. 4, the source electrode through hole 16a formed in dielectric layer 15 and drain electrode through hole
16b is source electrode through hole and the drain electrode through hole of fin formula field effect transistor final size.This source electrode through hole 16a and
The size of drain electrode through hole 16b is less.Afterwards, corresponding with drain electrode through hole 16b at above-mentioned source electrode through hole 16a
Metal level is formed on the source electrode material layer 14a exposed and drain material layer 14b.Afterwards, metal level is entered
Row annealing is the formation of source metal silicide layer 17a and drain metal silicide layer 17b.It is visible,
This metal level can only contact with the source electrode material layer 14a that the source electrode through hole 16a of final size exposes, and connects
Contacting surface is long-pending can be little.The drain material layer 14b that this metal level can only expose with the drain electrode through hole 16a of final size
Contacting, contact area is the least.So, the source metal silicide layer 17a ultimately formed and drain electrode
The volume of metal silicide layer 17b is the least.
In the present embodiment, after amorphizing ion injects, injecting ion can the internal and drain electrode at source electrode material layer
Being diffused inside material layer, the removal volume for follow-up increase source electrode material layer and drain material layer does standard
Standby, so that the volume of the first groove and the second groove increases, and then make follow-up filling the first groove
The contact area of metal and source electrode material layer increase so that the metal of follow-up filling the second groove and drain electrode
The contact area of material layer increases.So, on source electrode material layer formed source metal silicide layer and
The volume of the drain metal silicide formed on drain material layer increases.Raising is conducive to be subsequently formed
The performance of fin formula field effect transistor.
It addition, just because of using amorphizing ion to inject, the first groove, the shape of the second groove can be made
For smooth arc, increasing source metal silicide layer and the situation of drain metal silicide layer volume
Under, it is also possible to the break-through of prevention voltage.
In other embodiments, if Semiconductor substrate does not have fin, fall within protection scope of the present invention.
Now, grid structure is not across on fin, say, that the method forming metal silicide is also applied for
Planar transistor.
Embodiment two
The present embodiment is with the difference of embodiment one: the first source electrode through hole and the first drain electrode through hole are follow-up
Source electrode through hole in the fin formula field effect transistor formed and drain electrode through hole.Then, first in the present embodiment
The first source electrode through hole and first that the size of source electrode through hole and the first drain electrode through hole is both less than in embodiment one leaks
The size of pole through hole.So, the formation second dielectric layer in embodiment one, formation in second dielectric layer
The step of the second source electrode through hole and the second drain electrode through hole can be omitted.Afterwards, directly at the first source electrode through hole
Fill full second metal level with the first drain electrode through hole, form metal plug.
In the present embodiment, for mask, source electrode material layer is carried out amorphizing ion injection with the first source electrode through hole,
The scope of the first amorphizing ion injection region formed is injected less than the first amorphizing ion in embodiment one
The scope in district.Afterwards, the volume of the first groove of formation is less than the volume of the first groove in embodiment one,
So, the source metal silicide layer formed on source electrode material layer is less than the source metal in embodiment one
Silicide layer.But, bigger than the volume in source metal silicide of the prior art.
In the present embodiment, for mask, drain material layer is carried out amorphizing ion injection with the first drain electrode through hole,
The scope of the second amorphizing ion injection region formed is injected less than the second amorphizing ion in embodiment one
The scope in district.Afterwards, the volume of the second groove of formation is less than the volume of the second groove in embodiment one,
So, the drain metal silicide layer formed on drain material layer is less than the drain metal in embodiment one
Silicide layer.But, bigger than the volume in drain metal silicide of the prior art.
If it should be noted that the first source electrode through hole in embodiment one and the size of the second source electrode through hole
Size according to the fin formula field effect transistor being subsequently formed accomplishes maximum.So, according in embodiment one
Amorphizing ion inject condition, remove the condition of source electrode material layer in the first amorphizing ion injection region,
Remove in the first amorphizing ion injection region that the condition of the condition of drain material layer, annealing etc. is common to be made
With, so that formed on the source metal silicide layer formed on source electrode material layer, drain material layer
The volume maximization of drain metal silicide layer.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (15)
1. the forming method of a MOS transistor, it is characterised in that including:
Semiconductor substrate is provided；
Form grid structure on the semiconductor substrate；
Source electrode material layer and drain material layer is formed in the Semiconductor substrate of described grid structure both sides；
Described Semiconductor substrate, grid structure, source electrode material layer and drain material layer are formed first medium
Layer；
The first source electrode through hole and bottom of described source electrode material layer is exposed bottom being formed in described first medium layer
Expose the first drain electrode through hole of described drain material layer；
Etching is removed at the bottom of part source electrode material layer and the described first drain electrode through hole of described first source electrode via bottoms
The part drain material layer in portion；
Remaining source electrode material layer and remaining drain material layer are formed metal silicide layer.
2. the forming method of transistor as claimed in claim 1, it is characterised in that etching removes part source electrode
Before material layer and part drain material layer, the source electrode material that described first source electrode via bottoms is exposed
The drain material layer that layer and described first drain electrode via bottoms are exposed carries out amorphizing ion injection.
3. the forming method of transistor as claimed in claim 1, it is characterised in that described amorphizing ion is noted
The ionic type that injects entered is at least one in germanium, silicon, carbon, nitrogen and argon ion.
4. the forming method of transistor as claimed in claim 3, it is characterised in that described amorphizing ion is noted
The injection ionic type entered is germanium, and ion implantation energy is less than or equal to 7keV more than or equal to 2keV,
Ion implantation dosage is more than or equal to 1E13atom/cm2And less than or equal to 1E15atom/cm2。
5. the forming method of transistor as claimed in claim 3, it is characterised in that described amorphizing ion is noted
The injection ionic type entered is silicon, and ion implantation energy is less than or equal to 8keV more than or equal to 2keV,
Ion implantation dosage is more than or equal to 1E13atom/cm2And less than or equal to 1E15atom/cm2。
6. the forming method of transistor as claimed in claim 3, it is characterised in that described amorphizing ion is noted
The injection ionic type entered is carbon, and ion implantation energy is less than or equal to 22keV more than or equal to 2keV,
Ion implantation dosage is more than or equal to 1E13atom/cm2And less than or equal to 1E15atom/cm2。
7. the forming method of transistor as claimed in claim 2, it is characterised in that etching removes the first source electrode
After the part drain material layer of the part source electrode material layer of via bottoms and the first drain electrode via bottoms,
Before forming metal silicide layer, also include remaining source electrode material layer and remaining drain material layer
Make annealing treatment.
8. the forming method of transistor as claimed in claim 7, it is characterised in that described in be annealed into laser and move back
Fire, the temperature of described annealing is more than or equal to 800 DEG C and less than or equal to 1200 DEG C.
9. the forming method of transistor as claimed in claim 1, it is characterised in that described etching is that wet method is rotten
Erosion or dry etching.
10. the forming method of transistor as claimed in claim 1, it is characterised in that described etching is that wet method is rotten
During erosion, described wet etching agent is tetramethyl ammonium hydroxide solution.
The forming method of 11. transistors as claimed in claim 2, it is characterised in that remove part source electrode material
The degree of depth that the degree of depth of layer and drain material layer is injected less than or equal to described amorphizing ion.
The forming method of 12. transistors as claimed in claim 1, it is characterised in that described transistor is PMOS,
Described source electrode material layer and drain material layer include germanium silicon layer；Described transistor is NMOS, described source
Pole material layer and drain material layer include silicon carbide layer.
The forming method of 13. transistors as claimed in claim 1, it is characterised in that form metal silicide layer
After, fill full second dielectric layer in described first source electrode through hole and in the first drain electrode through hole, described the
Second medium layer is equal with described first medium layer.
The forming method of 14. transistors as claimed in claim 13, it is characterised in that lead at described first source electrode
Forming the second source electrode through hole in second dielectric layer in hole, described second source electrode via bottoms is exposed described
Metal silicide layer；
The second drain electrode through hole, described second drain electrode is formed in second dielectric layer in described first drain electrode through hole
Via bottoms exposes described metal silicide layer.
The forming method of 15. transistors as claimed in claim 1, it is characterised in that described Semiconductor substrate has
Having fin, described grid structure is across described fin, and covers top and the sidewall of described fin；
Source electrode material layer and drain material layer is formed in the fin of described grid structure both sides.
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| CN201510215853.1A CN106206301A (en) | 2015-04-29 | 2015-04-29 | The forming method of MOS transistor |
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| CN109326645A (en) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacturing method |
| CN109427880A (en) * | 2017-08-22 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| CN109599338A (en) * | 2017-09-30 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109786248A (en) * | 2017-11-13 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110098146A (en) * | 2018-01-31 | 2019-08-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| US11545562B2 (en) | 2017-07-31 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109326645A (en) * | 2017-07-31 | 2019-02-12 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacturing method |
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| US11545562B2 (en) | 2017-07-31 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
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| CN109599338A (en) * | 2017-09-30 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN110098146B (en) * | 2018-01-31 | 2020-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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Application publication date: 20161207 |