CN106168933B - A method of virtual dual-port shared drive is realized based on high-speed serial communication - Google Patents
A method of virtual dual-port shared drive is realized based on high-speed serial communication Download PDFInfo
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Abstract
The invention discloses a kind of methods for realizing virtual dual-port shared drive based on high-speed serial communication, belong to embedding assembly technical field.Communication cpu both sides of the invention respectively have a fpga chip to provide it RAM bus interface, are connected between two fpga chips with high speed communication lines, FPGA internal firmware realizes each layer communication protocol and RAM access function.The invention enables the interactions between CPU can be simple and efficient such as dual port RAM, and has very big flexibility in hardware distribution.
Description
Technical field
The invention belongs to embedding assembly technical fields, in particular it relates to which a kind of be based on high-speed serial communication
The method for realizing virtual dual-port shared drive.
Background technique
Embedded computing system is widely used in industrial control field.The automatically-monitored equipment of electric system secondary side is allusion quotation
The embedded computing system application of type, it is internal comprising one or more embedded units, realize specific protection control or
Data monitoring function.Such automation equipment is logically usually made of following several parts: analog acquisition unit, signal are defeated
Enter unit, control output unit, Logical processing unit, data processing unit, communications interface unit, man-machine interaction unit etc..
The embedding assembly equipment of early stage mostly forms embedded Control computing system by core of single CPU or DSP, and realization is set
Standby required function.With the variation of the external environments such as power grid demand, technology development, calculated performance, extended capability of equipment etc. are each
Item index steps up, so that must can be met the requirements using more set embedded subsystems inside equipment.Between multiple CPU how
Carrying out real time data interaction becomes the key points and difficulties of system design.
Substantially there are two types of modes: parallel mode, serial mode for real time data interaction between CPU.Parallel mode refers to use
Dual port memories chip (abbreviation dual port RAM) provides two sets of memory compatible bus, and two CPU are accessed jointly in same section
It deposits.Serial mode is connected between referring to two CPU by high-speed buses such as Ethernet, LVDS, is executed specific communication protocol and is counted
According to transmitting-receiving.Both modes all have some limitations.The parallel mode of dual port RAM can only be located at same print in two CPU
Shi Caiyong in making sheet；Serial communication mode can occupy the execution that a large amount of computing resource of CPU carries out communication protocol, reduce CPU
Application performance and reliability in time.In addition, also there is the high speed interactive selection of standardized multi -CPU, such as PCI, PCI-E, but this
Class scheme has higher requirements to system cost, development difficulty and production technology degree, be not widely deployed for middle low complex degree and at
The industrial control system of this sensitivity.
Summary of the invention
Object of the present invention is to: aiming at the problem that between communication among multiple CPUs in the prior art, provide a kind of logical based on high speed serialization
The method of reliable existing virtual dual-port shared drive.
Realize specifically, the present invention adopts the following technical solutions: the CPU of data interaction both sides passes through logical by two
It crosses the fpga chip that high speed serial communication link connects and carries out data interaction；It include RAM, RAM inside the fpga chip
For the storage of data, the CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively, and two sides ram space is identical, ground
Location is corresponding；When data are written into the RAM of the FPGA of its side in side CPU, which passes through high-speed serial communication for this data
Link is sent to the FPGA of the other side, this data is accessed by accessing the RAM identical address of the FPGA of its side in other side CPU.
Above-mentioned technical proposal is further characterized by, when side CPU enters data to the RAM write of the FPGA of its side,
After data reach other side CPU, the identical address of the RAM of the FPGA of data original write-in side is passed back to automatically, as data original is written
The CPU of side read this passback statistics indicate that data reliably reach other side.
Above-mentioned technical proposal is further characterized by, and the RAM of the FPGA is divided into multiple numbers according to the sequence of address
According to mapping priority, the high priority data transmission of the address area high in priority.
Above-mentioned technical proposal is further characterized by, and the RAM of the FPGA is equipped with read-write Acceditation Area and system registry area,
For managing the transmitting-receiving timing and error handle of data.
The invention also discloses a kind of safety and stability control device of electric network based on the communication of virtual dual-port shared drive, packets
Central processing module and each function module are included, is used between each module above-mentioned based on the virtual both-end of high-speed serial communication realization
The method of mouth shared drive is communicated.
Beneficial effects of the present invention are as follows: the data interaction side that the present invention combines both dual port memories and high-speed communication
Method.Communication cpu both sides respectively have a fpga chip to provide it RAM bus interface, with high speed communication lines phase between two fpga chips
Even, so that the interaction between CPU can be simple and efficient such as dual port RAM, and have very big flexibility in hardware distribution, special
The interaction of multiple subsystem complex data Shi Yongyu not be solved the problems, such as.
Detailed description of the invention
Fig. 1 is COM_RAM fundamental block diagram.
Fig. 2 is that COM_RAM often uses topological diagram.
Fig. 3 is the asymmetric switching node schematic diagram of COM_RAM.
Fig. 4 is COM_RAM work flow diagram.
Fig. 5 is COM_RAM typical case: stability control device physical assemblies schematic diagram.
Fig. 6 is COM_RAM typical case: stability control device communication topology figure.
Specific embodiment
Below with reference to embodiment and referring to attached drawing, present invention is further described in detail.
Embodiment 1:
The example for the virtual dual-port RAM (abbreviation COM_RAM) realized embodiment shows one with FPGA programming.Its base
In the extensive programmable logic chip of FPGA and High-Speed Communication Technique, enable CPU positioned at high-speed serial communication both link ends
Enough efficient and convenient data interactions carried out as dual port RAM in plate.
The basic principle that COM_RAM is realized is the firmware program by designing FPGA, the automatic multilayer for realizing data communication
Agreement only provides standardized RAM access interface to the CPU of data interaction both sides, simplifies its communication process burden, enables CPU
Enough it is absorbed in the realization of application software.
The basic realization of COM_RAM is as shown in Figure 1, COM_RAM is got up by two by high-speed serial communication link connection
Fpga chip and respective physical interface constitute, all include 2 logic units (LOGIC) and caching inside each fpga chip
(RAM), wherein 2 logic units are respectively used to realize data sending logic (SEND LOGIC) and data acceptance logic
(RECEIVE LOGIC), RAM are used for the storage of data.The CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively,
The interaction of shared RAM formula is made up of COM_RAM.When data are written into the RAM of the FPGA of its side in side CPU, the FPGA
This data is sent to the FPGA of the other side by high-speed serial communication link, other side CPU passes through the FPGA's for accessing its side
This data is accessed in RAM identical address.
Since COM_RAM is mainly accomplished that data communication function, the layer structure of Open System Interconnection OSI can refer to it
It is described.Following table briefly lists COM_RAM and is communicating the function control in each layer corresponding to OSI.Below from the function of each layer
It is able to achieve and is introduced respectively with characteristic.
Application level function by both party realize by CPU interactive application data.COM_RAM connects the CPU interaction for providing RAM mode
Mouthful, which can have the following characteristics that
1, data interaction two sides CPU accesses one section of shared RAM and interacts, and interface is similar to true dual port RAM chip.
2, standard SRAM bus interface is provided on hardware, 8/16/32 optional, and Intel/PowerPC mode is optional.
3, the size of dual port RAM is variable according to application, and low is 256 bytes, Gao Kewei 64k byte.
4, COM_RAM Module Reusable makes certain CPU that can realize the parallel interaction with multiple CPU by continuous multi-stage RAM.
The basic function of transport layer is that the data that the side A CPU write is entered certain address in shared RAM are reliably mapped to the side B CPU
RAM in identical address, that is, apply data mapping.Here like address refers to relative address, and two sides CPU is to this section of RAM
The absolute address of definition may be different.Transport layer realizes reliable mapping by data register and mechanism of rebounding.In view of COM_RAM
It is virtual dual-port RAM, data map the bandwidth that successful speed depends primarily on serial communication link, under most conditions can not
Reach the data mapping speed in single peripheral access period of true dual port RAM in plate, then transport layer introduces priority mechanism,
That is the high priority data of high priority is mapped.Details are as follows for this layer of principle:
1, the basic usage scenario of COM_RAM is point-to-point interaction, i.e., It is RAM Interface between CPU and FPGA, two sides ram space is identical, and address is corresponding, is with byte
Basic unit.
2, data map: new data is written in certain address into RAM CPU_A, and CPU_B should be over time in identical address
This new data is accessed.
3, it rebounds mechanism: after new data is written to the address RAM in CPU_A, after data reach the side CPU_B, can return automatically
The identical address (identical address that the RAM of the FPGA of side is written in data original) of CPU_A is passed to, CPU_A could be read herein at this time
New data.After i.e. CPU write enters data, as long as readback is correct, indicate that data reliably reach other side.
4, priority mechanism: the area RAM is divided into several data mappings according to the sequence of address and (transmits) priority, such as
Address 0-255 is high priority, and address 256-64k is low priority.The transmission mechanism of different priorities data, similar in CPU
The corresponding mechanism that different priorities interrupt, i.e. current priority soprano obtain prioritised transmission resource.The data of different priorities
Mechanism gives CPU and is applying upper flexibility.The high interaction data of requirement of real-time can be written to lower address area by CPU, be made
It most fastly being capable of the side's of being received reading.
5, login mechanism: every side RAM is respectively designed with read-write Acceditation Area, system registry area, for managing the transmitting-receiving of data
Timing and error handle.Acceditation Area is automatic management region, and CPU can not be accessed.The reality of the size and RAM of reading and writing Acceditation Area is big
Small correspondence, its corresponding RAM write of each of which unit record enter/read transmission state, the reception state of byte；System registry area mark
Note and record precedence information, error handle state etc..
In the communication networks such as Ethernet, network layer is usually realized by operations such as routing, exchanges, by complex topology network
In certain source node reliable data transmission to destination node.The design of COM_RAM is mainly directed towards Industry Control calculating field, application
Under more fixed Topology connection operating condition, do not have complicated routing, function of exchange.Although the basic module of COM_RAM is
Point-to-point virtual dual-port RAM, but by reasonable disposition, it can be achieved that a variety of topologys such as point-to-point, point-to-multipoint, multiple spot ring are answered
With.If more complicated network construction can be further realized in the operation of application layer in conjunction with CPU.Topological mode is summarized as follows:
1, point-to-point: the basic topology application of COM_RAM.I.e. two CPU are exchanged visits by COM_RAM, such as Fig. 2 institute
Show.
2, point-to-points: certain CPU side reuses multiple COM_RAM modules in FPGA, while being also connected to more sides in hardware link
CPU.By connected reference multistage address ram the parallel interaction with multi -CPU can be realized, as shown in Figure 2 in local cpu in this way.
3, multiple spot ring: cpu node CPU_A, CPU_B and CPU_C there are three setting, they have COM_RAM all the way respectively and connect
Mouthful, annular concatenation is TX_A- > RX_B, TX_B- > RX_C, TX_C- > RX_A to every road COM_RAM on the communication link.By above
The data mapping and mechanism of rebounding, multiple CPU can share same section of RAM, as shown in Figure 2.
4, asymmetric exchange: in a variety of industrial applications, the data flow of control system has asymmetric feature, such as more distributions
Data converge to central node, management node issues broadcast data at most executes node, etc. for node acquisition.For this purpose, COM_RAM
Expanded a kind of switch version of one-to-many asymmetric transmitting-receiving: many-one realizes convergence, one-to-many realization broadcast.Correspondingly,
Physical link must also carry out the configuration of 1+N.In this way, under above-mentioned multidrop network, with lower physics and design cost, side
Multiple CPU can share the data interaction of same section of RAM realization and other side list CPU.As shown in Figure 3.
The basic function of link layer is that unit data is reliably sent to opposite end from communication one end, is generally with data frame
Unit.In view of adapting to the high reliability in multiple physical layers communication link, and guarantee industrial application, COM_RAM is in link
The design of layer has following several features:
1, short frame is efficiently synchronized: to guarantee the real-time of transmission upper layer data and based on the considerations of connection reliability,
Link layer is transmitted using frame synchronization, i.e., receiving-transmitting chain repeats to transmit as unit of frame.Frame head is special byte code, and frame is can
Become the upper layer data data of frame length, postamble is this frame cyclic redundancy check.The higher data frame length of priority is shorter.Its workflow
Figure is as shown in Figure 4.
2, balance byte code: link layer include the basic unit of the data of frame head be encode after byte.According to object
The difference of layer interface is managed, byte is encoded using 8b10b or 5b4b.Use specific code in byte code as frame transmitting-receiving and preferential
The management of grade.
3, flexible physical layer interface: link layer and physical layer interface are roughly divided into two classes, first is that link layer and physics are received
Device or circuit direct interface are sent out, byte code is carried out by link layer；Second is that with standardized physical chip such as ethernet PHY
Interface, link layer carry out the transmitting-receiving of byte with dedicated timing control PHY chip, and the encoding and decoding of byte are automatically performed by PHY chip.
Physical layer provides the physical medium of communications, and guarantees the reliability of transmission as far as possible in design.In order to suitable
A variety of industrial application environment are answered, COM_RAM supports a variety of communication specifications and form of medium on a physical layer.According to usage scenario
Difference, institute's support pattern are listed below:
1, interaction in plate: high speed SERDES (1Gbps-2.5Gbps), LVDS (10Mpbs-800Mbps.
2, backboard interaction: LVDS (10Mpbs-500Mbps), BLVDS/MLVDS (10Mpbs-100Mbps.
3, interaction between cabinet: 10bpsM/100Mbps/1000bpsM Ethernet cable, special optic fibre (10Mbps-
2.5Gbps)。
4, remote interaction: E1 coaxial cable (multiplex link, the road 2Mbps/), SDH optical fiber (155Mbps-2.5Gbps).
In order to cope with the feature that physical layer medium is changeable, application scenarios are complicated, have following two in the design of physical layer
A feature:
(1) link is changeable, and mechanism is constant: under different application scenarios and restrictive condition, there are many physical communication links
Situation, as passed through SERDES in applying in plate or can realize the traffic rate of 2.5Gbps, and middle and long distance uses Ethernet cable
Application in may be down to 10Mbps.Due to the design of layering, so that the communication mode of physical layer and rate only influence
The frame transmission speed of link layer, does not have an impact upper layer realization mechanism or reliability.
(2) link doubles, and bandwidth multiplication: original intention of the invention is exactly so that the communicating pair under the conditions of serial link to the greatest extent may be used
The raising data interaction efficiency of energy, so under physical condition allows, it should improve data transfer bandwidth as far as possible.Therefore, exist
In place of link layer and physical layer interface, the mechanism of bandwidth multiplication is in addition devised, even if a plurality of identical communication link can provide
Bandwidth increments corresponding with mathematics promote (due to the increase of the communication overheads such as alignment of data, actual bandwidth is slightly lower).Such as it is being based on
In the application of backboard LVDS communication, the mapping of 4 byte datas (CPU_A write-in, CPU_B are read) delay of single 100Mbps link
About 1us, when 5 same links access simultaneously, delay will shorten to 200ns, this speed responds speed with true dual port RAM
Degree is close.In LVDS class physical link, this function can be directly supported；In ethernet link, it need to carry out direct-connected could supporting；
Physically support the bandwidth multiplication divided, in the application of the E1/SDH link of a multiplex protocol, it can be achieved that distant place communicates.
Embodiment 2:
The utilization that embodiment shows COM_RAM in safety and stability control device of electric network.
Safety and stability control device of electric network is control equipment important in high voltage substation.Every set equipment is usually by several machines
Case composition, each cabinet has multiple plug-in units, realize respectively analog acquisition, logic calculation, On-off signal output, man-machine interface,
The functions such as correspondence with foreign country.Mostly comprising the embedded system centered on a CPU in plug-in unit.Between the plug-in unit of cabinet inside, cabinet
It is required to carry out real-time, interactive.Interactive data have nothing in common with each other to real-time, bandwidth and data flow.As switching value data is real-time
Property require that high, bandwidth is low, bidirectional equalization, man-machine data bandwidth is high but input and output are unbalanced, real-time is lower, acquires data band
High and unidirectional uplink of wide, requirement of real-time, etc..If passing through various configurations mode in the system application COM_RAM technology
Combination, can efficiently solve the problems, such as multiple subsystem complex data interaction.
Fig. 5 lists a kind of typical safety and stability control device hardware configuration.Apparatus system is made of multiple cabinets, point
One mainframe box and one or more from cabinet.In mainframe box central processing unit needs collect respectively from the acquisition of cabinet, switch,
The data such as communication are simultaneously calculated and logic judgment in real time, while to respectively from cabinet output control command or communication data.Respectively from
Cabinet configures internal module according to application demand.It is all physically to be communicated from cabinet with mainframe box by optical fiber.
Fig. 6 describes the communication logic inside above-mentioned stability control device with COM_RAM between each module of main communication mode
Structure:
1, inside mainframe box, LVDS link and data management module, man-machine boundary that central processing module passes through case back plate
Face mould part is communicated.Data management module realizes the functions such as storage, printing, the background communication of system data；Man-machine interface mould
Part realizes the functions such as the liquid crystal display of system man-machine interface, keyboard input.
2, central processing module by bidirectional optical fiber with respectively communicated from cabinet.Each from cabinet configured with communication exchange
Module is realized from the asymmetric data real-time exchange in cabinet between multimode part and central processing module, both ends is made to share same section
Data exchange space.According to the actual data transfer bandwidth needs of application, certain can configure multipair optical fiber from cabinet to improve communication
Bandwidth.
3, it configures and opens, outputs etc. in the cabinet of modules, communication bandwidth is smaller, can be realized by the topological mode of multiple spot ring
The connection of multiple cases and central processing module meet demand and can save communication interface resource in this way.
4, from cabinet inside, each module is provided with the communication channel that module is exchanged with communication.According to the inhomogeneity of module
Not, the physical channels such as LVDS, BLVDS, CAN, RS-485 in backboard resource can be used, COM_RAM, MODBUS etc. is respectively adopted
Communication protocol.In fpga chip in communication exchange module, design has the IP module of DMA function, to realize COM_RAM and MOD_
The seamless exchange of the low-speed communications interface such as BUS, facilitates the exchanging visit of communicating pair CPU.
Although the present invention has been described by way of example and in terms of the preferred embodiments, embodiment is not for the purpose of limiting the invention.Not
It is detached from the spirit and scope of the present invention, any equivalent change or retouch done also belongs to the protection scope of the present invention.Cause
This protection scope of the present invention should be based on the content defined in the claims of this application.
Claims (5)
1. a kind of method for realizing virtual dual-port shared drive based on high-speed serial communication, which is characterized in that data interaction is double
The CPU of side is by carrying out data interaction by the fpga chip that high-speed serial communication link connection is got up by two；The FPGA
Chip interior includes RAM, and RAM is used for the storage of data, and the CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively,
Two sides ram space is identical, and address is corresponding；When data are written into the RAM of the FPGA of its side in side CPU, which counts this
According to the FPGA for being sent to the other side by high-speed serial communication link, other side CPU is identical by the RAM for accessing the FPGA of its side
This data is accessed in address；
Wherein by communication process between high-speed serial communication both link ends be divided into application layer, transport layer, network layer, link layer,
Totally 5 layers of physical layer, transport layer, network layer, link layer are realized by the FPGA；
The application layer for describe can be provided for communicating pair CPU the access interface for being equal to dual-port shared drive and
Characteristic, transport layer and following layers provide the access interface of dual-port shared drive for application layer；
Transport layer is used for one section of communication memory address mappings of communicating pair, and using rebound mechanism and priority mechanism；
The network layer is divided into point-to-point, multiple spot ring, point-to-points, asymmetric exchange for realizing network topology, by communication network
Four seed types, wherein two CPU of point-to-point finger are exchanged visits by the RAM of FPGA, multiple spot ring refers to that multiple cpu nodes are communicating
Chain road annular concatenation shares same section of RAM, it is point-to-points refer to side CPU by the multistage address ram of connected reference FPGA with
More side CPU are interacted parallel, and asymmetric exchange refers to that the multiple CPU in side share the number of the RAM and other side list CPU of same section of FPGA
According to interaction；
Unit data is reliably sent to opposite end from communication one end by the link layer, is transmitted using short frame format, and frame head is spy
Different byte code, frame are the upper layer data data of variable frame length, and postamble is this frame cyclic redundancy check, the higher data of priority
Frame length is shorter, when link layer and physics transceiving device or circuit direct interface, carries out byte code by link layer, works as link layer
When with standardized physical chip interface, byte code is carried out by physical chip；
The physical layer is for providing the physical medium of communications.
2. the method according to claim 1 for realizing virtual dual-port shared drive based on high-speed serial communication, feature
It is, the mechanism of rebounding refers to, when side CPU enters data to the RAM write of the FPGA of its side, reaches other side CPU in data
Afterwards, the identical address for passing back to the RAM of the FPGA of data original write-in side automatically, as the CPU of data original write-in side reads this passback
Statistics indicate that data reliably reach other side.
3. the method according to claim 1 or 2 for realizing virtual dual-port shared drive based on high-speed serial communication, special
Sign is that the priority mechanism refers to, the RAM of the FPGA is divided into multiple data according to the sequence of address and maps priority,
The high priority data of the address area high in priority transmits.
4. the method according to claim 1 or 2 for realizing virtual dual-port shared drive based on high-speed serial communication, special
Sign is that the RAM of the FPGA is equipped with read-write Acceditation Area and system registry area, at the transmitting-receiving timing and mistake for managing data
Reason.
5. it is a kind of based on virtual dual-port shared drive communication safety and stability control device of electric network, including central processing module with
And each function module, which is characterized in that using being realized based on high-speed serial communication as described in claim 1 ~ 4 between each module
The method of virtual dual-port shared drive is communicated.
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| CN107367991A (en) * | 2017-08-04 | 2017-11-21 | 湖南利能科技股份有限公司 | A kind of data acquisition device based on AMP |
| CN110750069B (en) * | 2019-12-24 | 2020-05-22 | 武汉精立电子技术有限公司 | Multi-equipment control device of AOI system |
| CN112181886A (en) * | 2020-10-16 | 2021-01-05 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Information interaction system, method and medium based on LVDS channel |
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| CN104021098A (en) * | 2014-06-19 | 2014-09-03 | 福州闽台机械有限公司 | Multi-board collaboration architecture based on DMA transparent transmission |
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