CN106158920B - A kind of power device and preparation method thereof - Google Patents
A kind of power device and preparation method thereof Download PDFInfo
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- CN106158920B CN106158920B CN201510166724.8A CN201510166724A CN106158920B CN 106158920 B CN106158920 B CN 106158920B CN 201510166724 A CN201510166724 A CN 201510166724A CN 106158920 B CN106158920 B CN 106158920B
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
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- 229920005591 polysilicon Polymers 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 16
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- 238000001312 dry etching Methods 0.000 claims description 7
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
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Abstract
The invention discloses a kind of power unit structure and preparation method thereof, the extension area including the epitaxial layer of substrate, the first conduction type and the second conduction type that set gradually；Main interface with the second conduction type of heavy doping and the cut-off ring with the first conduction type in the epitaxial layer, the extension area is between the main interface and the cut-off ring, the extension area is connected with the main interface, and the extension area is not connected to the cut-off ring；At least there are two, ion concentration identical ion implanted regions identical as main interface conduction type for tool in the extension area, and the spacing of adjacent ion implanted region increases with the increase apart from the main interface distance.Knot terminal elongated area area by reducing power device realizes that partial pressure region area reduces, and saves chip area, more devices can be made on silicon wafer of the same area, reduce element manufacturing cost.
Description
Technical field
The present invention relates to semiconductor device processing technology fields, more specifically, being related to a kind of power device and its production
Method.
Background technique
Insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor) is novel big function
Rate device, it integrates MOSFET grid voltage control characteristic and bipolar junction transistor low on-resistance characteristic, improves device
The case where part pressure resistance and conducting resistance mutually restrain has high voltage, high current, high-frequency, power integration density height, input resistance
Resist the advantages such as big, conducting resistance is small, switching loss is low.In frequency-conversion domestic electric appliances, Industry Control, electronic and hybrid vehicle, new energy
The numerous areas such as source, smart grid have been widely used space, and to ensure an important prerequisite item of IGBT high voltage
Part is excellent terminal protection structure, and the main function of terminal protection structure is to undertake device transverse electric field, guarantees that power is partly led
The voltage endurance capability of body device.
As shown in Figure 1, field limiting ring structure include inner ring partial pressure protection zone 11 and outer ring by ring 12.When bias is added in
When on collector 13, with the increase of institute's biasing, depletion layer extends along main knot 14 to the direction of the first field limiting ring 15.In electricity
Pressure increases to before the avalanche breakdown voltage of main knot 14, and depletion region of the depletion region of main knot with the first field limiting ring 15 converges,
Depletion region curvature increases, and is pass-through state between main knot and ring knot, thus weakens the accumulation electric field in main knot knee, breakdown potential
Pressure is improved.Before avalanche breakdown occurs for the first field limiting ring 15,16 break-through of the second field limiting ring, and so on.However field limits
Ring terminal structure suffers from the drawback that traditional field limiting ring structure by implanted dopant, relies on divergent contour of the impurity in thermal process
At field limiting ring one by one.In order to prevent two adjacent field limiting rings from diffusing into one another, the spacing of field limiting ring and field limiting ring must be kept
Remote enough, this makes the area of field limiting ring larger, increases element manufacturing cost.
Summary of the invention
The embodiment of the present invention provides a kind of power device, and the knot terminal elongated area area by reducing power device is realized
It divides region area to reduce, saves chip area, more devices can be made on silicon wafer of the same area, are reduced
Element manufacturing cost.
To achieve the above object, the embodiment of the invention provides following technical solutions:
A kind of power device, including the epitaxial layer of substrate, the first conduction type that sets gradually and the second conduction type
Extension area；Main interface with the second conduction type of heavy doping and the cut-off ring with the first conduction type in the epitaxial layer,
Between the main interface and the cut-off ring, the extension area is connected the extension area with the main interface, described to prolong
Area is stretched not to be connected to the cut-off ring；At least there are two, ion concentrations identical as main interface conduction type for tool in the extension area
Identical ion implanted region, and the spacing of adjacent ion implanted region increases with the increase apart from the main interface distance.
It further, further include the first medium layer on the non-implanted regions window of the extension area.
Wherein, the main interface is connected with the extension area by field plate, and at least in the extension area close to institute
The side setting for stating main interface has the polysilicon layer of the first conduction type as the field plate.
It further, further include the second dielectric layer being covered on the epitaxial layer and the extension area.
Based on power unit structure described above, the present invention provides a kind of production method of power device, comprising:
Epitaxial layer with the first conduction type and the second conduction type are sequentially formed by epitaxial growth on substrate
Initial extension area；The initial extension area is performed etching to form extension area, exposes the first area of the epitaxial layer and the
Two regions；At least two ion implantation windows are formed on the extension area；The ion implanting for carrying out the second conduction type exists
The main interface of the first conduction type of heavy doping is formed in the first area and forms heavy doping first in the extension area leads
The ion implanted region of electric type, the extension area are connected with the main interface, and the spacing of adjacent ion implanted region is with distance
The increase of the main interface distance and increase；The ion implanting for carrying out the first conduction type forms first in the second area and leads
The cut-off ring of electric type, the extension area are not connected to the cut-off ring.
Further, at least two ion implantation windows are formed on the extension area, specifically: in the extension area
Upper one dielectric layer of growth regulation；By first medium layer described in the first mask plate dry etching, at least two ion implanting windows are formed
Mouthful.
Wherein, the extension area is connected with the main interface, specifically:
After forming at least two ion implantation windows, the polysilicon layer of the first conduction type is deposited, is covered by second
Polysilicon layer described in film version dry etching forms polysilicon side wall, in the extension area close to the polysilicon side in the main interface
Main interface is connected by wall with the extension area.
Further, after ion implantation, further includes: deposit forms second on the epitaxial layer and the extension area
Dielectric layer.
In the knot terminal extended structure of power device of the present invention, at least there are two lead tool with main interface in the extension area
Electric type is identical, the identical ion implanted region of ion concentration, and the spacing of adjacent ion implanted region is with apart from the main interface
The increase of distance and increase so that the ion concentration in every section of region of extension area is successively decreased paragraph by paragraph because extension area passed through before this it is outer
Prolong growth, therefore ion concentration is uniform, then by variation spacing progress ion implanting make every section have one it is highly concentrated
The ion implanted region of degree, so that the ion concentration in every section of region of extension area is in the trend successively decreased paragraph by paragraph, this extension plot structure
The electric field strength that main knot knee can effectively be weakened, so that being improved breakdown voltage, and then can effectively improve knot
The area efficiency of terminal extended structure reduces partial pressure region area.It divides region area to reduce, chip area is saved, in phase
Just increase with the device that can be made on the silicon wafer of area, reduces chip cost.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is the schematic diagram of the field limiting ring structure for IGBT terminal protection；
Fig. 2 is the method flow schematic diagram that power device is made in the embodiment of the present invention；
Fig. 3 a to Fig. 3 h is the structural schematic diagram in each stage in the production process of power device disclosed by the embodiments of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that the described embodiments are only some of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
All other embodiment, shall fall within the protection scope of the present invention.
Semiconductor devices described in the embodiment of the present invention includes power diode, ambipolar isolated-gate field effect transistor (IGFET)
(IGBT), the devices such as metal oxide isolated-gate field effect transistor (IGFET) (MOS), thyristor (SCR).
The type of semiconductor is determined by majority carrier in semiconductor, if the majority carrier of the first conduction type is sky
Cave, then the first conduction type is p-type, and the first conduction type of heavy doping is P+ type, and the first kind being lightly doped is P-type；If
The majority carrier of first conduction type is electronics, then the first conduction type is N-type, and the first conduction type of heavy doping is N+
Type, the first kind being lightly doped are N-type.If the first conduction type is N-type, the second conduction type is p-type, and vice versa.
The embodiment of the present invention one proposes a kind of power unit structure, and as illustrated in figure 3h, Fig. 3 h is the power device to structure
The sectional view of part is described in detail power unit structure below with reference to Fig. 3 h.
Specifically, being illustrated by taking p-type channel as an example, i.e. the first conduction type is p-type, and the second conduction type is N-shaped, this
When merely illustrative, the embodiment of the equally applicable n-type channel of the invention.
The knot terminal extended structure includes:
Silicon wafer substrate 101, N- epitaxial layer 102, P- extension area 103；
There is the main interface 105 P+ and N+ to end ring 108, the P- extension area 103 is located at described in the N- epitaxial layer 102
Between the main interface 105 P+ and N+ cut-off ring 108, the P- extension area 103 is connected with the main interface 105 the P+, described
P- extension area 103 is not connected to N+ cut-off ring 108；
At least there are two identical as main 105 conduction type of interface of P+, ion concentration is identical for tool in the P- extension area 103
Ion implanted region 106, and the spacing of adjacent ion implanted region 106 increases with the increase apart from main 105 distance of interface of the P+
Greatly.
Wherein, the doping thickness of extension area 103 is commonly referred to as the depth of JTE (knot terminal extension) structure, abbreviation JTE knot
It is deep because JTE junction depth successively decreases step by step with the increase apart from main interface distance, ion concentration from main interface outward gradually
It reduces, weakens the electric field strength in main knot knee, be improved breakdown voltage, and then knot terminal extension can be effectively improved
The area efficiency of structure reduces partial pressure region area.It divides region area to reduce, chip area is saved, of the same area
The device that can be made on silicon wafer just increases, and reduces chip cost.
Wherein, the first medium layer 104 on the non-implanted regions window of the extension area passes through and is lithographically formed, the
The purpose of one dielectric layer 104 is to form ion implanted region window.
Preferably, the main interface 105 P+ is connected with the P- extension area 103 by field plate, at least in the P- extension area
The 103 side setting close to the main interface 105 the P+ has N-type polycrystalline silicon layer 107' as the field plate, the effect done so
It is that can further increase partial pressure effect in the case where having same partial pressure region area.
Preferably, further including the second dielectric layer 109 being covered on the epitaxial layer and the extension area, can effectively disappear
Except influence of the electric field to partial-pressure structure of surface accumulation, the effect of JTE structure partial pressure is maximized, improves device performance.
JTE structure function principle in the present embodiment is, when the reversed bias voltage rising on main interface makes semiconductor devices
Fringe field enhancing, when fringe field reaches critical electric field, punch-through will occur in the main knot of device, however work as and add
After JTE structure, when avalanche voltage breakdown not yet occurs for device main knot, main knot depletion region just has spread over JTE knot
Structure position, i.e., so that the depletion region of PN junction and the break-through of JTE structure, then main knot and the depletion layer of JTE structure are mutually linked,
Just induction produces JTE structure electric field near JTE structure, since JTE structure electric field is identical as main knot direction of an electric field, two electricity
For field mutually superposition to form pressure drop, being equivalent to just weakens the born potential difference of main knot；When applied voltage continues to rise, then by
JTE structure undertakes, and the increase of main knot electric field will be controlled.
In other words, the effect of JTE structure is equivalent to increase a voltage at the edge of planar power device
Divider can make applied voltage distribution in longer distance, so that preventing leads to device master since applied voltage is excessively high
The breakdown of knot, and then improve the voltage endurance capability of device.
The above are the power unit structures of the embodiment of the present invention, in order to better understand the present invention, with reference to embodiments
Two pairs of its production methods are described in detail.Such as Fig. 2, method includes the following steps:
Step S201: the epitaxial layer and second with the first conduction type is sequentially formed by epitaxial growth on substrate and is led
The initial extension area of electric type；
Step S202: performing etching to form extension area to the initial extension area, exposes the firstth area of the epitaxial layer
Domain and second area；
Step S203: at least two ion implantation windows are formed on the extension area；
Step S204: the ion implanting for carrying out the second conduction type forms the first conduction of heavy doping in the first area
The main interface of type and the ion implanted region that the first conduction type of heavy doping is formed in the extension area, the extension area and institute
It states main interface to be connected, the spacing of adjacent ion implanted region increases with the increase apart from the main interface distance；
Step S205: the ion implanting for carrying out the first conduction type forms cutting for the first conduction type in the second area
Only ring, the extension area are not connected to the cut-off ring.
Wherein, the ion implantation process of step S204 and step S205 is without inevitable ordinal relation, the ion of step S205
Injection process can also carry out after step S201, and the production that extension area 103 is connected with main interface 105 in step S204
Process can after ion implantation, or twice between ion implanting during formed.Step label in above-described embodiment is only
It is a kind of realization example, without specific sequencing between step.
Further, in step S203, at least two ion implantation windows are formed on the extension area, specifically
Are as follows: one dielectric layer 104 of growth regulation on the extension area；Pass through first medium layer 104 described in the first mask plate dry etching, shape
At at least two ion implantation windows.
Further, in step S204, the manufacturing process that extension area 103 is connected with main interface 105 be can be in shape
After at least two ion implantation windows, the polysilicon layer 107' of the first conduction type is deposited, the second mask plate dry method is passed through
The polysilicon layer 107' is etched, polysilicon side wall 107 is formed, in the extension area close to the polysilicon in the main interface 105
Main interface 105 is connected by side wall 107 with the extension area 103.The effect of polysilicon side wall 107 is that can have similarly
Partial pressure effect is further increased under partial pressure region area.
Wherein, in step s 201, it passes sequentially through to form diffusion source chemical vapor deposition on substrate 101 and has first
The initial extension area 103' of the epitaxial layer 102 of conduction type, the second conduction type.The diffusion source can be gas, can be with
For liquid, the effect that this technique is realized is can to accomplish initial extension area 103' intermediate ion even concentration distribution.
Further, after step S205, deposit forms second on the epitaxial layer 102 and the extension area 103
Dielectric layer 109 can effectively eliminate influence of the electric field of surface accumulation to partial-pressure structure, maximize the effect of JTE structure partial pressure,
Improve device performance.
Specifically, the production process of knot terminal is illustrated by following making step figure by taking p-type channel as an example.
As shown in Figure 3a, it firstly, providing substrate, is passed sequentially through on substrate 101 to diffusion source using CVD (Chemical
Vapor Deposition, chemical vapor deposition) form the epitaxial layer 102, the second conduction type with the first conduction type
Initial extension area 103', the effect that this technique is realized are can to accomplish initial extension area 103' intermediate ion even concentration distribution,
Instead of the mode of traditional JTE structure extension area ion implanting, traditional handicraft is in order to make ion free diffusing form different positions
Ion concentration difference this purpose is set, is realized by the way of being heated at high temperature again after ion implanting, practical operation gets up to control
Ion concentration is more difficult, thus the extension area area formed is larger, causes partial pressure region area larger, chip utilization rate drop
It is low.
As shown in Figure 3b, the initial extension area 103' in dry etching removal part, formation have after developing after coating photoresist
P- extension area 103 and first area and the second area for exposing the epitaxial layer.
As shown in Figure 3c, one dielectric layer 104 of growth regulation on the extension area, by described in the first mask plate dry etching
First medium layer 104 forms at least two ion implantation windows.
As shown in Figure 3d, the first area in the ion implantation window and epitaxial layer 102 on the extension area 103,
Main interface 105 and the ion implanted region 106 of P+ are formed in two regions by ion implanting, which can be positive the impurity of pentavalent
Ion, such as p5+.This have the effect that at least there are two, ions identical as main 105 conduction type of interface for tool in the extension area
The identical ion implanted region 106 of concentration, and the spacing of adjacent ion implanted region 106 is with apart from main 105 distance of interface
Increase and increase, so that the ion concentration in every section of region of extension area 103 is successively decreased paragraph by paragraph, weakens the electric-field strength in main knot knee
Degree, is improved breakdown voltage, and then can effectively improve the area efficiency of knot terminal extended structure, reduces partial pressure area surface
Product.It dividing region area to reduce, saves chip area, the device that can be made on silicon wafer of the same area just increases,
Reduce chip cost.
As shown in Fig. 3 e and Fig. 3 f, the polysilicon layer 107' of the first conduction type is deposited, is carved by the second mask plate dry method
The polysilicon layer 107' is lost, polysilicon side wall 107 is formed, in the extension area 103 close to the polysilicon in the main interface 105
Main interface 105 is connected by side wall 107 with the extension area 103, and the effect of field plate is that can have same partial pressure region
Partial pressure effect is further increased under area.
As shown in figure 3g, photoresist is applied, photoresist is exposed by third mask plate, the secondth area in the epitaxial layer
Domain forms N+ by ion implanting and ends ring 108, and the P- extension area 103 is not connected to N+ cut-off ring 108, and the N+
The cut-off main interface 105 ring 108 and P+ is oppositely arranged, and this have the effect that prevent semiconductor device surface from transoid and energy occurs
The contamination ion of enough collection semiconductor device surfaces, keeps device more stable.
As illustrated in figure 3h, deposit forms second dielectric layer 109 on the epitaxial layer 102 and the extension area 103, described
First medium layer 104 and the material of second dielectric layer 109 can mainly be made with passivation, usually silica, second dielectric layer 109
Be it is anti-oxidation, can effectively eliminate influence of the electric field to partial-pressure structure of surface accumulation, maximize the work of JTE structure partial pressure
With raising device performance.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent replacement, improvement and so within the spirit and principles in the present invention, are all contained in protection scope of the present invention
Within.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (9)
1. a kind of power device, it is characterised in that: the epitaxial layer and second of substrate, the first conduction type including setting gradually is led
The extension area of electric type；
The main interface with the second conduction type of heavy doping and the cut-off ring with the first conduction type, described in the epitaxial layer
Extension area is between the main interface and the cut-off ring, and the extension area is connected with the main interface, the extension area
It is not connected to the cut-off ring；
At least there are two, ion concentration identical ion implanted regions identical as main interface conduction type for tool in the extension area, and
The spacing of adjacent ion implanted region increases with the increase apart from the main interface distance, the ion note nearest apart from main interface
Entering between area and the main interface distance is first distance, the ion implanted region close apart from main interface time with it is nearest apart from main interface
The distance between ion implanted region be second distance, the first distance is less than the second distance.
2. power device as described in claim 1, which is characterized in that further include positioned at the non-implanted regions of the extension area
First medium layer on window.
3. power device as described in claim 1, which is characterized in that the main interface is connected with the extension area by field plate
It is logical.
4. power device as claimed in claim 3, which is characterized in that at least in the extension area close to the side in the main interface
Face setting has the polysilicon layer of the first conduction type as the field plate.
5. the power device as described in any claim of Claims 1 to 4, which is characterized in that further include being covered in the epitaxial layer
And the second dielectric layer on the extension area.
6. a kind of production method of power device characterized by comprising
The initial of epitaxial layer with the first conduction type and the second conduction type is sequentially formed by epitaxial growth on substrate
Extension area；
The initial extension area is performed etching to form extension area, exposes first area and the second area of the epitaxial layer；
At least two ion implantation windows are formed on the extension area；
The ion implanting for carrying out the second conduction type forms the main interface of the second conduction type of heavy doping in the first area
With the ion implanted region for forming the second conduction type of heavy doping in the extension area, the extension area is connected with the main interface
Logical, the spacing of adjacent ion implanted region increases with the increase apart from the main interface distance, apart from main interface it is nearest from
Distance is first distance between sub- injection region and the main interface, the ion implanted region time close apart from main interface with apart from main knot
The distance between nearest ion implanted region in area is second distance, and the first distance is less than the second distance；
The ion implanting for carrying out the first conduction type forms the cut-off ring of the first conduction type, the extension in the second area
Area is not connected to the cut-off ring.
7. method as claimed in claim 6, which is characterized in that form at least two ion implanting windows on the extension area
Mouthful, specifically:
One dielectric layer of growth regulation on the extension area；
By first medium layer described in the first mask plate dry etching, at least two ion implantation windows are formed.
8. the method for claim 7, which is characterized in that the extension area is connected with the main interface, specifically:
After forming at least two ion implantation windows, the polysilicon layer of the first conduction type is deposited, the second mask plate is passed through
Polysilicon layer described in dry etching forms polysilicon side wall, incites somebody to action in polysilicon side wall of the extension area close to the main interface
Main interface is connected with the extension area.
9. method according to claim 8, which is characterized in that after ion implantation, further includes: in the epitaxial layer and institute
It states deposit on extension area and forms second dielectric layer.
Priority Applications (1)
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| CN102651387A (en) * | 2011-02-25 | 2012-08-29 | 富士通株式会社 | Compound semiconductor device, method for producing the same, and power supply |
| CN102842609A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Junction terminal extension structure and method of manufacturing the same |
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| US8637386B2 (en) * | 2009-05-12 | 2014-01-28 | Cree, Inc. | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| WO2011091346A2 (en) * | 2010-01-22 | 2011-07-28 | Bridgestone Corporation | Polymers functionalized with nitrile compounds containing a protected amino group |
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| CN102651387A (en) * | 2011-02-25 | 2012-08-29 | 富士通株式会社 | Compound semiconductor device, method for producing the same, and power supply |
| CN102842609A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Junction terminal extension structure and method of manufacturing the same |
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