CN106158021A - There is the three-dimensional NAND gate memorizer of decoder and local word line driver - Google Patents
There is the three-dimensional NAND gate memorizer of decoder and local word line driver Download PDFInfo
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- CN106158021A CN106158021A CN201510134558.3A CN201510134558A CN106158021A CN 106158021 A CN106158021 A CN 106158021A CN 201510134558 A CN201510134558 A CN 201510134558A CN 106158021 A CN106158021 A CN 106158021A
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Abstract
The invention discloses a kind of memorizer.Memorizer includes by multiple stackings, multiple conductive vertical structure, multiple memory element, multiple wire and a control circuit.Described stacking is made up of multiple conductive strips.Described conductive vertical structure is orthogonal to described stacking.Memory element is positioned at the neighboring region of described stacking and the plotted point of the side surface of a little conductive vertical structures.Described stacking includes a bottom, multiple intermediate layer and a top layer.Multiple first wires are electrically coupled to top layer.Multiple second wires and multiple privates are electrically coupled to described intermediate layer.Control circuit selects at least one first given stack of described stacking for making described first wire, makes described second wire select this at least one first given stack and make described privates select at least one of which in described intermediate layer.
Description
Technical field
The present invention relates to a kind of high density memory Set, and arrange with multilayered memory unit particularly to one
Arrange into the storage device of three-dimensional volumetric array.
Background technology
Three-dimensional memory devices has developed into and comprises vertical channel structure (vertical channel structure)
Configuration in interior various changes.In vertical channel structure, comprise charge storing structure (charge
Storage structure) memory element (memory cell) be arranged at conductive strips horizontal plane and
The neighboring region of vertical actively band (vertical active strip).Conductive strips is as character line (word
line).Vertical actively band includes multiple passages that memory element uses.
Memorizer can include multiple planes of memory element, and it includes multiple horizontal conductive strips
The arrangement of multiple stackings of (horizontal conductive strip) or character line.Increase memorizer to hold
The trend of amount promotes the quantity of the stacking of horizontal conductive strips to increase.Horizontal strip selects line by going selection
Line (string select line) is selected.Unfortunately, the increase of the quantity of stacking causes electric capacity, makes an uproar
The problems such as sound (noise) and power consumption.
A kind of increase memory capacity but do not increase the method for the quantity of the stacking of horizontal conductive strips for increasing
Add quantity and the quantity of ladder contact (staircase contacts) of plane.The access of ladder contact increases
The plane of quantity.But, the density of the method and the wire being electrically coupled to ladder contact and decoder
Relevant.These density increased cause the challenge of other technique.
A kind of three dimensional integrated circuits memorizer using vertical channel structure need to be developed in pole at present, to reduce
Increase the shortcoming that memory span is brought.
Summary of the invention
According to various aspects of the invention, multiple wires (conductive line) e.g. block selects
Line (block select line), controls switch (control switch) e.g. transistor.Other are led
Line (e.g. layer selects line (layer select line)) carrying layer selects signal (layer select signal),
To select the certain layer of character line in turn.Transistor controls layer selects whether line is electrically coupled to character line
Different layers.The all of character line having selected layer will be opened when layer selects line independent.Layer select line with
Block selects the combination of line, then can only open the character line of the part selecting layer.Remaining wire (example
Row select line (string select line) in this way) select conductive strips (conductive strip) spy
Fixed stacking, the access of the end points being e.g. positioned at NAND gate row (NAND string) by startup is brilliant
Body pipe (access transistor).Row selection signal and block entrained by row select line select line to be taken
District's block selection signal of band all selects the given stack of conductive strips.The arrangement mode of this kind of wire can
Increase memory span without there being the problems referred to above again.After each aspect of the present invention will describe such as.
According to an aspect of the present invention, it is provided that a kind of storage device.Storage device includes by multiple wires
The stacking (stack) that (conductive line) is formed, multiple semiconductor vertical structure
(semiconductive vertical structure), multiple memory element (memory element), many
Individual wire and a control circuit.Semiconductor vertical structure is orthogonal to described stacking.Memory element is positioned at heap
The neighboring region of the side surface plotted point of folded and semiconductor vertical structure.
The stacked interleaved of conductive strips is in insulated strand.Stacking includes a bottom (bottom of conductive strips
Layer), multiple intermediate layers of conductive strips and a top layer of conductive strips.
Multiple first wires are electrically coupled to the top layer of conductive strips.Multiple second wires and the multiple 3rd
Wire is electrically coupled to intermediate layer.
Control circuit selects one first given stack (first of described stacking in order to make the first wire
Particular stack), make the second wire select the first given stack of described stacking and make the 3rd to lead
One certain layer (particular layer) in intermediate layer described in line options.
According to a further aspect in the invention, the decoder (decoder) that wire is used also is included.
According to a further aspect in the invention, it is provided that a kind of method.The method comprises the following steps:
Multiple first wire is made to select at least one first given stack (first particular of multiple stackings
stack).Described stacking is made up of multiple conductive strips (conductive strip).Described bus
Band crisscrosses multiple insulated strand (insulating strip).Described stacking includes described conductive strips
One bottom, multiple intermediate layers of described conductive strips and a top layer of described conductive strips.First leads
Line is electrically coupled to the top layer of band.
Multiple second wire is made to select the first given stack of described stacking.Second wire is electrically coupled to
Intermediate layer.
Privates is made to select a certain layer in described intermediate layer.Second wire is electrically coupled to intermediate layer.
Described first wire, described second wire and described privates assist multiple memory elements extremely
One of few selection.Described memory element is positioned at described stacking and multiple semiconductor vertical structures
Multiple neighboring regions of multiple plotted points of the side surface of (semiconductive vertical structure).
Described semiconductor vertical structure is orthogonal to described stacking.
In one embodiment, described first wire is row select line (string select line).Described
Two wires are electrically coupled to multiple switch (switch).Privates described in described switch electric property coupling and
Described conductive strips.Described privates is that layer selects line (layer select line).In an embodiment
In, described switch is transistor.Described transistor has multiple sides grid (lateral gate).Described
Side grid are positioned on multiple lateral conduction passage (lateral conductive channel).Described side
Face conductive channel is electrically coupled to described conductive strips and described privates.In one embodiment, institute
Stating switch is transistor.Described transistor has around vertical conduction passage (vertical conductive
Channel) multiple grid (gate).Described vertical conduction passage be electrically coupled to described conductive strips and
Described privates.
In one embodiment, described privates is electrically coupled to described centre by described second wire
Layer.
In one embodiment, different intermediate layers is electrically coupled to different ladder contact (staircase
And different privates is electrically coupled to different ladder contacts contact),.
In one embodiment, described second wire includes a specific decoding line (particular decoding
line).Described in specific decoding line options, stacking is multiple.Selected stacking is electrically coupled to described
The one first multiple set of one wire.The first different wire of the first set selects different stackings.
In one embodiment, one first conduction decoding line of described second wire only selects described stacking
One of them.
In one embodiment, loop is controlled in order to make described first wire select at least the one of described stacking
First given stack, make described second wire select described stacking at least one first given stack and
Do not select other parts of described stacking and make described privates select at least the one of described intermediate layer
Certain layer and do not select other parts in described intermediate layer.
In one embodiment, multiple privates are also included.Described privates are electrically coupled to described
Semiconductor vertical structure.Controlling loop makes described privates select the one of described semiconductor vertical structure
Subclass.This subclass is arranged in string, and these row are orthogonal to described stacking.
In one embodiment, described privates is parallel to described privates.
In one embodiment, one first decoder, one second decoder and one the 3rd decoder are also included.
First decoder is electrically coupled to described first wire.Second decoder is electrically coupled to described second and leads
Line.First decoder and the second decoder are positioned at the stacked on one first relative side of described heap and one second side,
And described first wire is parallel to described second wire.3rd decoder is electrically coupled to the described 3rd and leads
Line.3rd decoder is positioned at one the 3rd side of described stacking.3rd side is different from the first side and the second side.
More preferably understand in order to the above-mentioned and other aspect of the present invention is had, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below:
Accompanying drawing explanation
Fig. 1 is the simplified electrical circuit diagram of the two dimensional memory arrays of an embodiment；
Fig. 2 is the simplified electrical circuit diagram of a kind of 3 D memory array using vertical channel structure；
Fig. 3 is the schematic diagram of a kind of 3 D memory array showing and using vertical channel structure；
Fig. 4 is the top view of a kind of 3 D memory array using vertical channel structure；
Fig. 5 is the top view of a kind of Large Copacity 3 D memory array using vertical channel structure；
Fig. 6 is the top view of the another kind of Large Copacity 3 D memory array using vertical channel structure；
Fig. 7 is the top view of the another kind of Large Copacity 3 D memory array using vertical channel structure；
Fig. 8 is the block chart of a kind of 3 D memory array using vertical channel structure；
Fig. 9 is analogous to the simplified electrical circuit diagram of the path transistor of the three-dimensional memory devices of Fig. 8；
Figure 10 is to be a kind of three-dimensional memory devices using vertical channel structure and having path transistor
Top view；
Figure 11 is the another kind of three-dimensional memory devices using vertical channel structure and having path transistor
Top view；
Figure 12～13 is the another kind of three-dimensional storage using vertical channel structure and having path transistor
The top view of device and profile；
Figure 14～15 is the another kind of three-dimensional storage using vertical channel structure and having path transistor
The top view of device and profile；
Figure 16～17 is the another kind of three-dimensional storage using vertical channel structure and having path transistor
The top view of device and profile；
Figure 18 is the simplification block chart of the integrated circuit storage of one embodiment of the invention.
[description of reference numerals]
1,2,3: connector ladder
10,11: page buffer
20,21: wordline decoders
101: surface-mounted integrated circuit
120: vertical channel structure between stacking
130,141,142,143: connecting element
151、152、153、161、162、163、164、165、166、171、172、
173,174,175,176,181,182,183,184,185,186: interlayer is even
Fitting
160: reference conductor
167,177,187: conduction decoding line
170,190: access transistor
180: plotted point
201: row select line decoder
203: three-dimensional NAND gate memory array
204:X decoder
205: ladder connector
206: global character line
207: word line voltages generator
208: block decoder
209: local word line driver
231,232,233,234,235,236: stratum
251: vertical channel structure
252: memory element
261: vertical channel structure
262: dielectric medium
263,264,301,302: conductive plunger
310: horizontal channel structure
312,313: section line
1800: integrated circuit
1802: sensing amplifier and data input structure
1805: Data In-Line
1810: controller
1820: bias arrangement
1830: bus
1840: band decoder
1845: row selects and ground connection selects layer
1850: layer decoder/block decoder/local word line driver
1860: 3 D memory array
1865: bit line
1870: bit line decoder
1875: data/address bus
1885: DOL Data Output Line
1890: output circuit
B1, B2, B3: block selects line
BL1、BL1 12、BL1 13、BL2、BL2 14、BL2 15、BL3、BL3
16, BL3 17, BL4, BL4 18, BL4 19: bit line
B#: conduction decoding line
L1, L2, L3, L4: global character line
GND 34: earth point
GSL、GSL 32；GSL 210: ground connection selects line
SSL、SSL1、SSL2、SSL3、SSL 30、SSL1 42、SSL2 44、
SSL3 46、SSL1 42、SSL2 44、SSL3 46、SSL4 48、SSL5 50、SSL6
52, SSL#240: row select line
WL1 22、WL1 23、WL2 24、WL2 25、WL3 26、WL3 27、
WL4 28、WL4 29、WL0～WLN-1: character line
Detailed description of the invention
The embodiments of the invention graphic detailed description of collocation is as follows.The present invention is not limited to embodiment institute
The ad hoc structure disclosed and method.The present invention can pass through other features, element approach or other enforcement
Mode realizes.Preferred embodiment is only in order to exemplary explanation present disclosure, and is not used to limit
Protection scope of the present invention processed.Protection scope of the present invention is still as the criterion with claim.The present invention
Having usually intellectual in art, all to can be appreciated that described content comprises it impartial
Change kenel.Further, in different embodiments, similar element is with similar label narration.
Fig. 1 is the simplified electrical circuit diagram of two dimensional memory arrays.
Be connected to memory element multiple NAND gate (NAND) row by bit line (bit line) BL1 12,
BL2 14, BL3 16 and BL4 18 access.NAND gate row has the first end.First end passes through
Bit line is connected to page buffer (page buffer) 10.NAND gate row has the second end.Second end
It is positioned at earth point GND 34.First end of the NAND gate row being connected to page buffer 10 has multiple
Access transistor (access transistor), it is by row select line (string select line) SSL 30
Controlled.Second end of the NAND gate row being connected to earth point GND 34 has multiple access transistor,
It is selected line (ground select line) GSL 32 to be controlled by ground connection.Along NAND gate row not
With memory element by character line (word line) WL1 22, WL2 24, WL3 26 and
WL4 28 accesses.Character line WL1 22, WL2 24, WL3 26 and WL4 28 are by character
Line decoder (word line decoder) 20 is controlled.
Fig. 2 is the three-dimensional storage battle array using vertical channel structure (vertical channel structure)
The simplified electrical circuit diagram of row.
Cubical array is combined by multiple adjacent two-dimensional arraies.For convenience of explanation, circuit is simplified
Many two-dimensional arraies are in juxtaposition by figure.
NAND gate row is accessed by bit line BL1 13, BL2 15, BL3 17 and BL4 19 respectively.
Identical bit line is shared by multiple two-dimensional arraies.First end of NAND gate row is connected to page through bit line
Face buffer 11.NAND gate row has the second end in earth point GND 34.It is connected to page buffer
First end of the NAND gate row of 11 has access transistor, and it is by row select line SSL1 42, SSL2
The control of 44 and SSL3 46.The access transistor of specific two-dimensional array is by corresponding row select line
With control selected by SSL1 42, SSL2 44 and SSL3 46.It is connected to earth point GND's 34
Second end of NAND gate row has multiple access transistor, and it is selected the control of line GSL 32 by ground connection
System.Along NAND gate row different memory element by character line WL1 23, WL2 25, WL3 27,
WL4 29 accesses.Character line WL1 23, WL2 25, WL3 27, WL4 29 are by character line
The control of decoder 21.
Fig. 3 is the schematic diagram of the 3 D memory array using vertical channel structure.
Storage device includes the array of the memory element of NAND gate row.Storage device can be that bigrid hangs down
Straight channel storage array (double-gate vertical channel memory array, DGVC).?
In Fig. 3,3 D memory array includes an ic substrate (integrated circuit substrate)
101 and multiple stackings of being made up of multiple conductive strips.Each conductive strips is separated by insulant
Come, and include a bottom surface (ground connection select line GSL) of conductive strips, conductive strips multiple in
Interbed (character line WL0～WLN-1) and the end face (row select line SSL) of conductive strips.
Multiple vertical channel structures are orthogonal on described stacking, and include vertical channel structure between stacking
(inter-stack vertical channel structure) 120 and connecting element (linking element)
130.Between stacking, vertical channel structure 120 is between stacking.Connecting element 130 is positioned at stacking
Go up and connect vertical channel structure 120 between stacking.The material of the connecting element 130 of this example includes partly leading
Body, e.g. polysilicon, it has of a relatively high doping content, so that connecting element 130 has
Have higher than the electric conductivity of vertical channel structure 120 between stacking.Between stacking vertical channel structure 120 in order to
The channel region of the memory element in offer stacking.In figure 3, the material of connecting element 130 is permissible
Including N-type heavily-doped semiconductor material (N+doped semiconductor material).Between stacking
The material of vertical channel structure 120 can include semiconducting material is lightly doped.Memory element includes being connected to
The patterned conductive layer (not shown) of vertical channel structure, e.g. includes being connected to sensing circuit
Multiple global bit line (global bit line) of (sensing circuit).
Storage arrangement includes charge storing structure.Charge storing structure is positioned at the intermediate layer (word of stacking
Symbol line WL0～WLN-1) conductive strips and stacking between the plotted point of vertical channel structure 120
(cross-point)180.In the example described, the memory element being positioned at plotted point 180 is vertical
Straight kenel.Between one stacking, the bus of the both sides of vertical channel structure 120 is as bigrid
And can be read out, erase or programming process (dual-gates).In other embodiments, also
The grid of cincture can be used.Vertical channel structure passes through horizontal strip.Horizontal strip is in vertical channel
The frustum (frustum) of structure is around accumulation layer.Reference conductor 160 is arranged at the bottom of band
Between (ground connection selects line GSL) and ic substrate 101.
Storage device includes row selecting switch (string select switch) and with reference to selecting switch
(reference select switch).Row selecting switch is e.g. positioned at the access crystal of the top layer of band
Pipe (access transistor) 190.With reference to bottom (the ground connection choosing selecting switch to be e.g. positioned at band
Select line GSL) access transistor (access transistor) 170.In some example, electric charge stores up
Deposit the dielectric layer gate dielectric as access transistor 170,190 of structure.
In one embodiment, in order to reduce the resistance of reference conductor 160, storage device can include neighbour
It is bordering on the bottom-gate (bottom gate) of reference conductor 160.During reading program, suitable through applying
When the conducting voltage (pass voltage) impure well (doped well) in substrate or well (well),
Or other pattern conductive structure, bottom-gate can be started, to increase the conduction of reference conductor 160
Property.
Storage device includes connecting element.Connecting element includes that horizontal characters line and ground connection select line GSL
The touchdown area (landing rea) of line construction, to form the ladder contact (staircase of decoding circuit
contact).The row select line of the top layer of conductive strips couples independently and the controlled row select line that is formed on is translated
Code circuit (string selection line decoding circuits).
Intermediate layer (character line WL0～WLN-1) conductive strips and bottom (ground connection select line GSL)
Conductive strips link together, to reduce the area of decoder and to reduce the overall dimensions of storage device.
The conductive strips of top layer (row select line SSL) decodes independently, to allow bit line to decode.
Memory element can include connecting element (linking element) (e.g. connecting element 141
And 142) and interlayer connector (interlayer connector) (e.g. interlayer connector 151 and
152).In intermediate layer (character line WL0～WLN-1), connecting element 141,142 provides character line
Touchdown area (landing area).Interlayer connector 151,152 be coupled to connecting element 141,
The touchdown area of 142.Connecting element includes opening, so that interlayer connector passes through this opening and couples
Touchdown area to relatively low intermediate layer extended spot.Touchdown area is positioned at bottom surface and the company of interlayer connector
Connect the adjoiner of the end face of element.
As it is shown on figure 3, connecting element 141 provides is connected to character line WLN-1Touchdown area.Even
Element 142 offer is provided and is connected to character line WL0Touchdown area.
As it is shown on figure 3, the interlayer connector in intermediate layer concatenation character line is arranged in hierarchic structure.Lift
For example, interlayer connector 151 is connected to a touchdown area, to connect intermediate layer and character line WLN-1。
Interlayer connector 152 is connected to another touchdown area, to connect intermediate layer and character line WL0.Ladder
Structure can be formed at a wordline decoders, its be arranged at memory element NAND gate row array and
The edge of perimeter circuit.
In the example in figure 3, storage device includes connecting element and interlayer connector.Connecting element example
Ground connection as being connected in the bottom of conductive strips selects the connecting element 143 of line GSL.Interlayer is even
Stratum be e.g. coupled to the touchdown area of bottom interlayer connector 153.Interlayer connector extends
And pass through intermediate layer (character line WL0～WLN-1) connecting element in opening.Touchdown area is positioned at
Bottom surface and the connecting element of interlayer connector (e.g. interlayer connector 153) (e.g. connect unit
Part 143) the adjoiner of end face.
Several examples using the three-dimensional NAND gate memory construction of vertical channel have been described in Christian era
Total and the U.S. Patent Application No. of co-pending (co-pending) filed in 21 days Mays in 2014
" three-dimensional independent bigrid flash memory (the 3D Independent Double Gate Flash of 14/284,306
Memory) " U.S. patent application case.This case reference merge (incorporated by reference) this
Patent application case.And check and approve in JIUYUE, 2011 U.S. Patent number of 6 days 8,013,383 " bag in Christian era
Include non-volatile semiconductor storage device (the Nonvolatile Semiconductor of multiple memorizer band
Storage Device Including a Plurality of Memory Strings) " United States Patent (USP) case, disclosure
U.S. Patent Publication No. 2102/0299086 " semiconductor storage November 29 2012 Christian era
Device (Semiconductor Memory Devices) " and checked and approved January 20 2013 Christian era
U.S. Patent number 8,363,476 " storage device, manufacture method and operational approach (Memory thereof
Device, Manufacturing Method and Operating Method of the Same) " U.S. is special
Profit case is all merged by this case reference simultaneously.As described in the document that these are quoted, vertical channel memorizer is tied
The design of the various character lines of structure has been developed that, and these all may be utilized in the enforcement of the present invention
In example.
Fig. 4 is the top view of the three-dimensional memory devices using vertical channel structure.
Be connected to multiple NAND gate row of memory element by bit line BL1 13, BL2 15, BL3 17,
And BL4 19 accesses.NAND gate row has the first end and one second end.First end is by bit line even
It is connected to page buffer.Second end is connected to earth point (not shown).First end of NAND gate row
Originate in the access transistor controlled by row select line SSL1 42, SSL2 44 and SSL3 46.
It is positioned at the stacking of a specific vertical by corresponding row select line SSL1 42, SSL2 44 and SSL3 46
Selected.Row select line SSL1 42, SSL2 44 and SSL3 46 control to be positioned at specific vertical plane
Access transistor.Second end of NAND gate row is connected to earth point GND 34 having and is selected by ground connection
Select the access transistor that line GSL 32 is controlled.Different memory element along NAND gate row passes through word
Symbol line WL1 23, WL2 25, WL3 27, WL4 29 access.Character line WL1 23, WL2
25, WL3 27, WL4 29 are by the control of wordline decoders 21.
The different intermediate layer of character line is selected by interlayer connector 161,162 and 163.Interlayer
Connector 161,162 and 163 is electrically connected at the touchdown area in different intermediate layer.Depositing in array
Storage unit includes vertical channel structure 251 and memory element 252.
Fig. 5 is the schematic diagram of the Large Copacity three-dimensional memory devices using vertical channel structure.
By increasing the quantity of row select line, and by increasing the quantity of character line stacking, the three of Fig. 5
The capacity of the capacity of the dimension storage device three-dimensional memory devices more than Fig. 4.Described character line is arranged at increasing
Add on the vertical plane of quantity.Increased number of row select line includes row select line SSL1 42, SSL2
44, SSL3 46, SSL4 48, SSL5 50 and SSL6 52.Increased number of interlayer connector bag
Include interlayer connector 161,162,163,164,165 and 166.The number in the intermediate layer of character line
Amount also corresponds to the quantity of interlayer connector to be increased.By wire (e.g. conduction decoding line
(conductive decoding line) 167, interlayer connector 161,162,163,164,165,
And 166 be electrically connected between the touchdown area in wordline decoders 21 and different intermediate layer.Relatively
In the three-dimensional memory devices of the small number of stacking of Fig. 4, these increased number of stackings can increase appearance
Amount, noise, power consumption.
Fig. 6 is the schematic diagram of the another kind of Large Copacity three-dimensional memory devices using vertical channel structure.
By increasing the quantity in intermediate layer of character line, the capacity of the three-dimensional memory devices of Fig. 6 relative to
Fig. 4 increases.Corresponding to the quantity of interlayer connector, the interlayer connector of increase includes interlayer connector
171,172,173,174,175 and 176.
The quantity in the quantity of interlayer connector and the intermediate layer of character line is equal at the 5th and 6 figures.
But, the quantity of row select line (vertical of the stacking of character line) decreases.Another kind of situation is
The arrangement of touchdown area becomes degree of depth N and width 1 from the degree of depth 1 and width N.In this article, the degree of depth
Referring to the direction of character line length, width refers to the direction of bit line.By conduction decoding line 177,
Between connector 161,162,163,164,165 and 166 be electrically coupled to wordline decoders 21.
Owing to wire is crowded in small space, process complexity is far above Fig. 5.
Fig. 7 is the schematic diagram of the another kind of Large Copacity three-dimensional memory devices using vertical channel structure.
Relative to Fig. 4, by increasing the quantity in the intermediate layer of character line, the three-dimensional memory devices of Fig. 7
Capacity add.Interlayer connector increase to interlayer connector 181,182,183,184,185,
And 186.The quantity in the intermediate layer of character line also corresponds to the quantity of interlayer connector and increases.
The quantity in the quantity of interlayer connector and the intermediate layer of character line the 5th, 6,7 figures the most identical.
But, the quantity of the row select line stacking quantity of vertical plane (character line be stacked on) between Fig. 5 and
Fig. 6.The arrangement of touchdown area is not the degree of depth 1 and width N, is not degree of depth N and width 1.Instead
And, the arrangement of touchdown area is the degree of depth 2 and width N/2.In this article, the degree of depth refers to character line
The direction of length, width refers to the direction of bit line.Interlayer connector 181,182,183,184,
185 and 186 are electrically connected at wordline decoders by wire (e.g. conduction decoding line 187)
21 and different intermediate layer touchdown area between.Wire is arranged in the space bigger than Fig. 6.
This space is still less than Fig. 5, and technique is complex.
Fig. 8 is the block chart of the three-dimensional memory devices using a kind of vertical channel structure.
Three-dimensional NAND gate memory array (3D NAND memory array) 203 includes multiple and non-
Men Hang.NAND gate row is connected to memory element, and memory element is accessed by bit line.NAND gate row has
One end and the second end, the first end connects page buffer 11 through bit line, and the second end is positioned at earth point.
First end of the NAND gate row being connected to page buffer 11 has multiple access transistor, and it is subject to
The control of row select line.Row select line is by the control of row select line decoder 201.Three-dimensional NAND gate
Array is the similar arrangement of multiple two-dimensional array.Specific two-dimensional array is by selected by corresponding row select line
Selecting, this journey selects the access transistor of this two-dimensional array of line traffic control.The different storage list of NAND gate row
Unit is accessed by character line, and character line passes through word line voltages generator (word line voltage
Generator) 207 start.Layer decoder (layer decoder) and state machine circuit (state machine
Circuitry) during (not shown) is positioned at word line voltages generator 207, to control different global character
The voltage of line (global word line) 206.For example, erase, sequencing and reading program can
Control different global character lines 206 through word line voltages generator 207 and there is different voltage
To carry out erasing, the program such as sequencing and reading.Word line voltages generator 207 connects through ladder
Part (staircase contact) 205 and local word line driver (local word line driver) 209
It is electrically coupled to the local word line of three-dimensional NAND gate memory array 203.Local word line driver
Global character line 206 can be made to be electrically connected with or disconnect in three-dimensional as such as the switch of transistor
The local word line of NAND gate memory array 203.The signal of page buffer 11 to bit line, OK
Select the signal of line decoder 201 to row select line, word line voltages generator 207 via local word
The combination of the signal of symbol line drive 209 to local word line can fill pointed out in cubical array
Memory element.
Local word line driver 209 controls multiple switch, and described switch passes through ladder connector 205
Electric property coupling global character line 206 is to the local word line of three-dimensional NAND gate memory array 203.District
Block decoder (block decoder) 208 performs block decoding, to be turned on and off local word line
One group switch of driver 209.Global character line drive 207 can provide voltage to a centre
Multiple character lines of layer, local word line driver 209 is closed in being started by global character line 206
A part of character line of interbed.
The global character line 206 of the conduction come from word line voltages generator 207 is parallel to from the page
Buffer 11 and the bit line of conduction that comes.In this embodiment, SSL decoder 201 and X decoding
Device (X-decoder) 204 is positioned at the both sides of three-dimensional NAND gate memory array 203.X-decoder 204
Local word line driver 209 and block decoder 208 can be included.
In three-dimensional NAND gate memory array and ladder connector 205, dotted line represents the most absolutely
The different block of edge.Such being electrically insulated allows to select with different blocks in interbed in particular embodiments
Line (block select line) starts the local word line of part.
One block can be with erased cell minimum in right and wrong door flash memory (NAND flash).With two
For dimension NAND gate, each block has a row select line SSL/ ground connection and selects line GSL.Three
In dimension NAND gate, multiple row select line SSL and a ground connection select line GSL to may be located at single
In block.Flash memory has limited life cycle；For example, a flash memory cell is 1000
Secondary sequencing/week after date of erasing, it will crumble.In order to increase the life cycle of memory chip, each district
Digital independent/the write of block must balance.Under the block having damage, good block still can make
With.The least unit of the present invention is block (block).In two dimension NAND gate, resource block size is
NBL*NWL.In three-dimensional NAND gate, resource block size is NBL*NWL*NssL。NBLIt it is a block
The quantity of bit line.NWLIt is the quantity of the character line of a block.NSSLIt it is the row choosing of a block
Select the quantity of line SSL.
Fig. 9 is analogous to the path transistor (pass of the ladder connector of the three-dimensional storage device of Fig. 8
Transistor) simplified electrical circuit diagram.
Word line voltages generator 207 controls different global character line (e.g. global character lines
L1, L2, L3 and L4) have different voltage realize erasing, the program such as sequencing and reading.
Different global character line L1, L2, L3 and L4 is separately turned on/closes the difference of character line
Layer.Global character line L1 is electrically coupled to the first stratum (staircase step 1).Global character line
L2 is electrically coupled to the second stratum (staircase step 2).Global character line L3 is electrically coupled to
Three-layered (staircase step 3).Global character line L4 is electrically coupled to fourth order layer (staircase step
4).Different stratum is electrically coupled to the different intermediate layer of character line.As it has been described above, each stratum
Can the ladder connector (staircase that controls of Shi Shou district block selection signal (block select signal)
Contact) any set.
Block decoder 208 controls transistor and as novel word-line driver design for pseudo two-port, to switch global character line
Signal whether arrive at correspondence ladder connector and the character line intermediate layer of correspondence.Block decoder
208 signals produced are selected line (block select line) B1, B2 and B3 by the block conducted electricity
Carry.Block selects line B1, B2 and B3 to be respectively started and close the given zone of novel word-line driver design for pseudo two-port
Block, to start and to close the local word line in specific intermediate layer.Each conduction block select line B1,
B2 and B3 controls the novel word-line driver design for pseudo two-port transistor of string, and described character line drives gas transistor even
It is connected to different connector ladders (staircase of contacts).Different connector ladders is the most electric
Property insulation.Block selects line B1 to control to be connected to the one of connector ladder (contact staircase) 1
Row novel word-line driver design for pseudo two-port transistor.Block selects line B2 to control to be connected to connector ladder (contact
Staircase) the string novel word-line driver design for pseudo two-port transistor of 2.Block selects line B3 to control to be connected to connect
The string novel word-line driver design for pseudo two-port transistor of part ladder (contact staircase) 3.Connector ladder 1,
2 and 3 are mutually electrically insulated.
Figure 10 is to have path transistor (pass transistor) and use the three-dimensional of vertical channel structure
The top view of storage device.Path transistor startup is associated with a row select line of three-dimensional memory devices
Specific character line.
Word line voltages generator 207 produce signal by the global character line L1 conducted electricity, L2, L3,
Entrained by L4, L5 and L6.Global character line L1, L2, L3, L4, L5 and L6 start and
Close the different layers of character line.Global character line L1 is electrically coupled to stratum 231.Global character line
L2 is electrically coupled to stratum 232.Global character line L3 is electrically coupled to stratum 233.Global character
Line L4 is electrically coupled to stratum 234.Global character line L5 is electrically coupled to stratum 235.Global word
Symbol line L6 is electrically coupled to stratum 236.
Block decoder 208 control character line drive transistor.Novel word-line driver design for pseudo two-port transistors switch
Whether the signal of global character line arrives in the interlayer connector of correspondence and the corresponding of local word line
Interbed.For example, being positioned at block selects the character line of line B1 and global character line L1 confluce to drive
Dynamic device transistor has all around gate structure (gate all around structure), and it has and passes through dielectric
The vertical channel structure 261 of matter (dielectric) 262.The signal that block decoder 209 produces is by district
Block selects line B1, B2 and B3 to carry.Block select line B1, B2 and B3 be separately turned on
Close specific novel word-line driver design for pseudo two-port transistor, and start and the particular block closing each intermediate layer
Local word line.
Memory element in array includes vertical channel structure 251 and memory element 252.Vertical channel
Structure may be configured to the semi-conducting material of the passage as memory element, e.g. silicon (Si), germanium
(Ge), germanium silicide (SiGe), GaAs (GaAs), carbon silicide (SiC) and Graphene.
The memory element of storage device can include charge storing structure (charge storage structure), example
Multilayer dielectric charge trapping structure (multilayer dielectric charge known to flash memory technology in this way
trapping structure).Multilayer dielectric charge trapping structure e.g. ONO
(oxide-nitride-oxide)、ONONO(oxide-nitride-oxide-nitride-oxide)、SONOS
(silicon-oxide-nitride-oxide-silicon)、BE-SONOS(bandgap engineered
Silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum
Oxide, silicon nitride, silicon oxide, silicon) and MA BE-SONOS
(metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon)。
The NAND gate row connecting memory element is accessed by bit line BL1, BL2, BL3 and BL4.
Bit line selects the memory element of diverse location along local word line.The identical line that is positioned at is along in difference
The local word line select storage unit of interbed.NAND gate row has the first end.First end passes through bit line
It is connected to page buffer 11.NAND gate row has the second end.Second end is positioned at earth point.It is connected to
First end of the NAND gate row of page buffer 11 has by row select line SSL1, SSL2 and SSL3
The multiple access transistors controlled.Second end of the NAND gate row being connected to earth point has by ground connection
Select multiple access transistors that line GSL is controlled.
The first row NAND gate row is opened by earth point SSL1 and is closed.It is positioned at the first row NAND gate row
The transistor of local word line controlled by earth point B1.Second row NAND gate row is selected by row
Select line SSL2 to open and close.The transistor of the local word line being positioned at the first row NAND gate row passes through
Block selects line B2 to be controlled.The third line NAND gate row is opened by row select line SSL3 and closes.
The transistor of the local word line being positioned at the third line NAND gate row selects line B3 to be controlled by block.
Even if consequently, it is possible to the global character line voltage that word line voltages generator 207 produces is coupled to
Being positioned at multiple local word lines in same intermediate layer, block decoder 208 can only start selected
The local word line driver transistor of a part.Thereby, institute can only be started in same intermediate layer
The local word line of the part selected.For example, word line voltages generator 207 can use
The global character line L1 of conduction selects multiple local word lines in intermediate layer, top through stratum 231.
From these local word lines, block selects line B1 only to start the crystalline substance being relevant to row select line SSL1
Body pipe, block selects line B2 only to start the transistor being relevant to row select line SSL2, and block selects
Line B3 only starts the transistor being relevant to row select line SSL3.
Layer selects line (layer select line) to be parallel to character line.Row select line SSL determines vertical
Straight line width (vertical pitch).Character line and layer select line to determine horizontal live width (horizontal
pitch).Block selects the quantity of line can equal to or less than the quantity of row select line SSL.
Figure 11 be use vertical channel structure and have path transistor three-dimensional storage organization on regard
Figure.Path transistor starts the specific character line being relevant to multiple row select line.
The homotaxis of the three-dimensional memory devices of Figure 10 Yu Figure 11.But, in fig. 11, block
Decoder 208 produce signal by conduct electricity decoding line B# carry.Conduction decoding line B# starts and closes
Specific character line transistor corresponding to multiple row select line.In fig. 11, NAND gate row is complete
The novel word-line driver design for pseudo two-port transistor that portion's transistor is controlled by conduction decoding line B# opens and closes.
NAND gate row is opened by row select line SSL1, SSL2 and SSL3 and is closed.Relatively, at figure
In 10, the signal that block decoder 208 produces is selected entrained by line B1, B2 and B3 by block,
And it is separately turned on and closes the novel word-line driver design for pseudo two-port crystal of particular block corresponding to a row select line
Pipe.In other embodiments, block selects line can start and close the row choosing corresponding to other quantity
Select the novel word-line driver design for pseudo two-port transistor that the given zone of line is fast.
Figure 12 and Figure 13 is to use vertical channel structure and have the three-dimensional memory devices of path transistor
Top view and side view.Path transistor starts the word of the specific some about a row select line
Symbol line.
The portion of element of the different three-dimensional memory devices of Figure 10 and Figure 11 is described in Figure 12 in more detail
And Figure 13.Figure 12 and Figure 13 show in more detail row select line and the district of the three-dimensional memory devices of Figure 10
Block select line, e.g. row select line SSL1 and block select line B1 or row select line SSL2 and
Block selects line B2 or row select line SSL3 and block to select line B3.Figure 12 and Figure 13 is the most detailed
Carefully show that row select line and the block of the three-dimensional memory devices of Figure 11 select line, e.g. row to select
Line SSL2 and conduction decoding line B#.
Global character line L1, L2, L3, L4, L5 and L6 of conduction are respectively started and close rank
Layer 231,232,233,234,235 and 236.Conduction global character line L1, L2, L3,
L4, L5 and L6 carry respectively signal produced by word line voltages generator to stratum 231,232,
233,234,235 and 236.
Global character line L1 is coupled to the rank of interlayer connector through novel word-line driver design for pseudo two-port electric transistor
Layer 231.Global character line L2 is coupled to interlayer connector through novel word-line driver design for pseudo two-port electric transistor
Stratum 232.Global character line L3 is coupled to interlayer even through novel word-line driver design for pseudo two-port electric transistor
The stratum 233 of fitting.Global character line L4 is coupled to layer through novel word-line driver design for pseudo two-port electric transistor
Between the stratum 234 of connector.Global character line L5 couples through novel word-line driver design for pseudo two-port electric transistor
Stratum 235 in interlayer connector.Global character line L6 passes through novel word-line driver design for pseudo two-port electric transistor
It is coupled to the stratum 236 of interlayer connector.
Block decoding line (e.g. conduction decoding line B#) carry from block decoder signal with
Control character line drive transistor.The signal of novel word-line driver design for pseudo two-port transistors switch global character line is
The no interlayer connector arriving at correspondence and the corresponding intermediate layer of local word line.For example, in leading
The wire novel word-line driver design for pseudo two-port transistor of electricity decoding line B# and global character line L1 confluce has cincture
Grid structure (gate all around structure).All around gate structure has vertical channel structure 261,
It passes through the dielectric medium 262 around vertical channel structure 261.Novel word-line driver design for pseudo two-port transistor vertical
Channel architecture 261 is electrically coupled to the overall situation by conductive plunger (conductive plug) 263,264
Character line L1 and area characters line plane 231.Conduction decoding line B# and other global characters line L2,
The confluce of L3, L4, L5 and L6 also has the novel word-line driver design for pseudo two-port transistor of correspondence, and it has
All around gate structure.
Conduction decoding line B# carries the signal from block decoder, drives to start and to close character line
Dynamic device transistor and local word line.Conduction decoding line B# starts and closedown is electrically coupled to global word
Symbol line L1 and the novel word-line driver design for pseudo two-port transistor of stratum 231, be electrically coupled to global character line L2 and
The novel word-line driver design for pseudo two-port transistor of stratum 232, it is electrically coupled to global character line L3 and stratum 233
Novel word-line driver design for pseudo two-port transistor, be electrically coupled to global character line L4 and the character line of stratum 234
Driver transistor, the novel word-line driver design for pseudo two-port being electrically coupled to global character line L5 and stratum 235 are brilliant
Body pipe, it is electrically coupled to the novel word-line driver design for pseudo two-port transistor of global character line L6 and stratum 236.
The memory element of array includes vertical channel structure 251 and the storage unit accessed by bit line BL1
Part 252.Remaining bit line BL2, BL3 and BL4 also access and include vertical channel structure and storage unit
The similar memory element of part.Be connected to the NAND gate row of memory element by bit line BL1, BL2, BL3,
And BL4 is accessed.Bit line is along the difference of stratum 231,232,233,234,235 and 236
Position select storage unit.
Identical bit line is along different interlayer selecting memory element.NAND gate row has the first end.The
One end is connected to page buffer by bit line BL1, BL2, BL3 and BL4.NAND gate row has
There is the second end.Second end is positioned at earth point.It is connected to the first end tool of the NAND gate row of page buffer
There is the access transistor controlled by row select line SSL#240.Second end of NAND gate row have by
Ground connection selects the access transistor that line layer (ground select line plane) GSL 210 is controlled,
Earth point is walked to electric connection NAND gate.
NAND gate row is started by row select line SSL# and closes.The crystalline substance of the character line in NAND gate row
Body pipe is started by conduction decoding line B# and is closed.
Even if consequently, it is possible to the global character line voltage that word line voltages generator 207 produces is connected to
Multiple local word lines in same intermediate layer, block decoder 208 can only start local word line and drive
The some of dynamic device transistor, and thereby can only start the local word line of the part in same intermediate layer.
For example, the global character line L1 that word line voltages generator is electrically conductive is by stratum 231
Select crown center layer.
Figure 14 and Figure 15 is to use vertical channel structure and have membrane path transistor (thin film
Pass transistor) the top view of three-dimensional memory devices and profile.Path transistor start about
The character line of row select line.
Figure 14 has section line 312, and it is used to refer to the position of section of Figure 15.
The three-dimensional memory devices of Figure 14 is similar in appearance to the three-dimensional memory devices of Figure 11, the word of its NAND gate row
The memory element of symbol line is started by conduction decoding line B# and is closed.NAND gate row is selected by row
Line SSL1, SSL2 and SSL3 start or close.But, Figure 11 is by conducting electricity decoding line B#
The transistor controlled has all around gate structure (gate all around structure), and Figure 14 is by leading
The transistor that electricity decoding line B# is controlled is thin film transistor (TFT) (thin film transistor).
Global character line L1, L2, L3, L4, L5 and L6 carry by word line voltages generator
Generated a signal to stratum 231,232,233,234,235 and 236.Global character line L1,
L2, L3, L4, L5 and L6 are electrically coupled to conductive plunger (e.g. conductive plunger 301).Lead
Electric plug (e.g. conductive plunger 301) is electrically coupled to horizontal channel structure (horizontal channel
Structure) one first end of 310.In the top view of Figure 14, containing the one of conductive plunger 301
Row conductive plunger shows with solid line, and these row are positioned on horizontal channel structure 310.Horizontal channel structure
The material of 310 can be same as the material of vertical channel structure 251.Or, horizontal channel structure 310
And vertical channel structure 251 can be selected for different materials.Second end of horizontal channel structure 310 is electrical
It is coupled to conductive plunger (e.g. conductive plunger 302).In the top view of Figure 14, containing conduction
The string conductive plunger of connector 302 shows with deficiency and excess line, and these row are positioned under horizontal channel structure 310.
Figure 15 shows the conductive plunger 301 being positioned on horizontal channel structure 310 and is positioned at level
Conductive plunger 302 under channel architecture.
In the string conductive plunger containing conductive plunger 302, corresponding to leading of global character line L1
Electric plug is electrically coupled to the interlayer connector of stratum 231, corresponding to the conduction of global character line L2
Connector is electrically coupled to the interlayer connector of stratum 232, and the conduction corresponding to global character line L3 is inserted
Plug is electrically coupled to the interlayer connector of stratum 233, corresponding to the conductive plunger of global character line L4
It is electrically coupled to the interlayer connector of stratum 234, corresponding to the conductive plunger electricity of global character line L5
Property is coupled to the interlayer connector of stratum 235, and the conductive plunger corresponding to global character line L6 is electrical
It is coupled to the interlayer connector of stratum 236.
The interlayer connector of the not shown stratum of Figure 15 231.Similarly, cuing open in global character line L1
In face, stratum 231 is positioned on stratum 232, and the second end of horizontal channel structure 310 is by shorter
Conductive plunger 302 be connected to stratum 231.Similarly, in the section of global character line L3,
Stratum 233 is positioned under stratum 232, and the second end of horizontal channel structure 310 is by longer conduction
Connector 302 is connected to stratum 233.Similarly, in the section of global character line L4, stratum 234
Being positioned under stratum 232, the second end of horizontal channel structure 310 is by longer conductive plunger 302
It is connected to stratum 234.Similarly, in the section of global character line L5, stratum 235 is positioned at rank
Under layer 232, the second end of horizontal channel structure 310 is connected to by longer conductive plunger 302
Stratum 235.Similarly, in the section of global character line L6, stratum 236 is positioned at stratum 232
Under, the second end of horizontal channel structure 310 is connected to stratum 236 by longer conductive plunger 302.
Figure 16 and Figure 17 is another kind of employing vertical channel structure and has membrane path transistor (thin
Film pass transistor) the top view of three-dimensional memory devices and profile.Path transistor starts
Character line about row select line.Figure 16 has section line 313, and it is used to refer to the section of Figure 17
Position.
The three-dimensional memory devices of Figure 16～17 and Figure 14～15 is similar.But, the water of Figure 14～15
Flat channel architecture 310 is not extended on conductive plunger 302；In Figure 16～17, level is believed
Road structure 310 extends on conductive plunger 302.
In other embodiments, the novel word-line driver design for pseudo two-port transistor that block decoder is controlled has length
Long-channel more than 1.5 μm.
Figure 18 is the simplification block chart of the integrated circuit storage implemented according to the present invention one.
Integrated circuit 1800 includes 3 D memory array 1860, and it is positioned at surface-mounted integrated circuit.
The row that band decoder 1840 is coupled in memory array 1860 selects and ground connection selects layer
1845.Bit line decoder 1870 is connected to the bit line 1865 in memory array 1860, with read with
The memory element of programmed memory array 1860.At layer decoder/block decoder/local word line
In driver 1850, block decoder is electrically coupled to multiple squares of novel word-line driver design for pseudo two-port.Character
Line drive e.g. one transistor, it can be with electric property coupling or electrically isolated memory array 1860
In global character line and local word line.And at layer decoder/block decoder/local word line
In driver 1850, the control of layer decoder provides the sequencing to global character line, erases and read
Voltage.Address is provided to bit line decoder 1870, band decoder 1840 and layer by bus 1830
Decoder/block decoder/local word line driver 1850.Sensing amplifier and data input structure
(sense amplifiers and data-in structure) 1802 utilizes data/address bus 1875 to be coupled to position
Line decoder 1870.From sensing amplifier sensing data by DOL Data Output Line 1885 provide to
Output circuit (output circuit) 1890.Output circuit 1890 output sensing data are to integrated circuit
A destination outside 1800.Input data pass through Data In-Line (data-in line) 1805 from collection
Become the input/output port of circuit 1800 or the interiorly or exteriorly data source input of integrated circuit 1800.Number
Propped up according to source e.g. general service processor, special applications circuit, 3 D memory array 1860
Hold the module with System on Chip (system-on-a-chip) function.
In the example of Figure 18, controller 1810 controls the reading that bias arrangement 1820 provides
Or programming voltage.Controller 1810 can include storing (multi-level cell, MLC) at many levels
Sequencing and read mode.Controller 1810 can use known special applications logic circuit
(special-purpose logic circuitry).In another embodiment, controller includes at general service
Reason device (general-purpose processor).In other embodiments, controller can be general using
Processor and the combination of special applications logic circuit on the way.
Integrated circuit 1800 can support that novel word-line driver design for pseudo two-port switchs, e.g. transistor.Described crystalline substance
Body pipe is opened by block decoder and closes character line.Memory array 1860 can include
One wire.First wire is connected to the top layer of conductive strips, to select the according to row select line decoder
One given stack.Memory array 1860 can include the second wire.Second wire is electrically coupled to
Multiple intermediate layers, to select the first given stack according to block decoder.Memory array 1860 can
To include privates.Privates is electrically connected at intermediate layer, to select specific according to layer decoder
Layer.
In certain embodiments, row select line is (twisted) of distortion so that multicomponent is from row choosing
Select line and can access array.In certain embodiments, bit line is distortion so that many group bit lines are permissible
Access array.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect
Further describe it should be understood that the foregoing is only the specific embodiment of the present invention,
Be not limited to the present invention, all within the spirit and principles in the present invention, any amendment of being made,
Equivalent, improvement etc., should be included within the scope of the present invention.
Claims (20)
1. a storage device, including:
Multiple stackings (stack) that multiple conductive strips (conductive strip) are formed, described in lead
Electricity band crisscrosses multiple insulated strand (insulating strip), and described stacking includes described bus
Band a bottom (bottom layer), multiple intermediate layers (intermediate layer) of described conductive strips,
And a top layer (top layer) of described conductive strips；
Multiple semiconductor vertical body structures (semiconductive vertical structure), with described heap
Folded orthogonal；
Multiple memory elements (memory element), are positioned at described stacking and tie with described semiconductor vertical
Multiple neighboring regions of multiple plotted points of the side surface of structure；
Multiple first wires, open in order to control to be positioned at multiple transistors of this top layer of described conductive strips
Close (transistor switch)；
Multiple second wires, in order to control multiple local word line driver switch (local word line
driver switch)；And
Multiple privates, including multiple global character lines (global word line), described global word
Symbol line is electrically coupled to described intermediate layer by described local word line driver switch.
Store device the most as claimed in claim 1, it is characterised in that also include:
One control circuit (control circuitry), in order to make described first wire select described stacking
At least one first given stack (first particular stack), make described second wire select described heap
This folded at least one first given stack also makes described privates select the specific of described intermediate layer
Layer (particular layer).
Store device the most as claimed in claim 1, it is characterised in that described local word line drives
Dynamic device switch is multiple transistors (transistor), and described transistor has multiple side grid (lateral
Gate), described side grid be positioned at multiple lateral conduction passage (lateral conductive channel) it
On, described lateral conduction passage is electrically coupled to described conductive strips and described privates.
Store device the most as claimed in claim 1, it is characterised in that described local word line drives
Dynamic device switch is multiple transistors, and described transistor has around vertical conduction passage (vertical
Conductive channel) multiple grid (gate), described vertical conduction passage is electrically coupled to described
Conductive strips and described privates.
Store device the most as claimed in claim 1, it is characterised in that different described intermediate layers
It is electrically coupled to different multiple ladder contacts (staircase contact), and different the described 3rd leads
Line is electrically coupled to different described ladder contacts.
Store device the most as claimed in claim 1, it is characterised in that described second wire includes
One specific decoding line (particular decoding line), stacks described in this specific decoding line options many
Individual, selected described stacking is electrically coupled to the one first multiple set of described first wire, should
Different described first wire of the first set selects different described stackings.
Store device the most as claimed in claim 1, it is characterised in that the one of described second wire
First conduction decoding line only selects one of them of described stacking.
Store device the most as claimed in claim 1, it is characterised in that also include:
One controls loop, in order to make described first wire select at least one first specific heap of described stacking
Fold, make described second wire select this at least one first given stack of described stacking and not select institute
State other parts of stacking and make described privates select at least one certain layer in described intermediate layer also
And do not select other parts in described intermediate layer.
Store device the most as claimed in claim 1, it is characterised in that also include:
Multiple privates, including multiple bit lines, bit line is electrically coupled to described semiconductor vertical structure,
Wherein a control loop makes described privates select a subset of described semiconductor vertical structure
Closing, this subclass is arranged in string, and these row are orthogonal to described stacking.
Store device the most as claimed in claim 9, it is characterised in that described privates is parallel
In described privates.
11. store device as claimed in claim 1, it is characterised in that also include:
One first decoder, is electrically coupled to described first wire；And
One second decoder, is electrically coupled to described second wire, wherein this first decoder and this
Two decoders are positioned at the stacked on one first relative side of described heap and one second side, and described first conductor flat
Row is in described second wire.
12. 1 kinds of operational approach storing device, including:
Multiple first wire is made to select at least one first given stack (first particular of multiple stackings
Stack), described stacking is made up of multiple conductive strips (conductive strip), described bus
Band crisscrosses multiple insulated strand (insulating strip), and wherein said stacking includes described bus
One bottom, multiple intermediate layers of described conductive strips and a top layer of described conductive strips, the institute of band
State the first polygon control survey and be positioned at multiple transistor switches (transistor switch) of this top layer；
Make multiple second polygon control survey multiple local word line driver switch (local word line
Driver switch), to select this at least one first given stack of described stacking；And
Described privates is made to select described intermediate layer by described local word line driver switch
At least one certain layer (particular layer), described privates includes multiple global character line (global
Word line),
Wherein said first wire, described second wire and described privates assist multiple memory elements
At least one selection, described memory element is positioned at described stacking and multiple semiconductor vertical structures
Multiple neighboring regions of multiple plotted points of the side surface of (semiconductive vertical structure),
Described semiconductor vertical structure is orthogonal to described stacking.
13. operational approach storing device as claimed in claim 12, it is characterised in that described
Local word line driver switch is multiple transistors, and described transistor has multiple side grid (lateral
Gate), described side grid be positioned at multiple lateral conduction passage (lateral conductive channel) it
On, described lateral conduction passage is electrically coupled to described conductive strips and described privates.
14. operational approach storing device as claimed in claim 12, it is characterised in that described
Local word line driver switch is multiple transistors, and described transistor has around vertical conduction logical
Multiple grid (gate) in road (vertical conductive channel), described vertical conduction passage is electrical
It is coupled to described conductive strips and described privates.
15. operational approach storing device as claimed in claim 12, it is characterised in that different
Described intermediate layer be electrically coupled to different multiple ladder contacts (staircase contact), and different
Described privates be electrically coupled to different described ladder contacts.
16. operational approach storing device as claimed in claim 12, it is characterised in that described
Second wire includes a specific decoding line (particular decoding line), this specific decoding line options
Described stacking multiple, selected described stacking is electrically coupled to multiple one of described first wire
First set, different described first wire of this first set selects different described stackings.
17. operational approach storing device as claimed in claim 12, it is characterised in that described
One first conduction decoding line of the second wire only selects one of them of described stacking.
18. operational approach storing device as claimed in claim 12, it is characterised in that also wrap
Include:
Described first wire is made to select at least one first given stack of described stacking, make described second to lead
This at least one first given stack of stacking described in line options and other parts of described stacking making
Described privates selects at least one certain layer in described intermediate layer and does not select described intermediate layer
Other parts.
19. operational approach storing device as claimed in claim 12, it is characterised in that also wrap
Include:
Making multiple privates select a subclass of described semiconductor vertical structure, subclass is arranged in
String, these row are orthogonal to described stacking.
20. operational approach storing device as claimed in claim 19, it is characterised in that described
Privates is parallel to described privates.
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| US12073883B2 (en) | 2022-05-11 | 2024-08-27 | Macronix International Co., Ltd. | Ternary content addressable memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12073883B2 (en) | 2022-05-11 | 2024-08-27 | Macronix International Co., Ltd. | Ternary content addressable memory |
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| CN106158021B (en) | 2020-02-18 |
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