CN106098781B - A kind of VDMOS of groove structure - Google Patents
A kind of VDMOS of groove structure Download PDFInfo
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- CN106098781B CN106098781B CN201610676906.4A CN201610676906A CN106098781B CN 106098781 B CN106098781 B CN 106098781B CN 201610676906 A CN201610676906 A CN 201610676906A CN 106098781 B CN106098781 B CN 106098781B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 73
- 229920005591 polysilicon Polymers 0.000 claims abstract description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 34
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 33
- 230000007423 decrease Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 6
- 238000001727 in vivo Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000003860 storage Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004408 titanium dioxide Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to technical field of semiconductors, more particularly to a kind of VDMOS device of groove structure.The present invention mainly has two or more polysilicon islands that silicon dioxide layer is wrapped in groove in vivo, and negative electrical charge is store in these polysilicon islands.Since polysilicon island is surrounded by insulating layer, negative electrical charge will be fixed in polysilicon island.The negative charge density stored in each polysilicon island differs, and higher closer to the charge density of the polysilicon island of device surface storage.When device reverse blocking, transverse electric field, assisted depletion drift region are generated in the N-type drift region of high potential and polysilicon island between negative electrical charge.Since the potential of N-type drift region continuously decreases from the bottom to top, and the quantity of electric charge of negative electrical charge increases from the bottom to top, and the transverse electric field distribution for making drift region evenly, to which longitudinal electric field is closer to distributed rectangular, improves the reverse BV of device.Simultaneously as not using the body field plate structure being connected with source electrode, the gate leakage capacitance Cds in the present invention is relatively low.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of VDMOS device of groove structure.
Background technology
Power VDMOSFET is more subconductivity devices, has many advantages, such as that switching speed is fast, input impedance is high, easy driving.Preferably
VDMOS should have lower conducting resistance, switching loss and higher blocking voltage.But it conducting resistance and breakdown voltage, leads
Being powered between resistance and switching loss, there is restraining functions, limit the development of power VDMOSFET.In order to improve device performance, subtract
Small conducting resistance, the Chen Xing academicians that assist propose hyperconjugation VDMOS structure.Traditional structure is compared, super-junction structure obtains more excellent
The tradeoff of device pressure resistance and conducting resistance, under conditions of identical device pressure resistance, the electric conduction of the VDMOS of super-junction structure
Hinder smaller.
Since super-junction structure VDMOS is extremely sensitive for the charge balance of P/N columns, and the P/N columns in actual process
Minimum widith limits the reduction of cellular size, therefore, patent No. US6710,403 propose served as using polysilicon it is internal
Field plate structure substitutes P/N columns to reduce drift region conducting resistance, avoids the influence of charge balance, structure chart as shown in Figure 1.By
It is connected with source electrode in the current potential of polysilicon, when body field plate type VDMOS is reversely pressure-resistant, polysilicon current potential is low potential, N-type drift region
Transverse electric field is formed between field plate, which plays the role of assisted depletion N-type drift region, generates similar super-junction structure
Effect, can make device that the drift region of more high impurity concentration can be used while with high voltage.But body field plate type
VDMOS is there is also certain disadvantage, and the longitudinal electric field distribution in drift region is as shown in Figure 1, it can be seen that due to entire field plate
On current potential it is identical, the longitudinal electric field value in drift region declines along vertical direction, constrains further increasing for reversed pressure resistance.
Simultaneously as body field plate is connected with the source electrode of VDMOS, source drain capacitance Cds can be higher, affects the dynamic characteristic of device.
Invention content
It is to be solved by this invention, it is reversed resistance in order to preferably improve aiming at the above problem of body field plate type VDMOS
The trade-off relation of pressure and conducting resistance improves the reversed pressure resistance of device under conditions of identical conducting resistance, it is proposed that a kind of
The VDMOS of groove structure.
The technical scheme is that：A kind of VDMOS of groove structure, including the metal that is cascading from bottom to up
Change drain electrode 11, N+ substrates 1, the drift regions N- 2 and metallizing source 4；There is internal groove 3, p-type to adulterate in the drift regions N- 2
Area 5, N-type heavily doped region 6, p-type heavily doped region 7 and groove 8, the P-doped zone 5 are located between the internal groove 3 of both sides, and
The side of P-doped zone 5 is contacted with the side of internal groove 3；The N-type heavily doped region 6 is located at the upper surface of P-doped zone 5,
The upper surface of N-type heavily doped region 6 is contacted with the lower surface of metallizing source 4；The p-type heavily doped region 7 be located at internal groove 3 with
It is contacted between N-type heavily doped region 6 and respectively at internal groove 3 and N-type heavily doped region 6；The upper surface of the internal groove 3 and gold
The lower surface of categoryization source electrode 4 contacts；The upper surface of the groove 8 is contacted with the lower surface of metallizing source 4, the lower end of groove 8
It vertically sequentially passes through N-type heavily doped region 6 and p-type heavily doped region 7 and extends in the drift regions N- 2, filled out in the groove 8
Filled with the first silicon dioxide layer 9, there is polysilicon 10 in the first silicon dioxide layer 9；It is characterized in that, the internal groove 3
In be filled with the second silicon dioxide layer 12, there is in second silicon dioxide layer 12 multiple polysilicon islands 13, the polysilicon
Island 13 is vertically arranged in order, and the following table of P-doped zone 5 is not higher than positioned at the upper surface of the polysilicon island of the top
Face is stored with negative electrical charge in the polysilicon island 13, along device vertical direction, the negative charge density that is stored in each polysilicon island
It gradually decreases.
A kind of VDMOS of groove structure, including the metalized drain 11, P+ substrates 1, the P- that are cascading from bottom to up
Drift region 2 and metallizing source 4；There is internal groove 3, N-doped zone 5, p-type heavily doped region 6, N-type in the drift regions P- 2
Heavily doped region 7 and groove 8, the N-doped zone 5 is located between the internal groove 3 of both sides, and the side of N-doped zone 5 and body
The side of internal channel 3 contacts；The p-type heavily doped region 6 is located at the upper surface of N-doped zone 5, the upper surface of p-type heavily doped region 6
It is contacted with the lower surface of metallizing source 4；The N-type heavily doped region 7 is between internal groove 3 and p-type heavily doped region 6 and divides
It is not contacted in internal groove 3 and p-type heavily doped region 6；The upper surface and the lower surface of metallizing source 4 of the internal groove 3 connect
It touches；The upper surface of the groove 8 is contacted with the lower surface of metallizing source 4, and the lower end of groove 8 vertically sequentially passes through P
Type heavily doped region 6 and N-type heavily doped region 7 simultaneously extend in the drift regions P- 2, and the first silicon dioxide layer is filled in the groove 8
9, there is polysilicon 10 in the first silicon dioxide layer 9；It is characterized in that, being filled with the second titanium dioxide in the internal groove 3
Silicon layer 12, has multiple polysilicon islands 13 in second silicon dioxide layer 12, and the polysilicon island 13 is vertically successively
It arranges, and is not higher than the lower surface of N-doped zone 5 positioned at the upper surface of the polysilicon island of the top, in the polysilicon island 13
It is stored with positive charge, along device vertical direction, the positive charge density stored in each polysilicon island gradually decreases.
Further, the thickness of the first silicon dioxide layer 9 between 8 side wall of the polysilicon 10 and groove is 5-100nm,
The thickness of the first silicon dioxide layer 9 between 8 lower surface of polysilicon 10 and groove is 200-500nm.
Further, between the adjacent polysilicon island 13 and between 3 side wall of polysilicon island 13 and internal groove
Second silicon dioxide layer, 12 thickness is 50-200nm, the polysilicon island 13 of bottom and in vivo second between 3 lower surface of groove
12 thickness of silicon dioxide layer is 200-500nm.
Beneficial effects of the present invention are that a kind of VDMOS of groove structure provided by the present invention has two in groove in vivo
Two or more polysilicon islands that silicon oxide layer is wrapped in store negative electrical charge in these polysilicon islands.Due to polycrystalline
Silicon island is surrounded by insulating layer, and negative electrical charge will be fixed in polysilicon island.The negative charge density stored in each polysilicon island differs,
And it is higher closer to the charge density of the polysilicon island of device surface storage.When device reverse blocking, the N-type of high potential is drifted about
Transverse electric field, assisted depletion drift region are generated in area and polysilicon island between negative electrical charge.Since the potential of N-type drift region is under
It is supreme to continuously decrease, and the quantity of electric charge of negative electrical charge increases from the bottom to top, make the transverse electric field distribution of drift region evenly, to vertical
To electric field closer to distributed rectangular, the reverse BV of device is improved.Simultaneously as not using the body being connected with source electrode
Field plate structure, the present invention in gate leakage capacitance Cds it is relatively low.
Description of the drawings
Fig. 1 is a kind of VDMOS structural schematic diagrams with internal field plate that patent No. US6710,403 is provided and its anti-
Field distribution schematic diagram in drift region when to bias.
Fig. 2 is a kind of VDMOS structural schematic diagrams of groove structure provided by the invention.
Fig. 3 is a kind of VDMOS structures of groove structure provided by the invention exhausting in the drift region in reverse biased
Line and electric field
Fig. 4-Figure 10 is a kind of critical process step of the VDMOS structure fabrications of groove structure provided by the invention.
Specific implementation mode
With reference to the accompanying drawings and examples, detailed description of the present invention technical solution：
Embodiment 1
As shown in figure 3, a kind of VDMOS of groove structure of this example, including the metallization that is cascading from bottom to up
Drain electrode 11, N+ substrates 1, the drift regions N- 2 and metallizing source 4；There is internal groove 3, P-doped zone in the drift regions N- 2
5, N-type heavily doped region 6, p-type heavily doped region 7 and groove 8, the P-doped zone 5 is located between the internal groove 3 of both sides, and P
The side of type doped region 5 is contacted with the side of internal groove 3；The N-type heavily doped region 6 is located at the upper surface of P-doped zone 5, N
The upper surface of type heavily doped region 6 is contacted with the lower surface of metallizing source 4；The p-type heavily doped region 7 is located at internal groove 3 and N
It is contacted between type heavily doped region 6 and respectively at internal groove 3 and N-type heavily doped region 6；The upper surface of the internal groove 3 and gold
The lower surface of categoryization source electrode 4 contacts；The upper surface of the groove 8 is contacted with the lower surface of metallizing source 4, the lower end of groove 8
It vertically sequentially passes through N-type heavily doped region 6 and p-type heavily doped region 7 and extends in the drift regions N- 2, filled out in the groove 8
Filled with the first silicon dioxide layer 9, there is polysilicon 10 in the first silicon dioxide layer 9；It is characterized in that, the internal groove 3
In be filled with the second silicon dioxide layer 12, there is in second silicon dioxide layer 12 multiple polysilicon islands 13, the polysilicon
Island 13 is vertically arranged in order, and the following table of P-doped zone 5 is not higher than positioned at the upper surface of the polysilicon island of the top
Face is stored with negative electrical charge in the polysilicon island 13, along device vertical direction, the negative charge density that is stored in each polysilicon island
It gradually decreases.
Illustrate the operation principle of the present embodiment in terms of two below：
(1) forward conduction of device
A kind of VDMOS of groove structure provided by the present invention, electrode connection mode when forward conduction are：Polysilicon
10 positive potential of gate electrode, metalized drain 11 connect positive potential, and metallizing source 4 connects zero potential.Added by polygate electrodes 10
Positive voltage is equal to or more than after cut-in voltage, and how sub- electronics is under the action of 11 positive potential of metalized drain from N-type heavy doping
Area 6 flows to metalized drain 11.Since the gate oxide of 4 bottom of groove profile gate electrode takes thick oxygen technique, so gate leakage capacitance Cgd
Obtain larger improvement.Simultaneously as not using the body field plate that is connected with source electrode, compared to patent No. US6710, in 403
Using field plate techniques in source electrode body, the source drain capacitance Cds in the present invention is reduced.
(2) reverse blocking of device
A kind of VDMOS of groove structure provided by the present invention, electrode connection mode when reverse blocking are：Polysilicon
Gate electrode 10 and 4 short circuit of metallizing source and zero potential is connect, metalized drain 11 connects positive potential.
When device is reversely pressure-resistant, there is laterally electricity between the fixed negative charge in polysilicon 13 in the drift regions N- and slot 3
, the drift regions assisted depletion N-.At this point, the metalized drain of VDMOS connects high potential, metallizing source connects low potential, then N- floats
The potential of area from the bottom to top is moved to continuously decrease, and the fixed negative charge amount in several piece polysilicon 13 is increased from the bottom to top so that
Transverse electric field intensity between the drift regions N- and fixed negative charge is held essentially constant along vertical direction.Therefore drift region is vertical
It will be closer to distributed rectangular, as shown in Figure 3 to field distribution.When device compared to patent No. US6710,403 is reversely pressure-resistant
Field distribution on N- drift region verticals direction, electric field slope reduce, and the area that field distribution E (Y) encloses between Y-axis increases,
Reverse blocking pressure resistance improves.
A kind of manufacturing process flow of the VDMOS of groove structure of the present embodiment a kind of is as follows：
1, monocrystalline silicon preparation and epitaxial growth.Using N-type heavy doping monocrystalline substrate 1, using the methods of vapour phase epitaxy VPE
The drift regions N- 2 of certain thickness and doping concentration are grown, and one layer of thin oxide layer is formed on surface, as shown in Figure 4.
2, etching forms internal deep trouth 3.
3, silicon dioxide layer is grown in slot 3, forms dioxide layer 12, then the certain thickness polycrystalline of deposit in slot 3
Silicon 13 carries out anion injection, makes polysilicon 13 with fixed negative charge.As shown in Figure 5.
4, filling oxide layer in the trench.
5, step 3 and 4 is repeated, polysilicon 13 of the several piece with fixed negative charge is formed, is isolated between adjacent polysilicon 13
Silicon dioxide layer 12, the upper surface of the polysilicon of the top is no more than the lower surface of P-doped zone 5.
6, the extra polysilicon of silicon chip surface is etched away, silica is deposited in silicon chip surface, forms the titanium dioxide in slot 3
The top of silicon layer 12, as shown in Figure 6.
7,5 window of P-doped zone is formed using photoetching process, carries out boron injection, form P-doped zone 5, as shown in Figure 7.
8, photoetching N-type injection region window carries out N-type phosphorus injection, forms N-type heavily doped region 6, as shown in Figure 8.
9, etching forms slot 8, and somatomedin layer forms bottom and the side wall of silicon dioxide layer 9, then depositing polysilicon 10
Gate electrode is formed, as shown in Figure 9.
10, oxide layer is grown, carrying out ion etching using photolithography plate forms window, injects boron, forms p-type heavily doped region 7,
As shown in Figure 10.
11, it metallizes.Etch away extra oxide layer, front-side metallization, metal etch, back metal, passivation etc..
Embodiment 2
The structure of this example replaces with P-type material on the basis of embodiment 1, by all n type materials in embodiment 1, institute
Some P-type materials replace with n type material, and the negative electrical charge in polysilicon 13 replaces with positive charge.
When making devices, the semi-conducting materials substituted for silicon such as silicon carbide, GaAs or germanium silicon also can be used.
Claims (6)
1. a kind of VDMOS of groove structure, including be cascading from bottom to up metalized drain (11), N+ substrates (1),
The drift regions N- (2) and metallizing source (4)；There is internal groove (3), P-doped zone (5), N-type in the drift regions N- (2)
Heavily doped region (6), p-type heavily doped region (7) and groove (8), the P-doped zone (5) be located at both sides internal groove (3) it
Between, and the side of P-doped zone (5) is contacted with the side of internal groove (3)；The N-type heavily doped region (6) is located at p-type doping
The upper surface of the upper surface in area (5), N-type heavily doped region (6) is contacted with the lower surface of metallizing source (4)；The p-type heavy doping
Area (7) connects between internal groove (3) and N-type heavily doped region (6) and respectively with internal groove (3) and N-type heavily doped region (6)
It touches；The upper surface of the internal groove (3) is contacted with the lower surface of metallizing source (4)；The upper surface of the groove (8) and gold
The lower surface of categoryization source electrode (4) contacts, and the lower end of groove (8) vertically sequentially passes through N-type heavily doped region (6) and p-type weight
Doped region (7) simultaneously extends in the drift regions N- (2), the first silicon dioxide layer (9) is filled in the groove (8), the one or two
There is polysilicon (10) in silicon oxide layer (9)；It is characterized in that, being filled with the second silicon dioxide layer in the internal groove (3)
(12), there are multiple polysilicon islands (13), the polysilicon island (13) is vertically in second silicon dioxide layer (12)
It is arranged in order, and is not higher than the lower surface of P-doped zone (5), the polysilicon positioned at the upper surface of the polysilicon island of the top
Island is stored with negative electrical charge in (13), and when device is reversely pressure-resistant, the potential of the drift regions N- (2) from the bottom to top continuously decreases, multiple
Fixed negative charge amount in polysilicon island (13) increases from the bottom to top.
2. a kind of VDMOS of groove structure according to claim 1, which is characterized in that the polysilicon (10) and groove
(8) thickness of the first silicon dioxide layer (9) between side wall is 5-100nm, between polysilicon (10) and groove (8) lower surface
The thickness of first silicon dioxide layer (9) is 200-500nm.
3. a kind of VDMOS of groove structure according to claim 2, which is characterized in that the adjacent polysilicon island
(13) the second silicon dioxide layer (12) thickness between and between polysilicon island (13) and internal groove (3) side wall is 50-
200nm, the second silicon dioxide layer (12) thickness between the polysilicon island (13) and internal groove (3) lower surface of bottom are
200-500nm。
4. a kind of VDMOS of groove structure, including be cascading from bottom to up metalized drain (11), P+ substrates (1),
The drift regions P- (2) and metallizing source (4)；There is internal groove (3), N-doped zone (5), p-type in the drift regions P- (2)
Heavily doped region (6), N-type heavily doped region (7) and groove (8), the N-doped zone (5) be located at both sides internal groove (3) it
Between, and the side of N-doped zone (5) is contacted with the side of internal groove (3)；The p-type heavily doped region (6) is located at n-type doping
The upper surface of the upper surface in area (5), p-type heavily doped region (6) is contacted with the lower surface of metallizing source (4)；The N-type heavy doping
Area (7) connects between internal groove (3) and p-type heavily doped region (6) and respectively with internal groove (3) and p-type heavily doped region (6)
It touches；The upper surface of the internal groove (3) is contacted with the lower surface of metallizing source (4)；The upper surface of the groove (8) and gold
The lower surface of categoryization source electrode (4) contacts, and the lower end of groove (8) vertically sequentially passes through p-type heavily doped region (6) and N-type weight
Doped region (7) simultaneously extends in the drift regions P- (2), the first silicon dioxide layer (9) is filled in the groove (8), the one or two
There is polysilicon (10) in silicon oxide layer (9)；It is characterized in that, being filled with the second silicon dioxide layer in the internal groove (3)
(12), there are multiple polysilicon islands (13), the polysilicon island (13) is vertically in second silicon dioxide layer (12)
It is arranged in order, and is not higher than the lower surface of N-doped zone (5), the polysilicon positioned at the upper surface of the polysilicon island of the top
Island is stored with positive charge in (13), and when device is reversely pressure-resistant, the potential of the drift regions P- (2) from the bottom to top continuously decreases, multiple
Fixed positive charge amount in polysilicon island (13) increases from the bottom to top.
5. a kind of VDMOS of groove structure according to claim 4, which is characterized in that the polysilicon (10) and groove
(8) thickness of the first silicon dioxide layer (9) between side wall is 5-100nm, between polysilicon (10) and groove (8) lower surface
The thickness of first silicon dioxide layer (9) is 200-500nm.
6. a kind of VDMOS of groove structure according to claim 5, which is characterized in that the adjacent polysilicon island
(13) the second silicon dioxide layer (12) thickness between and between polysilicon island (13) and internal groove (3) side wall is 50-
00nm, the second silicon dioxide layer (12) thickness between the polysilicon island (13) and internal groove (3) lower surface of bottom are
200-500nm。
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| CN109065627A (en) * | 2018-08-21 | 2018-12-21 | 电子科技大学 | A kind of LDMOS device with polysilicon island |
| CN109119488A (en) * | 2018-08-24 | 2019-01-01 | 电子科技大学 | A kind of metal-oxide-semiconductor diode with polysilicon island |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102005041322A1 (en) * | 2005-08-31 | 2007-03-01 | Infineon Technologies Ag | Trench transistor structure, with a field electrode array in the trenches, has a potential fixed for the field electrodes through semiconductor zones |
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| US7132712B2 (en) * | 2002-11-05 | 2006-11-07 | Fairchild Semiconductor Corporation | Trench structure having one or more diodes embedded therein adjacent a PN junction |
| US7514743B2 (en) * | 2005-08-23 | 2009-04-07 | Robert Kuo-Chang Yang | DMOS transistor with floating poly-filled trench for improved performance through 3-D field shaping |
| KR20090116702A (en) * | 2007-01-09 | 2009-11-11 | 맥스파워 세미컨덕터 인크. | Semiconductor device |
| WO2011087994A2 (en) * | 2010-01-12 | 2011-07-21 | Maxpower Semiconductor Inc. | Devices, components and methods combining trench field plates with immobile electrostatic charge |
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| DE102005041322A1 (en) * | 2005-08-31 | 2007-03-01 | Infineon Technologies Ag | Trench transistor structure, with a field electrode array in the trenches, has a potential fixed for the field electrodes through semiconductor zones |
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