CN106098016A - Scan drive circuit and there is the flat display apparatus of this circuit - Google Patents
Scan drive circuit and there is the flat display apparatus of this circuit Download PDFInfo
- Publication number
- CN106098016A CN106098016A CN201610717822.0A CN201610717822A CN106098016A CN 106098016 A CN106098016 A CN 106098016A CN 201610717822 A CN201610717822 A CN 201610717822A CN 106098016 A CN106098016 A CN 106098016A
- Authority
- CN
- China
- Prior art keywords
- gate
- controlled switch
- signal
- control
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of scan drive circuit and flat display apparatus, scan drive circuit includes multiple scan drive cells of cascade, and each scan drive cell includes that first and second input circuit receives the first clock signal and drives signal and export first and second input signal；Pull-down circuit receives second clock signal and exports pulldown signal and drop-down control signal point carries out drop-down or charging；First and second control circuit receives first and second input signal and charges first and second pull-up control signal point, or it is drop-down to first and second pull-up control signal point to receive pulldown signal；First output circuit receives the 3rd clock signal and produces the first scanning drive signal to the first scan line to drive pixel cell；Second output circuit receives the 4th clock signal and produces the second scanning drive signal to the second scan line to drive pixel cell, the circuit realizing simplifying flat display apparatus with this, saves space, and then the narrow frame design of beneficially flat display apparatus.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of scan drive circuit and have this circuit plane show
Showing device.
Background technology
Current flat display apparatus uses scan drive circuit, namely utilizes existing thin film transistor (TFT) plane to show
Scan drive circuit is produced on array base palte by device array process, it is achieved the type of drive to progressive scan.Existing plane
In display device, every scan driving circuit only drives a scan line, and arranges all multi-strip scannings in general closed planar display device
Line, needs are designed many scan drive circuits, certainly will make complex circuit designs, and take up room by this, are unfavorable for that plane shows
The narrow frame design of showing device.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of scan drive circuit and has the plane of this circuit and show
Device, to simplify the circuit of flat display apparatus, saves space, and then the narrow frame design of beneficially flat display apparatus.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of scan drive circuit, institute
Stating scan drive circuit and include multiple scan drive cells of cascade, each described scan drive cell includes:
First input circuit, for receiving the first clock signal and driving signal and export the first input signal；
Second input circuit, for receiving the first clock signal and driving signal and export the second input signal；
Pull-down circuit, be used for receiving second clock signal and export pulldown signal and according to described second clock signal under
Control signal point is drawn to carry out drop-down or charging；
First control circuit, for receiving described first input signal and according to described first from described first input circuit
First pull-up control signal point is charged by input signal, or receives described pulldown signal basis from described pull-down circuit
Described first pull-up control signal point is carried out drop-down by described pulldown signal；
Second control circuit, for receiving described second input signal and according to described second from described second input circuit
Second pull-up control signal point is charged by input signal, or receives described pulldown signal basis from described pull-down circuit
Described second pull-up control signal point is carried out drop-down by described pulldown signal；
First output circuit, for receiving the 3rd clock signal and driving according to described 3rd clock signal generation the first scanning
Dynamic signal exports to the first scan line to drive pixel cell；And
Second output circuit, for receiving the 4th clock signal and driving according to described 4th clock signal generation the second scanning
Dynamic signal exports to the second scan line to drive pixel cell.
Wherein, described first input circuit includes the first gate-controlled switch, and the control end of described first gate-controlled switch receives institute
Stating the first clock signal, the first end of described first gate-controlled switch receives described driving signal, the of described first gate-controlled switch
Two ends connect described pull-down circuit and described first control circuit.
Wherein, described pull-down circuit includes the second to the 8th gate-controlled switch and the first electric capacity, described second gate-controlled switch
Control end and connect the second end of described first gate-controlled switch, the first end of described 3rd gate-controlled switch and described first control electricity
Road, the first end of described second gate-controlled switch receives closes voltage end signal, and the second end of described second gate-controlled switch connects institute
State the 3rd gate-controlled switch control end, described 4th gate-controlled switch control end, the control end of described 7th gate-controlled switch, described
Control end, the first end of described 5th gate-controlled switch and second end of described 6th gate-controlled switch of the 8th gate-controlled switch, described
Second end of the 3rd gate-controlled switch connects the first end of described 4th gate-controlled switch, the second end of described 7th gate-controlled switch and institute
State the first end of the 8th gate-controlled switch, described 4th gate-controlled switch second end connect described 5th gate-controlled switch control end,
Described second input circuit and described second control circuit, the second end of described 5th gate-controlled switch receives described closedown voltage end
Signal, the control end of described 6th gate-controlled switch receives described second clock signal, the first termination of described 6th gate-controlled switch
Receiving cut-in voltage end signal, the first end of described 7th gate-controlled switch connects described first output circuit, and the described 8th controlled opens
The second end closed connects described second output circuit, and described first electric capacity is connected to first end and the of described 6th gate-controlled switch
Between two ends.
Wherein, described first control circuit includes the 9th gate-controlled switch, and the control end of described 9th gate-controlled switch receives institute
Stating cut-in voltage end signal, the first end of described 9th gate-controlled switch connects the control end and described the of described second gate-controlled switch
First end of three gate-controlled switches, the second end of described 9th gate-controlled switch connects described first output circuit.
Wherein, described first output circuit includes the tenth gate-controlled switch and the second electric capacity, the control of described tenth gate-controlled switch
End processed connects the second end of described 9th gate-controlled switch, and the first end of described tenth gate-controlled switch receives described 3rd clock letter
Number, the second end of described tenth gate-controlled switch connects described first scan line and the first end of described 7th gate-controlled switch, described
Second electric capacity is connected between control end and second end of described tenth gate-controlled switch.
Wherein, described second input circuit includes the 11st gate-controlled switch, the control termination of described 11st gate-controlled switch
Receiving described first clock signal, the first end of described 11st gate-controlled switch receives described driving signal, described 11st controlled
Second end of switch connects the control end of described 5th gate-controlled switch.
Wherein, described second control circuit includes the 12nd gate-controlled switch, the control termination of described 12nd gate-controlled switch
Receive described cut-in voltage end signal, described 12nd gate-controlled switch first end connect described 4th gate-controlled switch the second end and
The control end of described 5th gate-controlled switch, the second end of described 12nd gate-controlled switch connects described second output circuit.
Wherein, described second output circuit includes the 13rd gate-controlled switch and the 3rd electric capacity, described 13rd gate-controlled switch
Control end connect described 12nd gate-controlled switch the second end, described 13rd gate-controlled switch first end connect described second
Scan line and the second end of described 8th gate-controlled switch, the second end of described 13rd gate-controlled switch receives described 4th clock letter
Number, described 3rd electric capacity is connected between control end and first end of described 13rd gate-controlled switch.
Wherein, described first to the 13rd gate-controlled switch is N-type TFT, described first to the 13rd gate-controlled switch
The grid, drain electrode and the source electrode that control end, the first end and the second end corresponding described N-type TFT respectively；Or described
One to the 13rd gate-controlled switch is P-type TFT, the control end of the described first to the 13rd gate-controlled switch, the first end and
Grid, drain electrode and the source electrode of two ends corresponding described P-type TFT respectively.
For solving above-mentioned technical problem, another technical solution used in the present invention is: provide a kind of flat display apparatus,
Described flat display apparatus includes the scan drive circuit as described in any of the above-described.
The invention has the beneficial effects as follows: be different from the situation of prior art, the scan drive circuit of the present invention of the present invention
By first and second input circuit and first and second control circuit, first and second pull-up control signal point is filled
Electricity, and realize the drop-down control to drop-down control signal point by arranging a pull-down circuit, exported by first and second
Circuit export first and second scanning drive signal be respectively supplied to first and second scan line drive correspondence pixel cell,
The circuit realizing simplifying flat display apparatus with this, saves space, and then the narrow frame design of beneficially flat display apparatus.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a scan drive cell of scan drive circuit in prior art；
Fig. 2 is the working timing figure of scan drive cell in prior art；
Fig. 3 is the circuit diagram of the first embodiment of a scan drive cell of the scan drive circuit of the present invention；
Fig. 4 is double working timing figures driven of the scan drive cell of Fig. 3；
Fig. 5 is the interleaved working timing figure of the scan drive cell of Fig. 3；
Fig. 6 is double software emulation result figures driven of the scan drive cell of Fig. 3；
Fig. 7 is the interleaved software emulation result figure of the scan drive cell of Fig. 3；
Fig. 8 is the second embodiment of a scan drive cell of the scan drive circuit of the present invention
Circuit diagram；
Fig. 9 is the schematic diagram of the flat display apparatus of the present invention.
Detailed description of the invention
Refer to Fig. 1, prior art midplane display device be provided with some scan lines, be also accomplished by corresponding these
Scan line arranges corresponding scan drive cell, and existing each scan drive cell only drives a scan line, often sweeps
Retouching driver element and include input circuit 10, pull-down circuit 20, control circuit 30 and output circuit 40, this will make plane display dress
Complex circuit designs in putting.It is the working timing figure of scan drive cell in prior art please continue to refer to Fig. 2, Fig. 2.Its
In, when the high level of clock signal CK1 comes interim, drive signal STV by thin film transistor (TFT) T1 and T5 to pull-up control signal
Point Q1 is charged, and pull-up control signal point Q1 is charged to high level, and electric capacity C1 maintains high level；Meanwhile, pull-up control signal
Point Q1 is by the control to thin film transistor (TFT) T3, it is achieved the drop-down control to drop-down control signal point P1, electric capacity C2 maintains low electricity
Flat；Now, thin film transistor (TFT) T2 and T7 is closed；When the high level of clock signal CK3 comes interim, scan line Gate1
Output high level signal, i.e. creates the gate drive signal of this grade, after clock signal CK3 becomes low level, clock signal
The high level signal of CK4 arrives, and now, thin film transistor (TFT) T4 turns on, and drop-down control signal point P1 is charged to high level, electric capacity C2
Maintain high level；Afterwards, thin film transistor (TFT) T2 and T7 turns on, and pull-up control signal point Q1 is pulled down to low level, scan line
The output signal of Gate1 is pulled down to low level, and whole circuit is in steady statue, the operation principle of remaining scan drive circuit
Same as described above, do not repeat them here.
Refer to Fig. 3, be the circuit of the first embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.In the present embodiment, only illustrate as a example by a scan drive cell.As it is shown on figure 3, the turntable driving of the present invention
Circuit includes multiple scan drive cells of cascade, and each described scan drive cell includes:
First input circuit 100, for receiving the first clock signal and driving signal and export the first input signal；
Second input circuit 500, for receiving the first clock signal and driving signal and export the second input signal；
Pull-down circuit 200, is used for receiving second clock signal and exporting pulldown signal and according to described second clock signal
Drop-down control signal point is carried out drop-down or charging；
First control circuit 300, for receiving described first input signal and according to institute from described first input circuit 100
State the first input signal the first pull-up control signal point is charged, or receive described drop-down from described pull-down circuit 200
Described first pull-up control signal point is also carried out drop-down according to described pulldown signal by signal；
Second control circuit 600, for receiving described second input signal and according to institute from described second input circuit 500
State the second input signal the second pull-up control signal point is charged, or receive described drop-down from described pull-down circuit 200
Described second pull-up control signal point is also carried out drop-down according to described pulldown signal by signal；
First output circuit 400, for receiving the 3rd clock signal and sweeping according to described 3rd clock signal generation first
Retouch driving signal to export to the first scan line to drive pixel cell；And
Second output circuit 700, for receiving the 4th clock signal and sweeping according to described 4th clock signal generation second
Retouch driving signal to export to the second scan line to drive pixel cell.
Specifically, described first input circuit 100 includes the first gate-controlled switch T1, the control of described first gate-controlled switch T1
End receives described first clock signal, and first end of described first gate-controlled switch T1 receives described driving signal, and described first can
Second end of control switch T1 connects described pull-down circuit 200 and described first control circuit 300.
Described pull-down circuit 200 includes the second to the 8th gate-controlled switch T2-T8 and the first electric capacity C1, and described second controlled opens
The end that controls closing T2 connects second end of described first gate-controlled switch T1, first end of described 3rd gate-controlled switch T3 and described the
One control circuit 300, first end of described second gate-controlled switch T2 receives closes voltage end signal VGL, and described second controlled opens
Close second end of T2 connect described 3rd gate-controlled switch T3 control end, the control end of described 4th gate-controlled switch T4, described the
Seven gate-controlled switch T7 control end, described 8th gate-controlled switch T8 control end, first end of described 5th gate-controlled switch T5 and
Second end of described 6th gate-controlled switch T6, second end of described 3rd gate-controlled switch T3 connects described 4th gate-controlled switch T4's
First end, second end of described 7th gate-controlled switch T7 and first end of described 8th gate-controlled switch T8, the described 4th controlled opens
The second end closing T4 connects the control end of described 5th gate-controlled switch T5, described second input circuit 500 and described second control
Circuit 600, second end of described 5th gate-controlled switch T5 receives described closedown voltage end signal VGL, described 6th gate-controlled switch
The control end of T6 receives described second clock signal, and first end of described 6th gate-controlled switch T6 receives cut-in voltage end signal
First end of VGH, described 7th gate-controlled switch T7 connects described first output circuit 400, the of described 8th gate-controlled switch T8
Two ends connect described second output circuits 700, described first electric capacity C1 be connected to first end of described 6th gate-controlled switch T6 with
Between second end.
Described first control circuit 300 includes that the control end of the 9th gate-controlled switch T9, described 9th gate-controlled switch T9 receives
First end of described cut-in voltage end signal VGH, described 9th gate-controlled switch T9 connects the control of described second gate-controlled switch T2
End and first end of described 3rd gate-controlled switch T3, second end of described 9th gate-controlled switch T9 connects described first output circuit
400。
Described first output circuit 400 includes the tenth gate-controlled switch T10 and the second electric capacity C2, described tenth gate-controlled switch
T10 controls the second end that end connects described 9th gate-controlled switch T9, and first end of described tenth gate-controlled switch T10 receives described
3rd clock signal, second end of described tenth gate-controlled switch T10 connects described first scan line and described 7th gate-controlled switch
First end of T7, described second electric capacity C2 is connected between control end and second end of described tenth gate-controlled switch T10.
Described second input circuit 500 includes the 11st gate-controlled switch T11, the control of described 11st gate-controlled switch T11
End receives described first clock signal, the first end described driving signal of reception of described 11st gate-controlled switch T11, and the described tenth
Second end of one gate-controlled switch T11 connects the control end of described 5th gate-controlled switch T5.
Described second control circuit 600 includes the 12nd gate-controlled switch T12, the control of described 12nd gate-controlled switch T12
End receives first end of described cut-in voltage end signal VGH, described 12nd gate-controlled switch T12 and connects described 4th gate-controlled switch
Second end of T4 and the control end of described 5th gate-controlled switch T5, second end of described 12nd gate-controlled switch T12 connects described
Second output circuit 700.
Described second output circuit 700 includes the 13rd gate-controlled switch T13 and the 3rd electric capacity C3, and the described 13rd controlled opens
Close T13 controls the second end that end connects described 12nd gate-controlled switch T12, first end of described 13rd gate-controlled switch T13
Connect described second scan line and second end of described 8th gate-controlled switch T8, second end of described 13rd gate-controlled switch T13
Receiving described 4th clock signal, described 3rd electric capacity C3 is connected to the control end and first of described 13rd gate-controlled switch T13
Between end.
In the present embodiment, described first to the 13rd gate-controlled switch T1-T13 is N-type TFT, described first to
13rd gate-controlled switch T1-T13 controls the grid of corresponding described N-type TFT, the leakage respectively of end, the first end and the second end
Pole and source electrode.
Specifically, described first clock signal is the first clock signal CK1, and described second clock signal is second clock letter
Number CK4, described 3rd clock signal is the 3rd clock signal CK2, and described 4th clock signal is the 4th clock signal CK3, institute
Stating the first pull-up control signal point is pull-up control signal point Q1, and described second pull-up control signal point is pull-up control signal point
Q2, drop-down control signal point is drop-down control signal point P12, drives signal for driving signal STV, and the first scan line is scan line
Gate1, the second scan line is scan line Gate2.
Refer to Fig. 4 to Fig. 7, be working timing figure and the software emulation figure of scan drive circuit of the present invention.According to Fig. 4 extremely
The operation principle that Fig. 7 can obtain described scan drive circuit is as follows: illustrate as a example by a scan drive cell below.
When the high level of the first clock signal CK1 comes interim, the first gate-controlled switch T1 and the second gate-controlled switch T2 conducting, the 9th controlled opens
The end that controls closing T9 receives the high level of cut-in voltage end signal VGH and in the conduction state always, now drives signal STV to lead to
Crossing the first gate-controlled switch T1 and the 9th gate-controlled switch T9 to be charged the first pull-up control signal point Q1, the first pull-up controls letter
Number some Q1 is charged to high level, and the second electric capacity C2 maintains high level；When the high level of described first clock signal CK1 comes interim,
11st gate-controlled switch T11 and the 5th gate-controlled switch T5 conducting, the control end of the 12nd gate-controlled switch T12 receives unlatching electricity always
The high level of pressure side signal VGH and in the conduction state, drive the signal STV can by the 11st gate-controlled switch T11 and the 12nd
Second pull-up control signal point Q2 is charged by control switch T12, and the second pull-up control signal point Q2 is charged to high level, and the 3rd
Electric capacity C3 maintains high level.When the low level of second clock signal CK4 is come interim, the 6th gate-controlled switch T6 cut-off, because second
Gate-controlled switch T2 and the 5th gate-controlled switch T5 is in conducting state, and the first pull-up control signal point Q1, the second pull-up control letter
Number some Q2 and drop-down control signal point P12 is all pulled down to low level, and the first electric capacity C1 maintains low level, and now, the 3rd is controlled
Switch T3, the 7th gate-controlled switch T7, the control end of the 4th gate-controlled switch T4 and the 8th gate-controlled switch T8 all receive low level signal
And end.
When the high level of the 3rd clock signal CK2 comes interim, because the tenth gate-controlled switch T10 is in the conduction state, therefore
First scan line Gate1 output high level signal, i.e. creates the gate drive signal of the first order and is supplied to the pixel of correspondence
Unit；When the high level of the 4th clock signal CK3 comes interim, because the 13rd gate-controlled switch T13 is in the conduction state, therefore the
Two scan line Gate2 output high level signals, i.e. create the pixel cell that the gate drive signal of the second level is corresponding.
When the high level of second clock signal CK4 comes interim, the 6th gate-controlled switch T6 conducting, drop-down control signal point P12
Being charged to high level, the first electric capacity C1 maintains high level；Afterwards, the 3rd gate-controlled switch T3, the 7th gate-controlled switch T7, the 4th controlled
The control end of switch T4 and the 8th gate-controlled switch T8 all receives high level signal and turns on, the first pull-up control signal point Q1 and the
Two pull-up control signal point Q2 are pulled down to low level and stable in low level, the first scan line Gate1 and the second scan line
The scanning drive signal of Gate2 output is pulled down to low level and is supplied to the pixel cell of correspondence, now, described turntable driving
Cell operation terminates, and whole circuit is in steady statue.The operation principle of remaining scan drive cell is same as described above, at this not
Repeat again.
Refer to Fig. 8, be the circuit of the second embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.Second embodiment of described scan drive cell is in place of the difference of the first embodiment of above-mentioned scan drive cell:
Described first to the 13rd gate-controlled switch T1-T13 is P-type TFT, described first to the 13rd gate-controlled switch T1-T13
The grid, drain electrode and the source electrode that control end, the first end and the second end corresponding described P-type TFT respectively.Implement at other
In example, described first to the 13rd gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
Refer to Fig. 9, for the schematic diagram of a kind of flat display apparatus of the present invention.Described flat display apparatus includes aforesaid
Scan drive circuit, described scan drive circuit is arranged on the two ends of described flat display apparatus, in described flat display apparatus
Other devices and function identical with the device in existing flat display apparatus and function, do not repeat them here.Wherein, described flat
Flat-panel display device is LCD or OLED.
The scan drive circuit of the present invention is come by first and second input circuit and first and second control circuit
One and second pulls up control signal point is charged, and realizes drop-down control signal point by arranging a pull-down circuit
Drop-down control, exports first and second scanning drive signal by first and second output circuit and is respectively supplied to first and second
Scan line drives the pixel cell of correspondence, the circuit realizing simplifying flat display apparatus with this, saves space, and then is beneficial to flat
The narrow frame design of flat-panel display device.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization is originally
Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or are directly or indirectly used in what other were correlated with
Technical field, is the most in like manner included in the scope of patent protection of the present invention.
Claims (10)
1. a scan drive circuit, it is characterised in that described scan drive circuit includes multiple scan drive cells of cascade,
Each described scan drive cell includes:
First input circuit, for receiving the first clock signal and driving signal and export the first input signal；
Second input circuit, for receiving the first clock signal and driving signal and export the second input signal；
Pull-down circuit, is used for receiving second clock signal and exporting pulldown signal and according to described second clock signal to drop-down control
Signaling point processed carries out drop-down or charging；
First control circuit, for receiving described first input signal and according to described first input from described first input circuit
First pull-up control signal point is charged by signal, or receives described pulldown signal and according to described from described pull-down circuit
Described first pull-up control signal point is carried out drop-down by pulldown signal；
Second control circuit, for receiving described second input signal and according to described second input from described second input circuit
Second pull-up control signal point is charged by signal, or receives described pulldown signal and according to described from described pull-down circuit
Described second pull-up control signal point is carried out drop-down by pulldown signal；
First output circuit, for receiving the 3rd clock signal and producing the first turntable driving letter according to described 3rd clock signal
Number output drives pixel cell to the first scan line；And
Second output circuit, for receiving the 4th clock signal and producing the second turntable driving letter according to described 4th clock signal
Number output drives pixel cell to the second scan line.
Scan drive circuit the most according to claim 1, it is characterised in that described first input circuit includes that first is controlled
Switch, the control end of described first gate-controlled switch receives described first clock signal, the first termination of described first gate-controlled switch
Receiving described driving signal, the second end of described first gate-controlled switch connects described pull-down circuit and described first control circuit.
Scan drive circuit the most according to claim 2, it is characterised in that described pull-down circuit includes that second can to the 8th
Control switch and the first electric capacity, described second gate-controlled switch control end connect the second end of described first gate-controlled switch, described the
First end of three gate-controlled switches and described first control circuit, the first end of described second gate-controlled switch receives closes voltage end letter
Number, the second end of described second gate-controlled switch connects control end, the control of described 4th gate-controlled switch of described 3rd gate-controlled switch
End processed, described 7th gate-controlled switch control end, described 8th gate-controlled switch control end, the first of described 5th gate-controlled switch
End and the second end of described 6th gate-controlled switch, the second end of described 3rd gate-controlled switch connects the of described 4th gate-controlled switch
One end, the second end of described 7th gate-controlled switch and the first end of described 8th gate-controlled switch, the of described 4th gate-controlled switch
The two ends connection control ends of described 5th gate-controlled switch, described second input circuit and described second control circuit, the described 5th
Second end of gate-controlled switch receives described closedown voltage end signal, when the control end of described 6th gate-controlled switch receives described second
Clock signal, the first end of described 6th gate-controlled switch receives cut-in voltage end signal, and the first end of described 7th gate-controlled switch is even
Connecing described first output circuit, the second end of described 8th gate-controlled switch connects described second output circuit, described first electric capacity
It is connected between the first end and second end of described 6th gate-controlled switch.
Scan drive circuit the most according to claim 3, it is characterised in that described first control circuit includes that the 9th is controlled
Switch, the control end of described 9th gate-controlled switch receives described cut-in voltage end signal, the first end of described 9th gate-controlled switch
Connect described second gate-controlled switch controls end and the first end of described 3rd gate-controlled switch, the second of described 9th gate-controlled switch
End connects described first output circuit.
Scan drive circuit the most according to claim 4, it is characterised in that described first output circuit includes that the tenth is controlled
Switch and the second electric capacity, second end controlling end described 9th gate-controlled switch of connection of described tenth gate-controlled switch, the described tenth
First end of gate-controlled switch receives described 3rd clock signal, and the second end of described tenth gate-controlled switch connects described first scanning
Line and the first end of described 7th gate-controlled switch, described second electric capacity is connected to the control end and second of described tenth gate-controlled switch
Between end.
Scan drive circuit the most according to claim 5, it is characterised in that described second input circuit includes that the 11st can
Control switch, the control end of described 11st gate-controlled switch receives described first clock signal, the of described 11st gate-controlled switch
One end receives described driving signal, and the second end of described 11st gate-controlled switch connects the control end of described 5th gate-controlled switch.
Scan drive circuit the most according to claim 6, it is characterised in that described second control circuit includes that the 12nd can
Control switch, the control end of described 12nd gate-controlled switch receives described cut-in voltage end signal, described 12nd gate-controlled switch
First end connects the second end of described 4th gate-controlled switch and the control end of described 5th gate-controlled switch, and the described 12nd controlled opens
The second end closed connects described second output circuit.
Scan drive circuit the most according to claim 7, it is characterised in that described second output circuit includes that the 13rd can
Control switch and the 3rd electric capacity, the end that controls of described 13rd gate-controlled switch connects the second end of described 12nd gate-controlled switch, institute
State the first end of the 13rd gate-controlled switch and connect described second scan line and the second end of described 8th gate-controlled switch, the described tenth
Second end of three gate-controlled switches receives described 4th clock signal, and described 3rd electric capacity is connected to described 13rd gate-controlled switch
Control between end and the first end.
Scan drive circuit the most according to claim 8, it is characterised in that described first to the 13rd gate-controlled switch is N
Type thin film transistor (TFT), the control end of described first to the 13rd gate-controlled switch, the first end and the second end corresponding described N-type respectively is thin
The grid of film transistor, drain electrode and source electrode；Or described first to the 13rd gate-controlled switch is P-type TFT, described
The control end of one to the 13rd gate-controlled switch, the first end and the grid of corresponding described P-type TFT, the drain electrode respectively of the second end
And source electrode.
10. a flat display apparatus, it is characterised in that described flat display apparatus includes as described in claim 1-9 is arbitrary
Scan drive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610717822.0A CN106098016B (en) | 2016-08-24 | 2016-08-24 | Scan drive circuit and flat display apparatus with the circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610717822.0A CN106098016B (en) | 2016-08-24 | 2016-08-24 | Scan drive circuit and flat display apparatus with the circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106098016A true CN106098016A (en) | 2016-11-09 |
| CN106098016B CN106098016B (en) | 2018-10-23 |
Family
ID=57226435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610717822.0A Active CN106098016B (en) | 2016-08-24 | 2016-08-24 | Scan drive circuit and flat display apparatus with the circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106098016B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106486078A (en) * | 2016-12-30 | 2017-03-08 | 深圳市华星光电技术有限公司 | A kind of scan drive circuit, drive circuit and display device |
| CN106782423A (en) * | 2017-03-29 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of scan drive circuit and liquid crystal display |
| CN108665837A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Scan drive circuit and its driving method and panel display apparatus |
| WO2018210103A1 (en) * | 2017-05-19 | 2018-11-22 | 京东方科技集团股份有限公司 | Pixel driver circuit, display device, and driving method |
| WO2021227185A1 (en) * | 2020-05-15 | 2021-11-18 | 武汉华星光电技术有限公司 | Display driving circuit |
| CN114038412A (en) * | 2021-11-30 | 2022-02-11 | 重庆康佳光电技术研究院有限公司 | Light-emitting control signal generation circuit, light-emitting diode driving module and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103345941A (en) * | 2013-07-03 | 2013-10-09 | 京东方科技集团股份有限公司 | Shift register unit, drive method, shift register circuit and display device |
| CN103578433A (en) * | 2012-07-24 | 2014-02-12 | 北京京东方光电科技有限公司 | Grid drive circuit and method and liquid crystal display |
| KR20140079106A (en) * | 2012-12-18 | 2014-06-26 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
| CN104505049A (en) * | 2014-12-31 | 2015-04-08 | 深圳市华星光电技术有限公司 | Grid driving circuit |
| CN104700803A (en) * | 2015-03-26 | 2015-06-10 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit, display panel and display device |
| CN105139816A (en) * | 2015-09-24 | 2015-12-09 | 深圳市华星光电技术有限公司 | Gate drive circuit |
-
2016
- 2016-08-24 CN CN201610717822.0A patent/CN106098016B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578433A (en) * | 2012-07-24 | 2014-02-12 | 北京京东方光电科技有限公司 | Grid drive circuit and method and liquid crystal display |
| KR20140079106A (en) * | 2012-12-18 | 2014-06-26 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
| CN103345941A (en) * | 2013-07-03 | 2013-10-09 | 京东方科技集团股份有限公司 | Shift register unit, drive method, shift register circuit and display device |
| CN104505049A (en) * | 2014-12-31 | 2015-04-08 | 深圳市华星光电技术有限公司 | Grid driving circuit |
| CN104700803A (en) * | 2015-03-26 | 2015-06-10 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit, display panel and display device |
| CN105139816A (en) * | 2015-09-24 | 2015-12-09 | 深圳市华星光电技术有限公司 | Gate drive circuit |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106486078A (en) * | 2016-12-30 | 2017-03-08 | 深圳市华星光电技术有限公司 | A kind of scan drive circuit, drive circuit and display device |
| US10262614B2 (en) | 2016-12-30 | 2019-04-16 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Scan driving circuit, driving circuit and display device |
| CN106486078B (en) * | 2016-12-30 | 2019-05-03 | 深圳市华星光电技术有限公司 | A kind of scan drive circuit, driving circuit and display device |
| CN108665837A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Scan drive circuit and its driving method and panel display apparatus |
| CN106782423A (en) * | 2017-03-29 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of scan drive circuit and liquid crystal display |
| US10699660B2 (en) | 2017-03-29 | 2020-06-30 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Scan-driving circuit and liquid crystal display |
| WO2018210103A1 (en) * | 2017-05-19 | 2018-11-22 | 京东方科技集团股份有限公司 | Pixel driver circuit, display device, and driving method |
| WO2021227185A1 (en) * | 2020-05-15 | 2021-11-18 | 武汉华星光电技术有限公司 | Display driving circuit |
| CN114038412A (en) * | 2021-11-30 | 2022-02-11 | 重庆康佳光电技术研究院有限公司 | Light-emitting control signal generation circuit, light-emitting diode driving module and display panel |
| CN114038412B (en) * | 2021-11-30 | 2022-12-30 | 重庆康佳光电技术研究院有限公司 | Light-emitting control signal generation circuit, light-emitting diode driving module and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106098016B (en) | 2018-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106128348B (en) | Scan drive circuit | |
| CN106098016B (en) | Scan drive circuit and flat display apparatus with the circuit | |
| CN105304011B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN103021358B (en) | Shifting register unit, gate driving circuit and display device | |
| CN103345941B (en) | Shift register cell and driving method, shift-register circuit and display device | |
| CN106023936B (en) | Scan drive circuit and flat display apparatus with the circuit | |
| CN104091572B (en) | Two drop-down control module, shifting deposit unit, gate drivers and display panel | |
| CN105139816B (en) | Gate driving circuit | |
| CN103456259B (en) | A kind of gate driver circuit and grid line driving method, display device | |
| CN105096803B (en) | Shift register and its driving method, gate driving circuit, display device | |
| CN106297636B (en) | Flat display apparatus and its scan drive circuit | |
| CN108766340A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN104505049A (en) | Grid driving circuit | |
| CN106601176A (en) | Shift register unit circuit, driving method, shift register and display device | |
| CN106098002B (en) | Scan drive circuit and flat display apparatus with the circuit | |
| CN104732904B (en) | Display device and gate drive circuit and gate drive unit circuit thereof | |
| CN103489391B (en) | A kind of gate driver circuit and grid line driving method, display device | |
| CN105469763A (en) | Gate driving unit, gate driving circuit and display device | |
| CN106297630B (en) | Scan drive circuit and flat display apparatus with the circuit | |
| CN106952624B (en) | Shifting deposit unit and its driving method, gate driving circuit and display device | |
| CN105976751A (en) | Scan drive circuit and planar display device provided with same | |
| CN103151013B (en) | Gate driver circuit | |
| CN104637430B (en) | Gate driving circuit and display device | |
| CN107221299A (en) | A kind of GOA circuits and liquid crystal display | |
| CN105185333A (en) | Grid driving circuit of liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |