CN106095675A - A kind of EDA and FPGA for passive label chip reusable checking system - Google Patents
A kind of EDA and FPGA for passive label chip reusable checking system Download PDFInfo
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- CN106095675A CN106095675A CN201610398841.1A CN201610398841A CN106095675A CN 106095675 A CN106095675 A CN 106095675A CN 201610398841 A CN201610398841 A CN 201610398841A CN 106095675 A CN106095675 A CN 106095675A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
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Abstract
The present invention relates to a kind of EDA and FPGA for passive label chip reusable checking system, including EDA environment checking system and FPGA environment checking system, reader verilog model (2) in described EDA environment checking system and reader verilog model (1 3) in DUT (7) and FPGA environment checking system and DUT (1 10) are mutually reused.In the checking system of the present invention, EDA and FPGA verification environment can reuse the verilog code of reader and label, the code so making EDA and FPGA use is living, RTL code not be used between two checking systems and is modified, and this avoid the Risks that little change brings.
Description
Technical field
The present invention relates to a kind of EDA and FPGA for passive label chip reusable checking system.
Background technology
Current industry main flow EDA checking system as shown in Figure 1, is will to be verified module DUT example in verification environment,
By adding excitation to DUT, observing what DUT output was carried out, such defect is that the read write line SV model that checking engineer writes has
Cannot be verified if defect, the scene also having checking engineer and design engineer simultaneously to neglect is difficult to be found.
Current industry main flow FPGA checking system as shown in Figure 2, be practical products in kind reader by antenna with under
The label RTL code being downloaded on FPGA plank communicates checking, and the defect of this system is all fields of products in kind reader
Scape is the very small part of clarifying space, and all parameters have been fixed or changed the least or too big, do not meet standard
Requirement, the development progress being exactly also reader may be more backward than label development progress, and such a checking system is to reader
The dependence of producer is too big, the serious development progress hindering label.
How label is carried out code realization, it is to avoid design engineer omits the scene of falling so that observe the checking of output
The most complete is prior art problem to be solved.
Summary of the invention
It is an object of the invention to: for above-mentioned technical problem present in prior art, it is provided that a kind of high efficiency, complete
Checking system.
The present invention is achieved by the following technical solutions:
A kind of EDA and FPGA for passive label chip reusable checking system: include EDA environment checking system and
FPGA environment checking system；
Reader simulink model, reader verilog model and excitation in described EDA environment checking system occur
Device is connected with the input of selection control one, the outfan of selection control respectively with label simulink model, label SV
Model is connected with the input of DUT, and the outfan of described label simulink model, label SV model and DUT is controlled by selection
Device two processed is connected with Comparative result device, result detector；
Upper computer software in described FPGA environment checking system is connected with reader, reader verilog model with read
Reading device radio-frequency module one to be connected, the algorithm model of reader realizes module and Reader radio frequency module two-phase by reader plate level
Even；Described reader, Reader radio frequency module one are connected with selection control with the outfan of Reader radio frequency module two；Label
Radio-frequency module is connected with DUT；Described selection control and Tag Radio Frequency module use Anneta module to be in communication with each other；
Readding in reader verilog model in described EDA environment checking system and DUT with FPGA environment checking system
Read device verilog model and DUT mutually reuses.
Further, the reader simulink model in described EDA environment checking system is by verifying that engineer one compiles
Writing and debugging is passed through, this model can be simulated reader and be carried out the return detection of excitation transmission and label.
The verilog model of the reader in described EDA environment checking system, is write by checking engineer one and is adjusted
Pinging, this model can be simulated reader and be carried out the return detection of excitation transmission and label.
Further, the actuation generator in described EDA environment checking system is by verifying that engineer two uses system
Verilog writes.
Further, the selection control one in described EDA environment checking system, reader simulink mould can be controlled
Type, reader verilog model and actuation generator and label simulink model, label SV model and the interface gateway of DUT,
Any one road, two-way or three in reader simulink model, reader verilog model and actuation generator can be selected
Road carries out communicating with label simulink model, label SV model and DUT.
Label simulink model in described EDA environment checking system is by algorithm engineering Shi Caiyong MATLAB
SIMULINK+M language realizes, as the reference model of label chip RTL code, as comparison.
Label SV model in described EDA environment checking system by verifying that engineer uses system verilog to write,
As the reference model of label chip RTL code, as comparison.
Further, the RTL code that DUT is label chip in described EDA environment checking system, designer use
Verilog language is write.
Further, the Comparative result device in described EDA environment checking system, result detector are to label simulink mould
The result that type, label SV model and DUT select through selection control two is verified.
Upper computer software in described FPGA environment checking system is developed by reader producer, controls reader and receives and dispatches
Deng operation.
Reader in described FPGA environment checking system is developed by reader producer, by upper computer software control, and can
To carry out the mutual of various scene with label.
Further, the reader verilog model in described FPGA environment checking system is by the checking engineering of label producer
Shi Kaifa, uses verilog language to realize, it is desirable to can carry out that FPGA is comprehensive, download, it is possible to be simultaneously embedded in EDA environment and test
Card system carries out simulating, verifying, is used for below specific scene substituting reader and label interacts.
Reader radio frequency module one in described FPGA environment checking system can be developed by reader producer, it is also possible to by
Label producer oneself develops.
Further, the algorithm model of the reader in described FPGA environment checking system, by algorithm engineering Shi Kaifa, uses
MATLAB SIMULINK+M language realizes.
Further, the reader plate level in described FPGA environment checking system realizes module and uses DSP+FPGA, reader
Algorithm model combine FPGA more jointly complete the interactive operation to label by downloading to DSP, DSP after compiling.
Reader radio frequency module two in described FPGA environment checking system completes the up-conversion of reader signal when sending
And signal amplifies, launched by antenna, complete to receive the down coversion of signal during reception and signal amplifies behaviour.
Selection control in described FPGA environment checking system can select any one, two, three, in order to complete
Operate with the various interaction scenarios of label, such as anticollision, group's reading, session group etc..
Tag Radio Frequency module in described FPGA environment checking system completes up-conversion and the signal of label signal when sending
Amplify, launched by antenna, during reception, complete to receive down coversion and the signal amplifieroperation of signal.
Further, the DUT in described FPGA environment checking system, the RTL verilog code being label chip realizes,
This code produces to chip production producer the most alternately by generating GDS after checking, comprehensive, placement-and-routing.
In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:
1, in the checking system of the present invention, two checking engineers one carry out verilog realization to reader, and one right
Label carries out system verilog realization, has been achieved in that the comparison to reader, reader and label can obtain
To the most perfect checking, label producer is without relying on the development progress of reader producer.
2, the checking system of the present invention is verified engineer and design engineer be respectively adopted system verilog and
Verilog carries out code realization to label, it is to avoid design engineer omits the scene of falling, and such comparison ratio is single
The checking carrying out verilog code filling excitation, observation exports is the most complete.
3, in the checking system of the present invention, EDA and FPGA verification environment can reuse the verilog generation of reader and label
Code, the code so making EDA and FPGA use is living, and RTL code not be used between two checking systems and carries out
Change, this avoid the Risks that little change brings.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is that the EDA of prior art verifies system block diagram；
Fig. 2 is that the FPGA of prior art verifies system block diagram；
Fig. 3 is that the EDA of the present invention verifies system block diagram；
Fig. 4 is that the EDA of the label chip base band of the specific embodiment of the invention verifies system block diagram；
Fig. 5 is that the FPGA of the present invention verifies system block diagram；
Fig. 6 is that the FPGA containing reusable module of the specific embodiment of the invention verifies system block diagram.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, except mutually exclusive
Feature and/or step beyond, all can combine by any way.
Any feature disclosed in this specification (including any accessory claim, summary and accompanying drawing), unless chatted especially
State, all can be by other equivalences or there is the alternative features of similar purpose replaced.I.e., unless specifically stated otherwise, each feature is only
It it is an example in a series of equivalence or similar characteristics.
As shown in Figures 3 and 5, a kind of EDA and FPGA for passive label chip reusable checking system: include EDA
Environment checking system and FPGA environment checking system；
Reader simulink model 1, reader verilog model 2 and excitation in described EDA environment checking system are sent out
Raw device 3 is connected with the input of selection control 1, the outfan of selection control 4 respectively with label simulink model 5,
Label SV model 6 is connected with the input of DUT7, described label simulink model 5, the outfan of label SV model 6 and DUT7
It is connected with Comparative result device, result detector 9 by selection control 28；
Upper computer software 1-1 in described FPGA environment checking system is connected with reader 1-2, reader verilog mould
Type 1-3 is connected with Reader radio frequency module one 1-4, the algorithm model 1-5 of reader by reader plate level realize module 1-6 with
Reader radio frequency module two 1-7 is connected；Described reader 1-2, Reader radio frequency module one 1-4 and Reader radio frequency module two 1-
The outfan of 7 is connected with selection control 1-8；Tag Radio Frequency module 1-9 is connected with DUT1-10；Described selection control 1-8 with
Tag Radio Frequency module 1-9 uses Anneta module to be in communication with each other；
In reader verilog model 2 and DUT7 Yu FPGA environment checking system in described EDA environment checking system
Reader verilog model 1-3 and DUT1-10 mutually reuses.
Specifically, the reader simulink model 1 in described EDA environment checking system is compiled by checking engineer one
Writing and debugging is passed through, this model can be simulated reader and be carried out the return detection of excitation transmission and label.
The verilog model 2 of the reader in described EDA environment checking system, by checking engineer one carry out writing and
Debugging is passed through, and this model can be simulated reader and be carried out the return detection of excitation transmission and label.
Specifically, the actuation generator 3 in described EDA environment checking system is used system by checking engineer two
Verilog writes.
Specifically, the selection control 1 in described EDA environment checking system, reader simulink mould can be controlled
Type 1, reader verilog model 2 and actuation generator 3 and label simulink model 5, the connecing of label SV model 6 and DUT7
Mouthful path, can select in reader simulink model 1, reader verilog model 2 and actuation generator 3 is any one
Road, two-way or three tunnels carry out communicating with label simulink model 5, label SV model 6 and DUT7.
Label simulink model 5 in described EDA environment checking system is by algorithm engineering Shi Caiyong MATLAB
SIMULINK+M language realizes, as the reference model of label chip RTL code, as comparison.
Label SV model 6 in described EDA environment checking system is used system verilog to write by checking engineer,
As the reference model of label chip RTL code, as comparison.
Specifically, the RTL code that DUT7 is label chip in described EDA environment checking system, designer use
Verilog language is write.
Specifically, the Comparative result device in described EDA environment checking system, result detector 9 are to label simulink mould
Type 5, label SV model 6 and DUT7 are verified through asserting of selecting of selection control 28.
Upper computer software 1-1 in described FPGA environment checking system is developed by reader producer, controls reader and carries out
The operations such as transmitting-receiving.
Reader 1-2 in described FPGA environment checking system is developed by reader producer, by upper computer software control,
The mutual of various scene can be carried out with label.
Specifically, the reader verilog model 1-3 in described FPGA environment checking system is by the checking work of label producer
Journey Shi Kaifa, uses verilog language to realize, it is desirable to can carry out that FPGA is comprehensive, download, it is possible to be simultaneously embedded in EDA environment
Checking system carries out simulating, verifying, is used for below specific scene substituting reader and label interacts.
Reader radio frequency module one 1-4 in described FPGA environment checking system can be developed by reader producer, it is possible to
To be developed by label producer oneself.
Specifically, the algorithm model 1-5 of the reader in described FPGA environment checking system, by algorithm engineering Shi Kaifa, adopts
Realize with MATLAB SIMULINK+M language.
Specifically, the reader plate level in described FPGA environment checking system realizes module 1-6 and uses DSP+FPGA, reads
The algorithm model of device is combined FPGA more jointly complete the interactive operation to label by being downloaded to DSP, DSP after compiling.
Reader radio frequency module two 1-7 in described FPGA environment checking system completes the upper change of reader signal when sending
Frequency and signal amplify, and are launched by antenna, complete to receive the down coversion of signal and signal amplifies behaviour during reception.
Selection control 1-8 in described FPGA environment checking system can select any one, two, three, in order to
Complete the various interaction scenarios with label, as anticollision, group's reading, session group etc. operate.
Tag Radio Frequency module 1-9 in described FPGA environment checking system completes up-conversion and the letter of label signal when sending
Number amplify, launched by antenna, complete during reception to receive the down coversion of signal and signal amplifieroperation.
Specifically, the DUT1-10 in described FPGA environment checking system, it is the RTL verilog code of label chip
Realizing, this code produces to chip production producer the most alternately by generating GDS after checking, comprehensive, placement-and-routing.
As shown in Figure 4, the EDA of the label chip base band in detailed description of the invention verifies system, including interface MUX (choosing
Select control signal path), VMM reader excitation produce device, VMM label excitation maker, n reader SV model, n reading
Device verilog model, n label SV model, interface monitor device (interface assert device), reader monitor (reader assert device)
(function coverage collection) is collected with code coverage；VMM test case by VMM environment configure, reader model configure and
Label configuration produces device with the excitation of VMM reader respectively after processing and VMM label excitation maker is in communication with each other, described interface
MUX (selecting control signal path) produces device, VMM label excitation maker, n reader SV respectively with the excitation of VMM reader
Model, n reader verilog model, n label SV model, n label RTL, interface monitor device (interface assert device) communicate
Letter connects；
Described n label SV model and n label RTL one_to_one corresponding, communicate with n label comparison logic even respectively
Connect.It is label SV model one and label one RTL communicates with label comparison logic one respectively and is connected, label SV model two and mark
Signing two RTL to communicate to connect with label comparison logic two-phase respectively, label SV model n and label n RTL patrols with label comparison respectively
Collect n and communicate connection.
N label RTL respectively with label monitor (label assert device) and code coverage is collected, and (function coverage is received
Collection) communicate connection.
Described n reader SV model, n reader verilog model one_to_one corresponding, respectively with n reader comparison
Logic communicates connection.Be reader SV model one and reader verilog model one respectively with reader comparison logic one
Communicate connection, reader SV model two and reader verilog model two respectively with reader comparison logic two-phase communication link
Connecing, reader SV model n and reader verilog model n communicates with reader comparison logic n respectively and is connected.
N reader SV model communicates with reader monitor (reader assert device) respectively and is connected.
Specifically, reader comparison logic one, SV (system verilog) the model one and verilog mould to reader
Type one contrasts, and uses master clock that forward and reverse signal carries out sampling contrast, and it is right to carry out when rising edge clock
Ratio, two model contrasts are inconsistent, report an error, complete comparison is then reported TEST PASS.
Specifically, reader comparison logic two, SV (system verilog) the model two and verilog mould to reader
Type two contrasts, and uses master clock that forward and reverse signal carries out sampling contrast, and it is right to carry out when rising edge clock
Ratio, two model contrasts are inconsistent, report an error, complete comparison is then reported TEST PASS.
Specifically, reader comparison logic n, SV (system verilog) model n and the verilog model to reader
N contrasts, and uses master clock that forward and reverse signal carries out sampling contrast, contrasts when rising edge clock,
Two model contrasts are inconsistent, report an error, complete comparison is then reported TEST PASS.
Specifically, reader SV model one, use system verilog that reader SV model is realized, this SV mould
Type can meet all functional performance requirements of reader in corresponding RF ID standard agreement.This model is mainly used to simulate reader pair
Label communicates, such that it is able to whether the various functions performance of checking label chip meets requirement.
Specifically, reader SV model two, use system verilog that reader SV model is realized, this SV mould
Type can meet all functional performance requirements of reader in corresponding RF ID standard agreement.
Specifically, reader SV model n, use system verilog that reader SV model is realized, this SV mould
Type can meet all functional performance requirements of reader in corresponding RF ID standard agreement.
Specifically, reader verilog model one, use verilog that reader is realized, this verilog model
All functional performance requirements of reader in corresponding RF ID standard agreement can be met.This model is mainly used to simulate reader to mark
Label communicate, such that it is able to whether the various functions performance of checking label chip meets requirement.This model can and reader
SV model one carries out contrast verification.This model can also download on FPGA plank, carries out at plate level simulation reader and label
Communication.Reader verilog model 1～n is reusable module, both can be used in EDA verification environment and carry out simulating, verifying, also
The test checking of FPGA plank enterprising andante level can be downloaded to.
Specifically, reader verilog model two, use verilog that reader is realized, this verilog model
All functional performance requirements of reader in corresponding RF ID standard agreement can be met.This model is mainly used to simulate reader to mark
Label communicate, such that it is able to whether the various functions performance of checking label chip meets requirement.This model can also download to
On FPGA plank, communicate at plate level simulation reader and label.
Specifically, reader verilog model n, use verilog that reader is realized, this verilog model energy
Meet all functional performance requirements of reader in corresponding RF ID standard agreement.This model is mainly used to simulate reader to label
Communicate, such that it is able to whether the various functions performance of checking label chip meets requirement.This model can also download to
On FPGA plank, communicate at plate level simulation reader and label.
Specifically, label SV model one, use system verilog that label SV model is realized, this model is used for
As the reference model of label verilog code, in EDA simulating, verifying, label SV model one can be with label verilog generation
Code (label one RTL) carries out contrast verification.
Specifically, label SV model two, use system verilog that label SV model is realized, this model is used for
As the reference model of label verilog code, in EDA simulating, verifying, label SV model two can be with label verilog generation
Code (label two RTL) carries out contrast verification.
Specifically, label SV model n, use system verilog that label SV model is realized, this model is used for
As the reference model of label verilog code, in EDA simulating, verifying, label SV model n can be with label verilog generation
Code (label n RTL) carries out contrast verification.
Specifically, label one RTL, use hardware description language verilog code to realize, label RTL verilog code
Example module (code of label one RTL～label n RTL is just as, and simply uses different in this verification environment
Name-tag, represents different labels).Label one RTL can carry out the contrast verification of any scene with label SV model one.Should
Code calls can comprehensively, placement-and-routing, final sheet of throwing produce.FPGA can also be downloaded to and carry out plate level debugging.This module is also
The reusable module of EDA and FPGA.
Specifically, label two RTL, use hardware description language verilog code to realize, label RTL verilog code
Example module.Label two RTL can carry out the contrast verification of any scene with label SV model two.This code calls can be combined
Conjunction, placement-and-routing, final head sheet produce.FPGA can also be downloaded to and carry out plate level debugging.This module is also that EDA and FPGA is reusable
Module.
Specifically, label n RTL, use hardware description language verilog code to realize, label RTL verilog code
Example module.Label n RTL can carry out the contrast verification of any scene with label SV model n.This code calls can be combined
Conjunction, placement-and-routing, final sheet of throwing produce.FPGA can also be downloaded to and carry out plate level debugging.This module is also that EDA and FPGA is reusable
Module.
Specifically, label comparison logic one, SV (system verilog) the model one and verilog model one to label
Contrast, use master clock that forward and reverse signal carries out sampling contrast (the important letter in the middle of submodule and module
Number also to pull out and to contrast), contrast when rising edge clock, two models contrasts are inconsistent, report an error, completely than
TEST PASS is then reported to upper.
Specifically, label comparison logic two, SV (system verilog) the model two and verilog model two to label
Contrast, use master clock that forward and reverse signal carries out sampling contrast (the important letter in the middle of submodule and module
Number also to pull out and to contrast), contrast when rising edge clock, two models contrasts are inconsistent, report an error, completely than
TEST PASS is then reported to upper.
Specifically, label comparison logic n, SV (system verilog) the model n and verilog model n of label is entered
Row contrast, uses master clock that forward and reverse signal carries out the sampling contrast (signal of interest in the middle of submodule and module
Also to pull out and contrast), contrast when rising edge clock, two model contrasts are inconsistent, report an error, complete comparison
On then report TEST PASS.
Specifically, VMM (Verification Methodology Manual, verification methodology handbook) test case, adopt
Write with system verilog or verilog.The configuration of each test case and initialization data configure by excel table
Lattice generate, and the configuration file of generation must is fulfilled for the requirement of perl script, because these configurations will be processed by perl step
After pass to VMM verification environment use.
Specifically, VMM environment configuration, the configuration of reader model, label configuration, by perl script according to the most original
The configuration of excel form generates.The form of these configurations must is fulfilled for VMM environment and reads the call format of file, different configurations
The disparate modules passing to example in environment uses.
Specifically, VMM reader excitation maker, use system verilog to write, be i.e. according to reading by excitation
The timing requirements of device beats into above the interface of interface controller, for the selection of subsequent module.
Specifically, VMM label excitation maker, use system verilog to write, i.e. by excitation according to label
Timing requirements beats into above the interface of interface controller, for the selection of subsequent module.
Specifically, interface selection control, at multiple reader SV models, multiple label SV model, multiple reader
The on and off of interface is controlled according to configuration, in order to realize different between verilog model, multiple label RTL code module
Test scene.Main test scene has multiple reader to multiple labels, multiple reader to a label, a reader
To a label, to multiple labels, (wherein reader can be SV model or verilog model to a reader, and label is permissible
For SV model or verilog code).These test scenes can be with application scenarios all of in coverage criteria agreement.
Specifically, interface monitor device and interface assert device, are i.e. described in docking port MUX (selecting control signal path)
The monitoring of interface and asserting.Monitor uses system verilog to realize, and use in verification environment master clock docking port is each
Plant signal to sample, see whether the response of these signals meets standard agreement requirement.Assert that device is some signal in docking port
Infer, such as " the response signal frequency of label n is between 310KHZ～330KHZ ", want if this signal frequency meets
Ask, then assert successfully (code gathering signal frequency needs individually to write, and uses system verilog).
Specifically, reader monitor and reader assert device, and reader verilog model is monitored and is asserted.
Reader external interface signals can be monitored and assert, it is also possible to the interface signal between reader internal submodule
And bottom inside modules signal of interest is monitored and asserts.
Specifically, device asserted by label monitor and label, and label verilog code is monitored and is asserted.Can be right
Label external interface signals is monitored and asserts, it is also possible to the interface signal between inside tags submodule and bottom module
Internal signal of interest is monitored and asserts.
Specifically, code coverage and function coverage are collected, and function coverage needs individually to write code, according to standard
The all functional performance indexs required in agreement, use system verilog code to realize, need to be embedded into EDA verification environment
In, enable with one and control its collection or do not collect.Code coverage need not individually write code, and eda software can be
Label verilog code code coverage shown above collects situation.After code coverage is up to standard, just starts collecting function and cover
Rate, function coverage requires that reaching 100% could export.
As shown in Figure 6, the FPGA containing reusable module in detailed description of the invention verifies system, including interface, on n
Position machine software, n reader (products in kind), n Reader radio frequency module, n reader verilog model, n label are penetrated
Frequency module and n label RTL.Described interface communicates with n reader verilog model respectively and is connected.
N Reader radio frequency module and n reader verilog model one_to_one corresponding, and it is in communication with each other connection.It is and reads
Reading device radio-frequency module one is in communication with each other with reader verilog model one and is connected, Reader radio frequency module two and reader
Verilog model two is in communication with each other connection, and Reader radio frequency module n is in communication with each other with reader verilog model n and is connected.
N Tag Radio Frequency module and n label RTL one_to_one corresponding, and it is in communication with each other connection.It is Tag Radio Frequency module one
Being in communication with each other with label one RTL and be connected, Tag Radio Frequency module two is in communication with each other with label two RTL and is connected, Tag Radio Frequency module n with
Label n RTL is in communication with each other connection.
N upper computer software and n reader (products in kind) one_to_one corresponding, and it is in communication with each other connection, n reader
(products in kind) receives n Tag Radio Frequency module by Anneta module (ant 2n+1 by Anneta module (ant-1～ant-n)
～ant-3n) signal that sends.
N reader verilog model receives n Tag Radio Frequency module by Anneta module (ant-n+1～ant-2n)
The signal sent by Anneta module (ant 2n+1～ant-3n).
N reader verilog model is added FPGA control by upper computer software respectively, and adds logic analyser with oscillograph
One communicates connection.
N label RTL adds logic analyser two-phase communication connection respectively with oscillograph.
Specifically, n upper computer software is developed by reader producer, and the transmitting-receiving etc. being used for controlling products in kind reader is grasped
Make, use C language to realize.
Specifically, n reader (products in kind) is developed by reader producer, according to the instruction of upper computer software, Xiang Biao
Sign and issue out corresponding order or order cluster, and receive the signal that label returns.
Specifically, n Reader radio frequency module is developed by reader producer or the exploitation of label producer.Descending mainly complete base
The modulation of band signal, mixing, up-conversion, power amplification, then launched by antenna.The up filter mainly completing to receive signal
Reader baseband module is given after ripple, demodulation, signal amplification.
Specifically, n reader verilog model is write by label producer checking engineer.It is mainly used to object simulating
Reader carries out transmitting-receiving operation to label.
Specifically, n Tag Radio Frequency module mainly complete to receive signal clock recovery, demodulate, filtering etc., complete reflection
The modulation of signal etc. operate.
Specifically, n label RTL is developed by label producer logical design engineer, and RFID standard agreement is carried out hardware
Realize.
Specifically, oscillograph+logic analyser, oscillograph is used for observing the forward and backward signal of reader, and logic is divided
Analyzer is used for analyzing function and the sequential correctness of reader base band.
Particular embodiments described above, has been carried out the purpose of the present invention, technical scheme and beneficial effect the most in detail
Describe in detail bright, be it should be understood that the specific embodiment that the foregoing is only the present invention, be not limited to the present invention.This
Invention expands to any new feature disclosed in this manual or any new combination, and the arbitrary new method that discloses or
The step of process or any new combination.
Claims (10)
1. EDA and the FPGA reusable checking system for passive label chip, it is characterised in that: include that EDA environment is tested
Card system and FPGA environment checking system；
Reader simulink model (1), reader verilog model (2) and excitation in described EDA environment checking system are sent out
Raw device (3) is connected with the input of selection control one (4), the outfan of selection control (4) respectively with label simulink
Model (5), label SV model (6) are connected with the input of DUT (7), described label simulink model (5), label SV model
(6) it is connected with Comparative result device, result detector (9) by selection control two (8) with the outfan of DUT (7)；
Upper computer software (1-1) in described FPGA environment checking system is connected with reader (1-2), reader verilog mould
Type (1-3) is connected with Reader radio frequency module one (1-4), and the algorithm model (1-5) of reader realizes mould by reader plate level
Block (1-6) is connected with Reader radio frequency module two (1-7)；Described reader (1-2), Reader radio frequency module one (1-4) and read
The outfan reading device radio-frequency module two (1-7) is connected with selection control (1-8)；Tag Radio Frequency module (1-9) and DUT (1-10)
Connect；Described selection control (1-8) and Tag Radio Frequency module (1-9) use Anneta module to be in communication with each other；
Reader verilog model (2) in described EDA environment checking system and DUT (7) with in FPGA environment checking system
Reader verilog model (1-3) and DUT (1-10) mutually reuse.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
Carried out writing and debug logical by checking engineer one in, reader simulink model (1) in described EDA environment checking system
Crossing, this model can be simulated reader and be carried out the return detection of excitation transmission and label.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, the actuation generator (3) in described EDA environment checking system is used system verilog to write by checking engineer two.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, the selection control one (4) in described EDA environment checking system, reader simulink model (1) can be controlled, read
Device verilog model (2) and actuation generator (3) and label simulink model (5), label SV model (6) and DUT's (7)
Interface gateway, can select in reader simulink model (1), reader verilog model (2) and actuation generator (3)
Any one road, two-way or three tunnels carry out communicating with label simulink model (5), label SV model (6) and DUT (7).
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, the DUT (7) in described EDA environment checking system is the RTL code of label chip, designer use verilog language
Write.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, Comparative result device in described EDA environment checking system, result detector (9) are to label simulink model (5), label
SV model (6) and DUT (7) verify through the selection of selection control two (8).
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, reader verilog model (1-3) in described FPGA environment checking system is developed by the checking engineer of label producer,
Verilog language is used to realize, it is desirable to can carry out that FPGA is comprehensive, download, it is possible to be simultaneously embedded in EDA environment checking system
Carry out simulating, verifying, be used for below specific scene substituting reader and label interacts.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, the algorithm model (1-5) of the reader in described FPGA environment checking system, by algorithm engineering Shi Kaifa, uses MATLAB
SIMULINK+M language realizes.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, the reader plate level in described FPGA environment checking system realizes module (1-6) and uses DSP+FPGA, the algorithm mould of reader
Type is combined FPGA more jointly complete the interactive operation to label by being downloaded to DSP, DSP after compiling.
EDA and FPGA for passive label chip the most according to claim 1 reusable checking system, its feature exists
In, the DUT (1-10) in described FPGA environment checking system, the RTL verilog code being label chip realizes, this code
Produce to chip production producer the most alternately by generating GDS after checking, comprehensive, placement-and-routing.
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