CN106059538B - A kind of relaxor of included process deviation calibration function - Google Patents
A kind of relaxor of included process deviation calibration function Download PDFInfo
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
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- H—ELECTRICITY
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Abstract
本发明公开了一种自带工艺偏差校准功能的张弛振荡器，包括基准信号发生器、本征振荡器、时间数字转换器和补偿电容阵列，时间数字转换器包括比较器、开关电容电路和计数器；基准信号发生器向开关电容电路中提供第一基准电压，向比较器提供第二基准电压；本征振荡器的输出频率控制开关电容电路，开关电容电路的输出电压接比较器，比较器的输出端接计数器；计数器的输出端接补偿电容阵列，计数器的输出自动调节补偿电容阵列的电容值，相应地改变了本征振荡器的频率。本发明张弛振荡器自带片上校准功能、芯片与芯片之间误差较小，减少了制片成本，提高了芯片的精度。
The invention discloses a relaxation oscillator with a process deviation calibration function, comprising a reference signal generator, an intrinsic oscillator, a time-to-digital converter and a compensation capacitor array. The time-to-digital converter includes a comparator, a switched capacitor circuit and a counter The reference signal generator provides the first reference voltage to the switched capacitor circuit and the second reference voltage to the comparator; the output frequency of the intrinsic oscillator controls the switched capacitor circuit, the output voltage of the switched capacitor circuit is connected to the comparator, and the The output terminal is connected to the counter; the output terminal of the counter is connected to the compensation capacitor array, and the output of the counter automatically adjusts the capacitance value of the compensation capacitor array, correspondingly changing the frequency of the intrinsic oscillator. The relaxation oscillator of the invention is provided with an on-chip calibration function, the error between chips is small, the production cost is reduced, and the precision of the chip is improved.
Description
[technical field]
The present invention relates to the clock generation circuits of integrated circuit, are a kind of relaxation oscillation of included process deviation calibration function
Device.
[background technique]
Relaxation oscillator has been applied to a variety of electronic circuits, and the clock signal generated can replace external crystal-controlled oscillation, shows
Write the complexity and cost of reduction system.Relaxor is higher with frequency stability, the control linearity is good, adjustable extent is wide
The advantages of, it is often used in the clock signal for generating control circuit timing.For example, relaxation oscillator circuit can be used in DC/DC
In converter, counter, shift unit, microcontroller and modulation circuit.
Document 1 (X.Zou, X.Xu, L.Yao and Y.Lian, " A 1-V 450-nW Fully Integrated
Programmable Biomedical Sensor Interface Chip, " IEEE Journal of Solid-State
Circuits, vol.44, no.4, pp.1067-1077, APRIL 2009) it is related to low consumption circuit design in biomedicine
Using a fully integrated programmable biomedical sensor interface chip being proposed, for different types of biomedical letter
Number processing.The chip optimizes power efficiency by using the low power system that two amplifiers form, and structure includes one
Low-noise amplifier, a variable band-pass filter, a programmable-gain grade and a successive approximation simulation-number turn
Parallel operation.Meanwhile the document is also realized using a kind of resistance with adjustability and is being distorted and the high dynamic under low voltage operating
Variation range.Fully integrated in order to reach low-power consumption and on piece, the on chip clock oscillator frequency of whole system is 30kHz, power consumption
For 53nW.This design is to manufacture to complete under 0.35 μm of standard CMOS process, is tested by the power supply of 1V, as a result table
Bright, the power consumption of entire sensor interface chip realizes the circuit design target of low-power consumption down to 445nW.
(K.Ueno, T.Asai, the Y.Amemiya, " A of document 2 30-MHz, 90ppm/ DEG C of fully-integrated
Clock reference generator with frequency-locked loop, " European Solid-State
(ESSCIRC), pp.392-395,2009.) propose one it is steady come keep frequency using frequency-current converter feedback mechanism
Fixed frequency locking loop technique.Currently, clock reference circuit is the important composition portion of number and mixed signal circuit and wireless system
Point.Although quartz oscillator is typically used to provide height accurately reference clock, they and standard CMOS process are not
It is compatible, and the requirement of inexpensive large scale integrated circuit application cannot be unable to satisfy with other circuit element single-chip integrations.
Therefore, in order to design all constant circuit of clock frequency under different technology conditions, Ken Ueno et al.
Have developed a fully integrated clock reference circuit (i.e. frequency locking loop technique).It is selected in the case where no calibration and correction technique
In 20 samples taken, frequency locking ring Technological expression has gone out 2.7% technique change rate, which is lower than Monte Carlo simulation
The result of emulation.Meanwhile although the circuit does not need reference voltage and electric current, but can generate one to temperature and supply voltage not
Sensitive clock frequency.It can not use LC resonance circuit, realize in the case where quartz resonator and MEMS oscillator
Monolithic work, and there is tunability in the wide frequency range of 2100MHz.The structure is relatively simple simultaneously, may be implemented
The circuit design target of low cost and low-power consumption.
The clock circuit produces clock pulses by Frequency Locking loop technique.As shown in Figure 1, the circuit includes one inclined
Circuits, a current comparator, a voltage controlled oscillator (VCO) and a D/A to be changed the mechanism based on frequency-electric current
Converter, and these circuit elements form feedback loop.Wherein, current comparator can sense bias current Ibias and frequency
Rate-current converter exports the difference in size of electric current Iout between the two, and produces the output proportional to this difference
Voltage Vout.Meanwhile voltage controlled oscillator produces the oscillating impulse depending on Vout, frequency after receiving output voltage Vout
Value is fout.Frequency-current converter has received oscillator pulses, and produces the output electric current proportional to fout
Iout.With that is, current comparator compares bias current Ibias and lout again, to generate a Vout resetted.It is this anti-
Infeed mechanism is constantly repeated, and to ensure that Iout and Ibias is close, finally makes clock frequency fout and temperature and supply voltage
It is unrelated.
Document 3 (F.Sebastiano, L.J.Breems, K.A.A.Makinwa, S.Drago, D.M.W.Leenaerts,
Bram Nauta, " Low-Voltage Mobility-Based Frequency Reference for Crystal-Less
ULP Radios " IEEE Journal of Solid-State CircUits, vol.44, no.7, pp.2002-2009, JULY
2009.) a fully integrated oscillator using electron mobility as design reference is proposed, which is one based on electric current
The oscillator of source control, inside the size of current that passes through and electron mobility it is directly proportional.Currently, process deviation is to electron transfer
The influence of rate, it is more insensitive compared with other parameters, such as polysilicon resistance or MIM capacitor.Meanwhile electron mobility
Standard deviation is no more than 2% at room temperature.Although electron mobility (about T larger to the dependence of temperature-1.5), but
The influence of temperature generation can be eliminated by the method for temperature-compensating.In consideration of it, document [3] is proposed based on electron mobility
Fully integrated reference frequency concept.Its frequency error is mainly respectively depending on temperature, power-supply fluctuation and process deviation, from -22 DEG C
To 85 DEG C, frequency changes less than 1.1%, and the voltage change of 0.27V leads to the frequency error less than 0.1%.But it as long as adopts
With compensation schemes appropriate, electron mobility can be used to generate enough to wireless sensor network (WSN) application
Accurately reference frequency, while the design has reached the circuit design requirements of low-voltage and low-power.
Oscillator disclosed in document above does not have through on piece calibration the function of eliminating process deviation, so by technique
Deviation is affected, though have technique deviation compensation, cost is that power consumption is very big.
[summary of the invention]
The technical problem to be solved in the present invention is to provide one kind to have on piece calibration function and error between chip and chip
Small low-power consumption relaxor.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is that, a kind of included process deviation calibration function
Relaxor, including reference generator, natural oscillation device, time-to-digit converter and compensating electric capacity array.Wherein
Time-to-digit converter includes comparator, switched-capacitor circuit and counter；Reference generator is into switched-capacitor circuit
First reference voltage is provided, provides the second reference voltage to comparator；The output frequency of natural oscillation device is injected into switching capacity
Circuit, the output voltage of switched-capacitor circuit connect comparator, and the output of comparator terminates counter；The output of counter, which terminates, mends
Capacitor array is repaid, the capacitance of the output automatic adjustment compensating electric capacity array of counter correspondingly changes natural oscillation device
Frequency.
Above-described relaxor, reference generator include 11 metal-oxide-semiconductors and three resistance, the first metal-oxide-semiconductor,
Second metal-oxide-semiconductor and the 5th metal-oxide-semiconductor are NMOS tube, and other metal-oxide-semiconductors are PMOS tube；The source electrode of 9th metal-oxide-semiconductor connects the 8th metal-oxide-semiconductor
Drain electrode, the source electrode of the 11st metal-oxide-semiconductor connect the drain electrode of the tenth metal-oxide-semiconductor, and the source electrode of remaining PMOS tube connects power supply；The leakage of 5th metal-oxide-semiconductor
Pole connects the drain electrode of the 6th metal-oxide-semiconductor, source electrode ground connection；The drain electrode of first metal-oxide-semiconductor connects the drain electrode of third metal-oxide-semiconductor, source electrode ground connection；Second
The drain electrode of metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, and source electrode is grounded by first resistor；The drain electrode of 9th metal-oxide-semiconductor passes through second resistance
The drain electrode of ground connection, the 11st metal-oxide-semiconductor is grounded by 3rd resistor；The drain electrode of 7th metal-oxide-semiconductor connects the drain electrode of third metal-oxide-semiconductor, grid
Connect the drain electrode of the 6th metal-oxide-semiconductor；The grid of first metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor, the 9th metal-oxide-semiconductor grid and the 11st MOS
The grid of pipe connects the drain electrode of the 7th metal-oxide-semiconductor, the grid of third metal-oxide-semiconductor, the grid of the 4th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor,
The grid of the grid of six metal-oxide-semiconductors, the grid of the 8th metal-oxide-semiconductor and the tenth metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor；The leakage of 9th metal-oxide-semiconductor
Pole is the output end of the first reference voltage, and the drain electrode of the 11st metal-oxide-semiconductor is the output end of the second reference voltage.
Above-described relaxor, reference generator include the 12nd metal-oxide-semiconductor and the 13rd metal-oxide-semiconductor, the tenth
Two metal-oxide-semiconductors and the 13rd metal-oxide-semiconductor are PMOS tube；The source electrode of 12nd metal-oxide-semiconductor and the 13rd metal-oxide-semiconductor connects power supply, and grid connects the 4th
The drain electrode of the drain electrode of metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor is the output end of bias current, connects natural oscillation device；The leakage of 13rd metal-oxide-semiconductor
Pole is the output end of comparator operating current.
Above-described relaxor, natural oscillation device include that Schmidt trigger, phase inverter, capacitor, PMOS are opened
Pipe and NMOS switch pipe are closed, the first end of the compensating electric capacity array connects power supply by PMOS switch pipe, passes through NMOS switch pipe
Ground connection；The second end of compensating electric capacity array is grounded, capacitor and compensating electric capacity array in parallel；The input of Schmidt trigger terminates
The first end of compensating electric capacity array, the output end of Schmidt trigger connect the input terminal of phase inverter, the output end conduct of phase inverter
The grid of the output termination PMOS switch pipe of natural oscillation device and the grid of NMOS switch pipe.
Above-described relaxor, Schmidt trigger include the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor, the 16th
Metal-oxide-semiconductor, the 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor and the 19th metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor and the 18th MOS
Pipe is NMOS tube, and the 16th metal-oxide-semiconductor, the 17th metal-oxide-semiconductor and the 19th metal-oxide-semiconductor are PMOS tube；The source electrode of 17th metal-oxide-semiconductor connects electricity
Source, drain electrode connect the source electrode of the 16th metal-oxide-semiconductor；The drain electrode of 16th metal-oxide-semiconductor terminates the 15th as the output of Schmidt trigger
The drain electrode of metal-oxide-semiconductor, the source electrode of the 15th metal-oxide-semiconductor connect the drain electrode of the 14th metal-oxide-semiconductor, the 14th metal-oxide-semiconductor source electrode ground connection；18th MOS
The drain electrode of pipe connects power supply, the grounded drain of the 19th metal-oxide-semiconductor；The grid of the grid of 18th metal-oxide-semiconductor and the 19th metal-oxide-semiconductor connects
The drain electrode of 16 metal-oxide-semiconductors；The grid of 14th metal-oxide-semiconductor, the grid of the 15th metal-oxide-semiconductor, the 16th metal-oxide-semiconductor grid and the 17th
Input terminal of the gate interconnection of metal-oxide-semiconductor as Schmidt trigger.
Above-described relaxor, the natural oscillation device course of work are as follows: charging current is to capacitor and benefit first
Repay capacitor array charging, after the voltage on capacitor and compensating electric capacity array reaches the high threshold of Schmidt trigger, Shi Mi
The output level of special trigger switchs to low level, and the output level of phase inverter is made to switch to high level, closes PMOS switch pipe, opens
NMOS switch pipe；Capacitor and the electric discharge of compensating electric capacity array, when the voltage of capacitor and compensating electric capacity array drops to Schmidt's touching
When sending out the Low threshold of device, Schmidt trigger output level switchs to low level, and phase inverter closes NMOS switch pipe, opens PMOS and opens
Guan Guan；Capacitor and compensating electric capacity array repeated charge, compensating electric capacity array generate triangular wave, and phase inverter exports rectangular wave.
Above-described relaxor, the switched-capacitor circuit include the 20th metal-oxide-semiconductor, the 21st metal-oxide-semiconductor
And first capacitor, time-to-digit converter further include the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, second
15 metal-oxide-semiconductors, the second capacitor, third capacitor and the second phase inverter；20th metal-oxide-semiconductor to the 25th metal-oxide-semiconductor is all NMOS tube,
The drain electrode of 20th metal-oxide-semiconductor connects the first reference voltage output end of reference generator, and the source electrode of the 20th metal-oxide-semiconductor connects second
The drain electrode of 11 metal-oxide-semiconductors, and be grounded by first capacitor；The source electrode of 21st metal-oxide-semiconductor connects the drain electrode of the 23rd metal-oxide-semiconductor,
And pass through the second capacity earth；The source electrode and drain electrode of 22nd metal-oxide-semiconductor is connect respectively at the both ends of the second capacitor, and grid connects integral
Pulse；The grid of 20th metal-oxide-semiconductor and the grid of the 21st metal-oxide-semiconductor connect two complementary clock signals respectively；23rd
The source electrode of metal-oxide-semiconductor connects the drain electrode of the 24th metal-oxide-semiconductor and connects the inverting input terminal of the comparator, comparator by third capacitor
Non-inverting input terminal and the source electrode of the 24th metal-oxide-semiconductor connect the second reference voltage output end of reference generator, comparator
Output end counter is connect by phase inverter；The grid of 24th metal-oxide-semiconductor connects the first clock signal, the 23rd metal-oxide-semiconductor
Grid connects second clock signal；The grid of 25th metal-oxide-semiconductor connects third clock signal, and drain electrode connects the anti-phase input of comparator
End, source electrode connect the non-inverting input terminal of comparator.
Relaxor of the present invention carries between on piece calibration function, chip and chip that error is smaller, reduce film-making at
This, improves the precision of chip.
[Detailed description of the invention]
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is the schematic diagram of traditional relaxation oscillation clock circuit.
Fig. 2 is the functional block diagram of relaxor of the embodiment of the present invention.
Fig. 3 is the schematic diagram of reference generator of the embodiment of the present invention.
Fig. 4 is the schematic diagram of natural oscillation device of the embodiment of the present invention.
Fig. 5 is the circuit diagram of Schmidt trigger of the embodiment of the present invention.
Fig. 6 is the schematic diagram of time-to-digit converter of the embodiment of the present invention.
Fig. 7 is the timing diagram of relaxor self-calibrating of the embodiment of the present invention.
Fig. 8 is Δ of embodiment of the present invention tdelayAnd tlogicalTime interval figure.
Fig. 9 is the original frequency histogram of 100 Monte Carlo simulation results of the embodiment of the present invention.
Figure 10 is the calibration frequency histogram of 100 Monte Carlo simulation results of the embodiment of the present invention.
The timing diagram of output frequency during Figure 11 is calibration of the embodiment of the present invention.
[specific embodiment]
As shown in Fig. 2, the relaxor of included process deviation calibration function proposed by the invention includes reference signal
Generator, natural oscillation device, time-to-digit converter and compensating electric capacity array.Wherein, time-to-digit converter includes comparing again
Device, switched-capacitor circuit and counter, for measuring the variation of frequency caused by technique change.Reference generator is electric to switch
Capacitive circuit provides the first reference voltage, provides the second reference voltage to comparator；The output frequency of natural oscillation device is injected into out
Powered-down capacitive circuit, the output voltage of switched-capacitor circuit connect comparator, and the output of comparator terminates counter；The output of counter
Compensating electric capacity array is terminated, the capacitance of the output automatic adjustment compensating electric capacity array of counter correspondingly changes intrinsic vibration
Swing the frequency of device.
Specifically, reference generator provides one partially to the charge or discharge of capacitor for natural oscillation device
Set electric current IbiasAnd one be able to maintain comparator normal work electric current Icomp.Meanwhile during self-calibrating, to switch electricity
Capacitive circuit provides reference voltage Vbias1, reference voltage V is provided to comparator circuitbias2。
During the work of natural oscillation device, the output Vout of natural oscillation device is generated mutual by non-overlapping clock generation circuit
The clock signal of benefit, then complementary clock signal is connected to the end clk of switched-capacitor circuit, outputs it frequency and is injected into out
Powered-down capacitive circuit, and the voltage of capacitor has been determined, and the capacitor is connected to the defeated of the comparator of driving digit counter
Enter end.Counter output automatic adjustment compensating electric capacity array and the frequency for correspondingly changing natural oscillation device.In several periods
Later, relative to reference frequency, the frequency of natural oscillation device can keep stable, and entire calibration process is similar to a simple lock
Xiang Huan.Meanwhile being influenced to reduce compensation circuit process deviation itself to the greatest extent to calibration accuracy bring, present invention employs one
A calibration circuit insensitive on piece technique.
Band-gap reference circuit
Reference generator is as shown in figure 3, include 13 metal-oxide-semiconductors and three resistance R1, R2 and R3.Metal-oxide-semiconductor M1, MOS
Pipe M2 and metal-oxide-semiconductor M5 is NMOS tube, and other metal-oxide-semiconductors are PMOS tube.The source electrode of metal-oxide-semiconductor M9 connects the drain electrode of metal-oxide-semiconductor M8, metal-oxide-semiconductor
The source electrode of M11 connects the drain electrode of metal-oxide-semiconductor M10, and the source electrode of remaining PMOS tube connects power supply.The drain electrode of metal-oxide-semiconductor M5 connects the leakage of metal-oxide-semiconductor M6
Pole, source electrode ground connection.The drain electrode of metal-oxide-semiconductor M1 connects the drain electrode of metal-oxide-semiconductor M3, source electrode ground connection.The drain electrode of metal-oxide-semiconductor M2 connects the leakage of metal-oxide-semiconductor M4
Pole, source electrode are grounded by resistance R1.The drain electrode of metal-oxide-semiconductor M9 is grounded by resistance R2, and the drain electrode of metal-oxide-semiconductor M11 is connect by resistance R3
Ground.The drain electrode of metal-oxide-semiconductor M7 connects the drain electrode of metal-oxide-semiconductor M3, and grid connects the drain electrode of metal-oxide-semiconductor M6.The grid of the grid of metal-oxide-semiconductor M1, metal-oxide-semiconductor M2
The grid of pole, the grid of metal-oxide-semiconductor M9 and metal-oxide-semiconductor M11 connects the drain electrode of metal-oxide-semiconductor M7, the grid of metal-oxide-semiconductor M3, metal-oxide-semiconductor M4 grid,
The grid of metal-oxide-semiconductor M5, the grid of metal-oxide-semiconductor M6, the grid of metal-oxide-semiconductor M8 and metal-oxide-semiconductor M10 grid connect the drain electrode of metal-oxide-semiconductor M4.MOS
The drain electrode of pipe M9 is the first reference voltage Vbias1Output end, the drain electrode of metal-oxide-semiconductor M11 is the second reference voltage Vbias2Output
End.
The source electrode of metal-oxide-semiconductor M12 and metal-oxide-semiconductor M13 connect power supply, and grid connects the drain electrode of metal-oxide-semiconductor M4, and the drain electrode of metal-oxide-semiconductor M12 is inclined
Set electric current IbiasOutput end, connect natural oscillation device.The drain electrode of metal-oxide-semiconductor M13 is comparator operating current IcompOutput end.
Metal-oxide-semiconductor M1 and M2 are worked in subthreshold region.M3 and M4 play the role of mirror current source.In addition, one by
The cascade image current of M8, M9, M10, M11 composition, for generating the gate voltage of M8 and M10, to bias voltage Vbias1
And Vbias2Variation it is insensitive (wherein, to bias voltage Vbias1And Vbias2Influence be by switched-capacitor circuit charge infuse
Caused by entering).In addition, M5, M6, M7 form the start-up circuit with the characteristics of compact area.
Bias current IbiasIt is equal to:
Wherein VT=kT/q is a thermal voltage unrelated with technique, it and absolute temperature is proportional, and KM1、KM2、KM3、
KM4The W/L ratio of corresponding transistor.In general, VTValue be at room temperature about 26mV, and such a Weak current IbiasIt can
By increasing R1Value obtain.According to expression formula (1), bias current will be by the W/L ratio of transistor, absolute voltage and R1
It determines.In order to reduce silicon area, the transistor to work under linear region can be used in and replace resistance R1.However, this is one
Kind using sacrificial system stability and increase to technique change sensibility as the method for cost.
Natural oscillation device
As shown in figure 4, natural oscillation device include two current sources, as the Schmidt trigger of comparator, as buffering
The phase inverter of device, capacitor Cr, two PMOS tube and NMOS tube as switch.
The mirror current source of natural oscillation device is with bias current IbiasAs input signal.
Compensating electric capacity array CCFirst end power supply is connect through the first current source by PMOS switch pipe, pass through NMOS switch pipe
It is grounded through the second current source.The second end of compensating electric capacity array is grounded, capacitor CrWith compensating electric capacity array CCIt is in parallel.Schmidt
The input of trigger terminates compensating electric capacity array CCFirst end, the output end of Schmidt trigger connects the input terminal of phase inverter,
The output end of phase inverter terminates the grid of the PMOS tube and NMOS tube as switch as the output of natural oscillation device.
Using Schmidt trigger as comparator, power consumption can be further reduced.Schmidt trigger includes MOS
Pipe M14, metal-oxide-semiconductor M15, metal-oxide-semiconductor M16, metal-oxide-semiconductor M17, metal-oxide-semiconductor M18 and metal-oxide-semiconductor M19, wherein metal-oxide-semiconductor M14, metal-oxide-semiconductor M15 and
Metal-oxide-semiconductor M18 is NMOS tube, and metal-oxide-semiconductor M16, metal-oxide-semiconductor M17 and metal-oxide-semiconductor M19 are PMOS tube.The source electrode of metal-oxide-semiconductor M17 connects power supply, leakage
Pole connects the source electrode of metal-oxide-semiconductor M16.Drain electrode of the drain electrode of metal-oxide-semiconductor M16 as the output termination metal-oxide-semiconductor M15 of Schmidt trigger, MOS
The source electrode of pipe M15 connects metal-oxide-semiconductor M14 drain electrode, metal-oxide-semiconductor M14 source electrode ground connection.The drain electrode of metal-oxide-semiconductor M18 connects power supply, the leakage of metal-oxide-semiconductor M19
Pole ground connection.The grid of metal-oxide-semiconductor M18 and the grid of metal-oxide-semiconductor M19 connect the drain electrode of metal-oxide-semiconductor M16.The drain electrode of metal-oxide-semiconductor M15, metal-oxide-semiconductor M16
Drain electrode, the grid of metal-oxide-semiconductor M18 and output end of the gate interconnection as Schmidt trigger of metal-oxide-semiconductor M19.
If the electric current that natural oscillation device is charged and discharged is equal, the clock cycle be can simplify are as follows:
The specific work process of natural oscillation device is as follows: charging current is to capacitor C firstrWith compensating electric capacity array CCIt fills
Electricity, as capacitor CrWith compensating electric capacity array CCOn voltage reach the high threshold of Schmidt trigger after, Schmidt trigger
Output level from high to low so that the level of phase inverter is from low to high, close the PMOS switch of control charging current,
The NMOS switch of control discharge current is opened, then capacitor CrWith compensating electric capacity array CCStart to discharge, as capacitor CrWith
Compensating electric capacity array CCOn voltage when reaching Low threshold, the output level of Schmidt trigger changes, and closes NMOS switch, beats
PMOS switch is opened, so, capacitor CrWith compensating electric capacity array CCIt starts to charge again, this process is repeated later, constant current
Constantly to capacitor CrWith compensating electric capacity array CCCharge and discharge, capacitor CrWith compensating electric capacity array CCUpper generation triangular wave, instead
The output of phase device generates rectangular wave.
Wherein, VthhAnd VthlIt is the threshold value of Schmidt trigger, CrIt is charge and discharge capacitance, CCIt is the compensation electricity that initial value is 0
Vessel array, IchargeIt is IbiasImage current.Due to the long clock cycle of nearly 100 μ s, by Schmidt trigger and phase inverter
The caused delay within 10ns is ignored.
Time-to-digit converter
As shown in Figure 5 and Figure 6, time-to-digit converter includes comparator, switched-capacitor circuit and counter.Switching capacity
Circuit includes metal-oxide-semiconductor M20, metal-oxide-semiconductor M21 and first capacitor C1, time-to-digit converter further include metal-oxide-semiconductor M22, metal-oxide-semiconductor M23,
Metal-oxide-semiconductor M24, metal-oxide-semiconductor M25, the second capacitor C2, third capacitor CSWith the second phase inverter.Metal-oxide-semiconductor M20 to metal-oxide-semiconductor M25 is NMOS
Pipe, the drain electrode of metal-oxide-semiconductor M20 meet the first reference voltage output end V of reference generatorbias1, the source electrode of metal-oxide-semiconductor M20 meets MOS
The drain electrode of pipe M21, and pass through first capacitor C1Ground connection.The source electrode of metal-oxide-semiconductor M21 connects the drain electrode of metal-oxide-semiconductor M23, and passes through the second electricity
Hold C2Ground connection.The source electrode and drain electrode of metal-oxide-semiconductor M22 is connect respectively in the second capacitor C2Both ends, grid connects integrated pulse.Metal-oxide-semiconductor M20
Grid and the grid of metal-oxide-semiconductor M21 meet two complementary clock signal Clk and Clk ' respectively.The source electrode of metal-oxide-semiconductor M23 connects metal-oxide-semiconductor
The drain electrode of M24 simultaneously passes through third capacitor CSConnect the inverting input terminal of comparator, the non-inverting input terminal of comparator and metal-oxide-semiconductor M24's
Source electrode meets the second reference voltage output end V of reference generatorbias2, the output end of comparator connects counting by phase inverter
Device.The grid of metal-oxide-semiconductor M24 meets the first clock signal S1, and the grid of metal-oxide-semiconductor M23 meets second clock signal S2.The grid of metal-oxide-semiconductor M25
Pole meets third clock signal Sla, and drain electrode connects the inverting input terminal of comparator, and source electrode connects the output end of comparator.
Time-to-digit converter is other than the control signal of metal-oxide-semiconductor M22 is generated by external crystal oscillator, other control letters
It number is generated by original clock.S1a, S1, S2 are generated by frequency-halving circuit and non-overlapping clock circuit, and effect is control
Offset voltage processed eliminates the timing of circuit, and integrated pulse circuit is generated by external crystal oscillator, for determining the time of calibration
It (is the equal of one Perfect Time of external offer, by time-to-digit converter, so that clock frequency and reference that on piece generates
Frequency is consistent).
Clk and Clk ' is the two complementary clock signals generated by non-overlapping circuit.Switching tube M20, M21 and capacitor
C1、C2It has been interconnected to form a typical switched-capacitor circuit.
Firstly, C1And C2Initial value be 0, V after the first clock cyclec2(0) increase to Vbias1Half, then exist
V after second clock cyclec2(1) increase to Vc2(0) half, later Vc2(n) it is equal to 1.5VC2(n-1)。C2The time of integration
It is switched on and off M22 to be controlled, Vbias1It is reference voltage above-mentioned.Vbias2Size be arranged in 0.5Vbias1And 0.75Vbias1Between.
Calibration process performance is as follows: with the injection of integrated pulse, switch M22 is periodically closed and turns off.It is closed in M22
Before conjunction, voltage Vc2Increase to 0.5V after period first timebias.The output of comparator will not change its logic electricity during this period
It is flat.After a half period, Vc2Rise to 0.75Vbias.Then, the output logic level of comparator can change and generate
One failing edge signal carrys out actuation counter and starts counting.Hereafter, turning on the switch M22 makes MC2Become 0, meanwhile, one was calibrated
Journey terminates.Work as Mc2Reach 0.75VbiasWhen, comparator generates a failing edge signal, this shows if 1.5TclkThan switch M22
The time T of settingintIt is smaller, until 1.5TclkNo less than TintBefore, TclkIt is unstable, and compensating electric capacity array is herein
Period can continue to change.Due to T at the beginningintIt is arranged to compare 1.5TclkIt is bigger, TclkTo constantly it increase, to guarantee 1.5Tclk
Close to Tint.Work as TclkIncreased time step is close to Tclk0.2% or so when, it is available if ignoring time step error:
Wherein, TclkIt is clock cycle, tdIt is the delay time of comparator, TintWhen being the integral determined by external pulse
Between.So basic cycle TrefIt can indicate are as follows:
Wherein tlogicalIt is in the time interval between the high logic output levels of comparator and low logic output level.
M23, M24, M25 form a typical offset voltage and eliminate circuit, in this circuit, it is contemplated that speed and are injected by charge
Caused noise and chip area, CSUsing the sampling capacitor of a 500fF.
As shown in fig. 7, VclkIt is the waveform of clock Clk, Clk ' is the waveform opposite with Clk, VoutIt is the output of comparator,
Vcounter_1bit is the output of counter lowest order, VintIt is integrated pulse waveform, is generated by outside, VC2It is capacitor C2On
Voltage waveform, when second failing edge of clock signal carrys out interim, VC2By 0.5Vbias1Reach 0.75Vbias1, at this point, will triggering
The output logic level of comparator changes into low level, and this when by high level, and counter starts counting.(Ms1aFor than
Compared with the operating phase waveform of device, low level work eliminates state in offset voltage in relatively state, high level work).
The analysis of relaxor technique change
Merge (1) and (2), last clock cycle expression formula is as follows:
Wherein, m indicates KM1KM4With KM2KM3Ratio.In view of fabrication error, and assume Vth=Vthh-Vthl, equation (5)
It can be rewritten as:
Here transistor KM1、KM2、KM3、KM4Mismatch error ignore.It can thus be seen that main error source comes
From in resistance Rl, capacitor CrAnd the threshold voltage V of Schmidt triggerth.Passing through 0.18 micron of 1P6M standard technology of UMC
In the circuit of realization, Rl、Cr、VthChange rate (σ) be respectively ± 8%, ± 8% and ± 5%.Least ideally,
Entire error amount is about 23% as caused by process deviation.
On piece calibration
The reliability of time-to-digit converter depends on C1、C2、Vbias1With Vbias2Between good fitting.And two above
Voltage depends on resistance R2With R3Ratio, (such as common centroid) can be achieved by being commonly laid out skill.If considering
The variation of comparator delay time as caused by process deviation, equation (4) can be rewritten are as follows:
If 70%Vdd and 30%Vdd, it is considered to be the output high level of the reverser in Fig. 6 before counter and low
Level, then running 100 times as a result, its input voltage, the i.e. output voltage of comparator, the worst feelings according to Monte Carlo simulation
Variation range under condition is respectively 0-434.5mV and 482.3mV-1V.(such as according to the result of 100 Monte Carlo simulations emulation
Shown in Fig. 8), when injecting comparator with the electric current of 400nA, by suitably adjusting the size of transistor in comparator, equation
(7) second part in, i.e., two time intervals exported between threshold voltages remain close to 0.2 μ s in the worst cases.
It means that when reference frequency is close to 10K, TrefAnd TintBetween time error rate be about 0.2%.According to above point
Analysis, the constant error as caused by process deviation are about ± 23%.In order to realize that 0.2% resolution ratio, the present invention use one 9
Counter controls compensation capacitor, which is the counting pulsed drive generated by comparator.When output frequency is stablized,
Calibration loop is turned off.Based on the small delay time variation of comparator, the self-calibrating function of on piece may be implemented.
Beneficial effects of the present invention:
The relaxor for the included on piece calibration function that the embodiment of the present invention is proposed has low in energy consumption, self-calibrating
Function is simple and easy and advantage with high accuracy.Wherein, it is applied as comparator in pierce circuit using Schmidt trigger
In, greatly reduce the power dissipation of circuit；Meanwhile by the variation of automatic sensing output clock frequency, and alternately adjust
Used capacitor carries out charging and discharging, finally makes the clock frequency of oscillator be consistent (as shown in figure 11), realizes electricity
The self-calibrating function on road.Carry out keep frequency relative to utilization frequency-current converter feedback mechanism mentioned in document [2]
Stable frequency locking loop technique, 0.31% process sensitive degree that the present invention realizes are far below the 2.7% of frequency locking loop technique, reflect
Self-calibrating function precision of the invention is higher, and effect is more preferable.
It is tested by Monte Carlo simulative emulation, self-calibrating function can be compared to the shadow of oscillator operating frequency
It rings.Fig. 9 shows the working frequency (100 emulation at room temperature) of the oscillator not with self-calibrating function, average
Value and standard deviation value are respectively 19.45kHz and ± 3.72kHz, and error (σ/μ) value is 19.1%.When oscillator operation is in 1V
Supply voltage under, quiescent dissipation 910nW.Output frequency of the embodiment of the present invention with self-calibrating function oscillator is such as
Shown in Figure 10, average value and standard deviation value are respectively 10.24kHz and ± 32.5Hz, and process sensitive degree (σ/μ) is
0.31%.In addition, phase noise of the mentioned oscillator of the present invention in 100Hz is -38dBc/Hz, it is -89dBc/ in 10kHz
Hz, power consumption are lower than 1 μ W.It can be seen that the self-calibrating function that the embodiment of the present invention is proposed is for improving clock circuit design
Accuracy, practicability and stability be of great significance.
The fully integrated oscillator using electron mobility as design reference referred in document 3, is that electron transfer is utilized
This metastable feature of rate, alleviates process deviation caused by frequency drift, passes so as to be used to generate to wireless
The enough accurately reference frequencies of sensor network (WSN) application.It is different from this, the mentioned oscillator of the embodiment of the present invention is metastable
Reference frequency is to drive compensation capacitor to carry out charge or discharge by calibration module, to control the reference frequency of oscillator
It tends towards stability and realizes.
The timing diagram of output frequency during Figure 11 is calibration of the embodiment of the present invention, due to process deviation, original frequency is that have
Great changes.And a stabilizied reference frequency 10.2kHz was obtained by multiple clock cycle.Due to digital code
Non-fully synchronism, obtained spike can be observed.In addition, invention applies a simple binary numbers
Word code is used to control the compensation capacitor in the operating circuit, to generate multiple pulses.With compensating electric capacity weight
Increase, pulse becomes steeper, and due to above-mentioned step error, final calibration result is higher by 0.1% than theoretical calculation.
Claims (7)
1. a kind of relaxor of included process deviation calibration function, which is characterized in that including reference generator, intrinsic
Oscillator, time-to-digit converter and compensating electric capacity array, wherein time-to-digit converter includes comparator, switched-capacitor circuit
And counter；Reference generator provides the first reference voltage to switched-capacitor circuit, provides the second benchmark electricity to comparator
Pressure；The output frequency control switch condenser network of natural oscillation device, the output voltage of switched-capacitor circuit connect comparator, comparator
Output terminate counter；The output of counter terminates compensating electric capacity array, and the output of counter automatically adjusts compensating electric capacity battle array
The capacitance of column correspondingly changes the frequency of natural oscillation device.
2. relaxor according to claim 1, which is characterized in that reference generator include 11 metal-oxide-semiconductors and
Three resistance, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 5th metal-oxide-semiconductor are NMOS tube, and other metal-oxide-semiconductors are PMOS tube；9th metal-oxide-semiconductor
Source electrode connect the drain electrode of the 8th metal-oxide-semiconductor, the source electrode of the 11st metal-oxide-semiconductor connects the drain electrode of the tenth metal-oxide-semiconductor, and the source electrode of remaining PMOS tube connects
Power supply；The drain electrode of 5th metal-oxide-semiconductor connects the drain electrode of the 6th metal-oxide-semiconductor, source electrode ground connection；The drain electrode of first metal-oxide-semiconductor connects the leakage of third metal-oxide-semiconductor
Pole, source electrode ground connection；The drain electrode of second metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, and source electrode is grounded by first resistor；9th metal-oxide-semiconductor
Drain electrode is grounded by second resistance, and the drain electrode of the 11st metal-oxide-semiconductor is grounded by 3rd resistor；The drain electrode of 7th metal-oxide-semiconductor connects third
The drain electrode of metal-oxide-semiconductor, grid connect the drain electrode of the 6th metal-oxide-semiconductor；The grid of first metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor, the 9th metal-oxide-semiconductor
The grid of grid and the 11st metal-oxide-semiconductor connects the drain electrode of the 7th metal-oxide-semiconductor, the grid of third metal-oxide-semiconductor, the grid of the 4th metal-oxide-semiconductor, the 5th
The grid of metal-oxide-semiconductor, the grid of the 6th metal-oxide-semiconductor, the grid of the 8th metal-oxide-semiconductor and the grid of the tenth metal-oxide-semiconductor connect the leakage of the 4th metal-oxide-semiconductor
Pole；The drain electrode of 9th metal-oxide-semiconductor is the output end of the first reference voltage, and the drain electrode of the 11st metal-oxide-semiconductor is the defeated of the second reference voltage
Outlet.
3. relaxor according to claim 2, which is characterized in that reference generator includes the 12nd metal-oxide-semiconductor
With the 13rd metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor and the 13rd metal-oxide-semiconductor are PMOS tube；The source electrode of 12nd metal-oxide-semiconductor and the 13rd metal-oxide-semiconductor
Power supply is connect, grid connects the drain electrode of the 4th metal-oxide-semiconductor, and the drain electrode of the 12nd metal-oxide-semiconductor is the output end of bias current, connects natural oscillation
Device；The drain electrode of 13rd metal-oxide-semiconductor is the output end of comparator operating current.
4. relaxor according to claim 1, which is characterized in that natural oscillation device includes Schmidt trigger, anti-
The first end of phase device, capacitor, PMOS switch pipe and NMOS switch pipe, the compensating electric capacity array connects electricity by PMOS switch pipe
Source is grounded by NMOS switch pipe；The second end of compensating electric capacity array is grounded, capacitor and compensating electric capacity array in parallel；Shi Mi
The first end of the input termination compensating electric capacity array of special trigger, the output end of Schmidt trigger connect the input terminal of phase inverter,
The output end of phase inverter is as the grid of the output termination PMOS switch pipe of natural oscillation device and the grid of NMOS switch pipe.
5. relaxor according to claim 4, which is characterized in that Schmidt trigger includes the 14th metal-oxide-semiconductor, the
15 metal-oxide-semiconductors, the 16th metal-oxide-semiconductor, the 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor and the 19th metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th
Metal-oxide-semiconductor and the 18th metal-oxide-semiconductor are NMOS tubes, and the 16th metal-oxide-semiconductor, the 17th metal-oxide-semiconductor and the 19th metal-oxide-semiconductor are PMOS tube；Tenth
The source electrode of seven metal-oxide-semiconductors connects power supply, and drain electrode connects the source electrode of the 16th metal-oxide-semiconductor；The drain electrode of 16th metal-oxide-semiconductor is as Schmidt trigger
Output the 15th metal-oxide-semiconductor of termination drain electrode, the source electrode of the 15th metal-oxide-semiconductor connects the drain electrode of the 14th metal-oxide-semiconductor, the 14th metal-oxide-semiconductor
Source electrode ground connection；The drain electrode of 18th metal-oxide-semiconductor connects power supply, the grounded drain of the 19th metal-oxide-semiconductor；The grid of 18th metal-oxide-semiconductor and
The grid of 19th metal-oxide-semiconductor connects the drain electrode of the 16th metal-oxide-semiconductor；The grid of 14th metal-oxide-semiconductor, the grid of the 15th metal-oxide-semiconductor, the tenth
Input terminal of the gate interconnection of the grid of six metal-oxide-semiconductors and the 17th metal-oxide-semiconductor as Schmidt trigger.
6. relaxor according to claim 4, which is characterized in that the natural oscillation device course of work is as follows: filling first
Electric current charges to capacitor and compensating electric capacity array, when the voltage on capacitor and compensating electric capacity array reaches schmidt trigger
After the high threshold of device, the output level of Schmidt trigger switchs to low level, and the output level of phase inverter is made to switch to high level, closes
PMOS switch pipe is closed, NMOS switch pipe is opened；Capacitor and the electric discharge of compensating electric capacity array, when capacitor and compensating electric capacity array
When voltage drops to the Low threshold of Schmidt trigger, Schmidt trigger output level switchs to low level, and phase inverter closes NMOS
Switching tube opens PMOS switch pipe；Capacitor and compensating electric capacity array repeated charge, compensating electric capacity array generate triangular wave,
Phase inverter exports rectangular wave.
7. relaxor according to claim 1, which is characterized in that the switched-capacitor circuit includes the 20th
Metal-oxide-semiconductor, the 21st metal-oxide-semiconductor and first capacitor, time-to-digit converter further include the 22nd metal-oxide-semiconductor, the 23rd MOS
Pipe, the 24th metal-oxide-semiconductor, the 25th metal-oxide-semiconductor, the second capacitor, third capacitor and the second phase inverter；20th metal-oxide-semiconductor is to
25 metal-oxide-semiconductors are all NMOS tubes, and the drain electrode of the 20th metal-oxide-semiconductor connects the first reference voltage output end of reference generator
Vbias1, the source electrode of the 20th metal-oxide-semiconductor connects the drain electrode of the 21st metal-oxide-semiconductor, and is grounded by first capacitor；21st metal-oxide-semiconductor
Source electrode connect the drain electrode of the 23rd metal-oxide-semiconductor, and pass through the second capacity earth；The source electrode and drain electrode of 22nd metal-oxide-semiconductor is distinguished
It connects at the both ends of the second capacitor, grid connects integrated pulse；The grid of 20th metal-oxide-semiconductor and the grid difference of the 21st metal-oxide-semiconductor
Connect two complementary clock signals；The source electrode of 23rd metal-oxide-semiconductor connects the drain electrode of the 24th metal-oxide-semiconductor and is connect by third capacitor
The source electrode of the inverting input terminal of the comparator, the non-inverting input terminal of comparator and the 24th metal-oxide-semiconductor connects reference signal
Second reference voltage output end V of devicebias2, the output end of comparator connects counter by phase inverter；The grid of 24th metal-oxide-semiconductor
Pole connects the first clock signal, and the grid of the 23rd metal-oxide-semiconductor connects second clock signal；The grid of 25th metal-oxide-semiconductor connects third
Clock signal, drain electrode connect the inverting input terminal of comparator, and source electrode connects the output end of comparator.
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| CN107493097B (en) * | 2017-07-31 | 2020-02-07 | 天津大学 | Power-on self-reset circuit with long reset time |
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| CN108365836B (en) * | 2018-01-30 | 2024-07-19 | 长沙景嘉微电子股份有限公司 | Novel relaxation oscillator circuit |
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