CN106024902B - The production method of SiC base punch groove MOSFET with high blocking characteristics - Google Patents
The production method of SiC base punch groove MOSFET with high blocking characteristics Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
A kind of production method of the SiC base punch groove MOSFET with high blocking characteristics, made MOSFET blocking ability with higher, it include: that the SiC epitaxial layer that epitaxial growth multilayer difference is adulterated on the substrate of the first conduction type of SiC forms SiC substrate, it is from bottom to top the first conductive type buffer layer, the first conduction type drift layer, the second conductivity type body region layer, the first conduction type source region layer, wherein the first conduction type drift layer thickness meets certain break-through condition；Main line is formed, has at two groove angles of main line radiused, channel bottom is without radiused structure；Etching SiC substrate forms terminal structure；Etching SiC substrate forms base area groove；Formation includes the gate oxide of thick bottom silicon dioxide layer, primary gate oxide, secondary gate oxide three parts in main line；Form gate electrode；Source metal contact is formed in the groove of base area, forms drain metal contacts at the back side of SiC substrate, and form Ohmic contact；Deposit passivation layer and via metal interconnection.
Description
Technical field
The present invention relates to a kind of production methods of SiC trench FET (MOSFET), and in particular to a kind of tool
There is the production method of the SiC base punch groove MOSFET of effective protection channel bottom oxide layer and terminal structure.
Background technique
SiC surmounts the limit of Si base power device with its superior physically and electrically characteristic, and in high pressure, high temperature electric power
Electronic field occupies absolute predominance.In high-end switch power supply, hybrid-electric car and motor-driven field, SiC base
MOSFET can reduce size, weight and encapsulation difficulty, while meet the needs of high frequency, high power, lower transition loss, special
It is not the current class for the node voltages such as 1200V, 1700V and 100A or more, this advantage is more obvious.
Vertical device is mainly based on Dual Implantations type (DMOSFET) and groove-shaped (UMOSFET).For DMOSFET, draw
More low on-resistance, bigger ditch can theoretically be may be implemented with effective protection grid oxygen, and for UMOSFET by entering the region JFET
Track density, thus realize more high current grade.The grid oxygen of UMOSFET is exposed to drift layer, and grid leak is not only made to transmit capacitor mistake
The problems such as big constraint device switch conversion characteristic, while making electric field in oxide excessive under reversed high voltage, especially ditch
The two dimensional electric field of trench bottom is assembled and causes device breakdown in advance, and the operating voltage of device is reduced；Another problem,
The channel of UMOSFET need to realize that the usual roughness of side wall after etching is very high by dry etching, and high temperature tension and
It anneals damage to device, thus the low problem of UMOSFET channel mobility restricts the promotion of its on-state performance.
Summary of the invention
In view of the above-mentioned problems, the object of the present invention is to provide a kind of production sides of SiC base punch groove MOSFET
Method makes up the low problem with on-state characteristic difference of channel mobility, the effective method of secondary design from the design in structure first
The gate oxide and terminal part in groove are protected, so that made SiC base punch groove MOSFET is with higher
Blocking ability.
In order to achieve the above-mentioned object of the invention, the present invention provides a kind of SiC base punch groove with high blocking characteristics
The production method of MOSFET, which comprises the following steps: epitaxial growth is more on the substrate of the first conduction type of SiC
The SiC epitaxial layer of the different doping of layer, forms the SiC substrate of stepped construction, from bottom to top successively are as follows: the buffering of the first conduction type
The source region layer of layer, the body region layer of the drift layer of the first conduction type, the second conduction type, the first conduction type, wherein first leads
The thickness of the drift layer of electric type meets certain break-through condition；Main line is formed on the SiC substrate, the main line
Side wall is the face { 11-20 } system, has radiused structure at two groove angles of main line, channel bottom is without radiused structure；
The SiC substrate is etched, terminal structure is formed；The SiC substrate is etched, is formed and is exposed on the second conductivity type body region layer
The base area groove on surface；Formed in the main line includes thick bottom silicon dioxide layer, primary gate oxide, secondary gate oxidation
The gate oxide of layer three parts；Gate electrode is formed in the main line for having formed the gate oxide；In the base area ditch
Source metal contact is formed in slot, forms drain metal contacts at the back side of the substrate of first conduction type of SiC, and make it
Form Ohmic contact；And passivation layer is deposited on the gate electrode and source metal contact, and via metal interconnects.
The SiC substrate comprising the main line is subjected to high temperature twice additionally, it is preferred that further including steps of
Annealing, for the first time 1600 DEG C~1800 DEG C, SiH4With annealing in the atmosphere of Ar more than half an hour, second 1400 DEG C~
1600℃、H2Atmosphere in annealing it is more than half an hour, formed at two groove angles of the main line have radiused structure,
Channel bottom is without radiused structure.
It is greater than 1 point additionally, it is preferred that further including steps of and etching the main line using reactive ion etching method
Clock, being formed has radiused structure at two groove angles of the main line, channel bottom is without radiused structure, etching gas
For Cl2And O2, gas ratio 7:1, radio-frequency power is 100W~250W, pressure 40mTorr.
Additionally, it is preferred that further include steps of by the SiC substrate comprising the main line 1200 DEG C~
Dry-oxygen oxidation 2 hours or more under conditions of 1500 DEG C, wet etching removes removing oxide layer, repeats this process, until forming the master
There is radiused structure, channel bottom is without radiused structure at two groove angles of groove.
It is carved additionally, it is preferred that further including steps of to fill silica in the main line and return, forms thick bottom
Portion's silicon dioxide layer；Dry-oxygen oxidation half an hour under conditions of 1100 DEG C~1300 DEG C, and in 1200 DEG C~1300 DEG C of temperature
It anneals 1~3 hour under NO atmospheric condition, forms primary gate oxide；On the primary gate oxide, in N2And O2Gas
The source reactive sputtering Al in atmosphere, and AlON is obtained in 900 DEG C of at a temperature of annealing, form secondary gate oxide, the secondary grid oxygen
Change layer with a thickness of 30nm.
Additionally, it is preferred that further include steps of successively deposited in the base area groove 60~100nm Ni, 20~
The multiple layer metal of 40nm Ti, 60~100nm Al, removing form the source metal contact, the source metal contact covering
The upper surface of the base area groove.
Additionally, it is preferred that the thickness of the drift layer of first conduction type make it is described under the blocking state of the MOSFET
Electric field break-through in the drift layer of first conduction type is into the buffer layer of first conduction type, first conduction type
Drift layer thickness and first conduction type drift layer the ratio for being maximally depleted slice width degree that is determined of doping concentration
It is 0.7~0.8.
Additionally, it is preferred that the terminal structure includes the terminal trenches of the same depth formed by a dry etching, close to device
The terminal trenches of part active area are of same size with the main line, and the terminal trenches far from device active region are wide grooves.
Additionally, it is preferred that the terminal structure includes being leaned on by the terminal trenches for the different depth that at least dry etching is formed three times
The terminal trenches of nearly device active region are of same size with the main line, and the terminal trenches far from device active region are wide ditches
Slot, the last one terminal trenches far from device active region are ended in the body region layer of second conduction type.
The present invention has following beneficial effect:
A, compared to common MOSFET element, epitaxial layer meets break-through condition, and selection one by rationally designing
Fixed channel crystal face increases channel mobility, so that the on-state performance of device is effectively improved, so that process costs reduce.
B, groove is only radiused at groove angle, using lamination oxide layer, thick bottom insulation layer, can effectively improve grid oxygen
Change the reliability of layer.
C, the MOSFET groove-shaped based on SiC proposes new terminal structure, effective protection device periphery terminal, lifter
Part blocking ability.
D, the SiC base trench MOSFET, well region or source region adulterate the method for mostly using epitaxial growth, do not have simultaneously
The shielding implanted layer of conventional groove type MOSFET trench bottom reduces the high temperature tension in routine SiC base power device and moves back
Fire process, to reduce the lattice damage to chip, improve device on-state characteristic and reduce cost.
Detailed description of the invention
Fig. 1 is the flow chart of the production method of the SiC base punch groove MOSFET with high blocking characteristics of the invention.
Fig. 2~Fig. 9 is the schematic diagram with the production method of SiC base punch groove MOSFET of high blocking characteristics.Its
In, Fig. 2 is the schematic diagram of the SiC substrate of stepped construction；.1~3.2 Fig. 3 are the schematic diagrames for making main line 6；.1~4.2 Fig. 4
It is the schematic diagram for making terminal structure；Fig. 5 is the schematic diagram for making base area groove；Fig. 6 is showing for the gate oxide of three layers of production
It is intended to；Fig. 7 is the schematic diagram for making gate electrode；Fig. 8 is the schematic diagram for making source metal contact and drain metal contacts；Fig. 9
It is the schematic diagram of passivation and metal interconnection.
Specific embodiment
To further illustrate technology contents of the invention, with reference to embodiments and attached drawing is described in detail.With first
Conduction type is N-shaped, and the second conduction type is to illustrate the SiC base punch with high blocking characteristics of the invention for p-type
The production method of groove MOSFET.
Fig. 1 is the flow chart of the production method of the SiC base punch groove MOSFET with high blocking characteristics of the invention.
It is illustrated below in conjunction with each step of Fig. 2~Fig. 9 to the flow chart of Fig. 1.
S1: the SiC substrate of stepped construction is formed.Referring to Fig. 2, epitaxial growth multilayer is different on the n++ type substrate 1 of SiC
The SiC epitaxial layer of doping forms the SiC substrate of stepped construction.From bottom to top successively are as follows: n+ type buffer layer 2, n-type drift layer 3,
P-type body region layer 4, n+ type source region layer 5.The wherein maximum consumption that the doping of the thickness of n-type drift layer 3 and n-type drift layer 3 is determined
The ratio of slice width degree is 0.7~0.8 to the greatest extent.
S2: main line is formed.Referring to Fig. 3 .1~Fig. 3 .2, main line 6 is made on the SiC substrate that step S1 is completed,
The side wall of main line 6 need to be the face { 11-20 } system, and main line 6 needs guiding through the bottom of p-type body region layer 4 and enters n-type drift layer 3
It is interior, also, there is radiused structure at two groove angles 60,61 of main line 6, channel bottom 63 is without radiused structure.
S3: terminal structure is formed.Referring to Fig. 4 .1~Fig. 4 .2, implement photolithography patterning, deposits and dry etching forms one
Determine the silica of thickness or the mask layer of polysilicon or metal medium, dry etching SiC substrate, formed terminal structure 90 or
91。
S4: base area groove is formed.Referring to Fig. 5, implement photolithography patterning, dry etching forms mask layer 801, continues dry method
Etching SiC substrate forms the base area groove 802 for exposing the upper surface of p-type body region layer 4.
S5: three layers of gate oxide is formed.Referring to Fig. 6, standard cleaning (RCA) SiC substrate utilizes object in main line 6
The methods of reason or chemical vapor deposition form thick bottom silicon dioxide layer 501, utilize the side such as high-temperature thermal oxidation and post-oxidation anneal
Method forms primary gate oxide 502, forms secondary gate oxide 503 using the methods of atomic layer deposition (ALD).As a result, in master
The gate oxide finally obtained in groove 6 includes thick bottom silicon dioxide layer 501, primary gate oxide 502, secondary gate oxide
503 three parts.
S6: gate electrode is formed.Referring to Fig. 7, filling has formed the main line 6 of gate oxide (501,502,503), using dry
The methods of method etching, which is returned, carves deposited filler, deposits and returns again and carves, until planarizing and only retaining trench portions
Filler, to form gate electrode 10.
S7: source metal contact and drain metal contacts are formed.Referring to Fig. 8, implement photolithography patterning, and with diluted HF
The oxide layer for removing base area groove 802, using membrane deposition methods such as electron beam evaporation or sputterings, in base area, groove 802 is successively
The multiple layer metal of 70~90nm Ni, 30~50nm Ti, 80~100nm Al are deposited, removing forms source metal contact 11, source
Pole metal contact 11 need to cover the upper surface of base area groove 802.
Gluing protects front source metal contact 11, and the oxide layer at 1 back side of n++ type substrate, benefit are removed with diluted HF
The membrane deposition methods such as deposited by electron beam evaporation or sputtering overleaf deposited metal as drain metal contacts 12.
Source metal of annealing under 900 DEG C~1100 DEG C of condition of nitrogen gas contacts 11 and drain metal contacts 12, makes its shape
At Ohmic contact.
S8: deposit passivation layer and via metal interconnection.Referring to Fig. 9, deposited on gate electrode 10, source metal contact 11
SiO2And Si3N4Passivation layer 13, and through-hole forms metal interconnection area 14, completes device preparation.
The doping of the n+ type buffer layer 2 for the SiC that the present invention designs need to hindered with thickness, the doping of n- drift layer 3 and thickness
Meet break-through design requirement under disconnected state, is required and customized according to different device stress levels.The following are specific embodiments.
Embodiment
S1: referring to Fig. 2, using the method for chemical vapor deposition or other epitaxial grown materials SiC n++ type substrate 1
The SiC epitaxial layer of upper epitaxial growth multilayer difference doping, forms a kind of stepped construction.N++ type substrate 1 with a thickness of standard 350 μ
M~1000 μm or the method by being machined and chemically reacting carry out a series of thinned, grinding to sample, polish, clear
The techniques such as wash, thickness required for reaching sample surfaces and flatness.The specific epitaxial growth method on n++ type substrate 1
It is as follows:
(a) referring to Fig. 2, n+ type buffer layer 2 is epitaxially formed on n++ type substrate 1, the source of epitaxial growth is silane or trichlorine
Hydrogen silicon, ethylene etc. or propane etc., n+ type buffer layer 2 with a thickness of 1~2 μm, the doping concentration of n+ type buffer layer 2 is 1.0 ×
1018cm-3~1.5 × 1018cm-3, doped source used is the gas sources such as ammonia, and epitaxial growth temperature is 1500 DEG C~1700 DEG C.
(b) referring to Fig. 2, n-type drift layer 3 is epitaxially formed on n+ type buffer layer 2, the source of epitaxial growth is silane or three
Chlorine hydrogen silicon, ethylene etc. or propane etc., doped source used are the gas sources such as ammonia, and epitaxial growth temperature is 1500 DEG C~1700 DEG C.n-
The thickness of type drift layer 3 needs so that the electric field break-through under the blocking state of device in n-type drift layer 3 is into n+ type buffer layer 2,
The ratio for being maximally depleted slice width degree that the thickness of n-type drift layer 3 and the doping concentration of n-type drift layer 3 are determined is 0.7~
0.8.As embodiment, the doping concentration of n-type drift layer 3 is 9.0 × 1015cm-3~1.1 × 1016cm-3, n-type drift layer 3
With a thickness of 10~15 μm.
(c) referring to Fig. 2, p-type body region layer 4 is epitaxially formed on n-type drift layer 3, doped source used is the gas such as trimethyl aluminium
Source, epitaxial growth temperature are 1500 DEG C~1700 DEG C.The doping concentration of p-type body region layer 4 is 1.5 × 1017cm-3~3.5 ×
1017cm-3, p-type body region layer 4 with a thickness of 1.2~1.5 μm.
(d) referring to Fig. 2, n+ source region layer 5 is epitaxially formed in p-type body region layer 4, the source of epitaxial growth is silane or trichlorine hydrogen
Silicon, ethylene etc. or propane etc., n+ source region layer 5 with a thickness of 0.2~0.5 μm, the doping concentration of n+ source region layer 5 is 1.0 ×
1019cm-3~1.0 × 1020cm-3, doped source used is the gas sources such as ammonia, and epitaxial growth temperature is 1500 DEG C~1700 DEG C.
The preparation of epitaxial material is completed by above step.
S2: referring to Fig. 3 .1~Fig. 3 .2, main line 6, the side of main line 6 are made on the epitaxial material that step S1 is completed
Wall need to be the face { 11-20 } system, and main line 6 needs guiding through the bottom of p-type body region layer 4 and enters in n-type drift layer 3, and main line 6 needs
Meeting has radiused structure at two groove angles 60,61, and channel bottom 63 is without radiused structure.It is exemplified below several tools
The implementation method of body.
Implementation method one
(a) referring to Fig. 3 .1, physics and chemical vapor deposition or other membrane deposition methods deposit certain thickness two are utilized
The exposure masks medium such as silica or polysilicon or metal implements photolithography patterning and forms mask layer 701.Silica is as mask layer
It can be 1.8 μm or more if 701, silicon dioxide mask layer need to be in 1000 DEG C or more, O2Under conditions of anneal density.Metal is made
It can be Al, Ni etc. for mask layer 701, thickness is in 800nm or more.Dry etching gas can be C4F8、CHF3、Cl2Deng
Gas.
(b) referring to Fig. 3 .1, the mask layer 701 formed in (a) is utilized, by the etching means such as physics, chemistry, is such as reacted
Ion etching (RIE) or inductively coupled plasma (ICP) etc., dry etching SiC substrate etch main line 6.Etching gas
It can be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/O2Deng combination of gases.
As an example, using SF6/O2The etching gas of/HBr, ICP power are 600W~1000W, and substrate bias power is
100W~300W, temperature are 20 DEG C.Main line 6 needs guiding through 4 bottom of p-type body region layer and enters in n-type drift layer 3, corresponds to step
Parameter setting in rapid S1, the depth of main line 6 can be 1.75~2.25m, and width is 2~4 μm.
(c) referring to Fig. 3 .2, remove the mask layer 701 in (b), height twice will be passed through containing the SiC substrate of main line 6
Warm annealing process, the i.e. first step are at 1600 DEG C~1800 DEG C, SiH4Annealing is more than half an hour in the atmosphere of/Ar, so that two
There is radiused structure, and smooth side wall at groove angle 60,61；Second step is at 1400 DEG C~1600 DEG C, H2Atmosphere in anneal
More than half an hour, smooth surface, finally forms the groove angle 60,61 with obvious radiused structure, ditch in main line 6 again
Trench bottom 63 is without radiused structure.
Implementation method two
In implementation method two, the method for preliminarily forming main line 6 is identical as (a) in implementation method one, (b) two step, no
Same is the third step in implementation method two are as follows:
(c) referring to .1~3.2 Fig. 3, mask layer 701 is kept, utilizes the etch tool of reactive ion etching (RIE), selection
Etching gas is Cl2/O2, gas ratio 7:1, radio-frequency power is 100W~250W, pressure 40mTorr, dry etching SiC
Main line 6 is greater than 1 minute, and the groove angle 60,61 with obvious radiused structure, channel bottom are finally formed in main line 6
63 without radiused structure.
Implementation method three
In implementation method three, the method for preliminarily forming main line 6 is identical as (a) in implementation method one, (b) two step, no
Same is the third step in implementation method three are as follows:
(c) referring to Fig. 3 .2, remove mask layer 701, the item by the SiC substrate containing main line 6 at 1200 DEG C~1500 DEG C
Dry-oxygen oxidation 2 hours or more under part, wet etching removal is formed by certain thickness oxide layer, and wet etching liquid can be
Solution containing HF.This process is repeated, finally forms the groove angle 60,61 with obvious radiused structure, ditch in main line 6
Trench bottom 63 is without radiused structure.
Implementation method four
The method that above-mentioned implementation method one, two, three can be combined forms implementation method four, is finally formed in main line 6
Groove angle 60,61 with obvious radiused structure, channel bottom 63 is without radiused structure.
S3: it referring to Fig. 4 .1~Fig. 4 .2, is deposited using physically or chemically vapor deposition or other membrane deposition methods certain
The exposure masks medium such as the silica or polysilicon of thickness or metal medium is implemented photolithography patterning and forms mask layer, covered using this
Film layer, by physically or chemically waiting etchings means, such as reactive ion etching (RIE) either inductively coupled plasma (ICP),
Dry etching SiC substrate forms terminal structure 90 or 91.The etching gas can be SF6/O2、NF3/Ar、CF4、CHF3/
O2、C4F8/O2Deng combination of gases, the terminal structure 90 or 91 for etching formation has following several types:
Type one:
Referring to Fig. 4 .1, the terminal structure 90 of dry etching is to form unified depth by a dry etching, is had close to device
Terminal trenches 901~903 near source region are of same size with main line 6, far from the terminal trenches 904 near device active region
It is wide groove.Corresponding to the parameter setting in step S1, the depth of terminal trenches 901~904 can be 0.5~0.6 μm.
Type two:
Referring to Fig. 4 .2, the terminal structure 91 of dry etching, be by least dry etching forms the terminal slot of different depth three times,
In to scheme for three grooves, wherein terminal trenches 911~913 and the width phase of main line 6 near device active region
Together, 914 far from the alternatively terminal trenches near device active region can be wide groove, the last one terminal trenches 914
It need to end in p-type body region layer 4.
Type three:
By changing the number of the terminal trenches 901~903 of type one and the terminal trenches 911 of spacing or type two
~913 number and width, forms new terminal structure.Three kinds of terminal structures be only specific embodiments of the present invention and
, it is not intended to restrict the invention.
After the completion of terminal structure etching, corresponding mask layer is removed.
S4: referring to Fig. 5, certain thickness dioxy is deposited using physics and chemical vapor deposition or other membrane deposition methods
The exposure masks medium such as SiClx or polysilicon or metal medium implements photolithography patterning and forms mask layer 801, using the mask layer 801,
Pass through physically or chemically equal etchings means, such as reactive ion etching (RIE) either inductively coupled plasma (ICP), dry method
Etching SiC substrate forms the base area groove 802 for exposing 4 upper surface of p-type body region layer.The etching gas can be SF6/O2、
NF3/Ar、CF4、CHF3/O2、C4F8/O2Deng combination of gases, etching after the completion of remove mask layer 801.
S5: gate oxide is formed.Standard cleaning (RCA) SiC substrate first, specific as follows:
A. it is successively cleaned with acetone and EtOH Sonicate, then is rinsed with deionized water.
B. the SiC substrate after organic ultrasonic is placed in the concentrated sulfuric acid and hydrogen peroxide solution and at least boils 10min.
C. the SiC substrate for boiling the concentrated sulfuric acid is successively boiled into 10min or more with No.1 liquid and No. two liquid respectively, then uses deionization
Water is stand-by with being dried with nitrogen after rinsing well.No.1 liquid is the mixed liquor of ammonium hydroxide, hydrogen peroxide and deionized water, and No. two liquid are salt
The mixed liquor of acid, hydrogen peroxide and deionized water.
D. the substrate after flushing is put into hydrofluoric acid and impregnates at least 1min, remove surface oxide layer.
Referring to Fig. 6, on the SiC substrate after standard cleaning (RCA), by physically or chemically waiting membrane deposition methods
The gate oxide with low-leakage current, high reliability is formed with conditions such as etch tool and thermal oxides.Specific step is as follows:
(a) a half an hour left side need to be aoxidized under 1100 DEG C or so of wet oxygen environment by the SiC substrate of standard cleaning (RCA)
Right formation sacrificial oxide layer, and the sacrificial oxide layer is removed by the rinsing of diluted HF ultrasound.
(b) it is formed by main line 6 using physically or chemically the methods of vapor deposition in step S2 and fills silica
500, using physically or chemically etch tool, the silica 500 filled in dry or wet etch main line 6, until protecting
The part below of p-type body region layer 4 is stayed, thick bottom silicon dioxide layer 501 is formed.
(c) on the SiC substrate containing thick bottom silicon dioxide layer 501, dry oxygen oxygen under conditions of 1100 DEG C -1300 DEG C
Change or so half an hour, and anneal 1-3 hours at 1200 DEG C -1300 DEG C of temperature and NO atmospheric condition, forms primary gate oxidation
Layer 502.The annealing atmosphere is not only NO, is also possible to POCl3, H2, N2O, P2O5, Sb+NO etc..
(d) on primary gate oxide 502, in N2/O2Atmosphere in the source reactive sputtering Al, and in 900 DEG C anneal obtain
AlON forms secondary gate oxide 503.For secondary 503 thickness of gate oxide in 30nm or so, secondary gate oxide 503 can also be with
It is the Al deposited by the method for atomic layer deposition2O3Film.
The gate oxide finally obtained includes thick bottom silicon dioxide layer 501, primary gate oxide 502, secondary gate oxidation
503 three parts of layer, can effectively protect the reliability of the gate oxide under blocking state, promote the blocking ability of groove MOSFET.
S6: referring to Fig. 7, the tap drain of gate oxide (501,502,503) has been formed using the filling of isotropic deposition technology
Slot 6, filler can be DOPOS doped polycrystalline silicon or silicide with high conductance.Return what quarter was deposited using the methods of dry etching
Filler is deposited again and is returned and carves, until the filler of trench portions is planarized and only retain, to form gate electrode 10.
S7: referring to Fig. 8, implement photolithography patterning, and remove the oxide layer of base area groove 802 with diluted HF, utilize electricity
The membrane deposition methods such as beamlet evaporation or sputtering, in base area, groove 802 successively deposits 60~100nm Ni, 20~40nm Ti, 60
The multiple layer metal of~100nm Al, removing form source metal contact 11, and source metal contact 11 need to cover base area groove 802
Upper surface.Alternatively, source metal contact 11 can be other metallic combinations such as AlTi, Ni, TiW.
Referring to Fig. 8, gluing protects positive source metal contact 11, and removes 1 back side of n++ type substrate with diluted HF
Oxide layer, AlTi, the 300~400nm for overleaf depositing 20nm thickness using membrane deposition methods such as electron beam evaporation or sputterings are thick
Ni metal layer as drain metal contacts 12.Alternatively, drain metal contacts 12 can be AlTi, Ni, TiW, AlTi etc.
Other metallic combinations.
Referring to Fig. 8, in N2Under environment, 900 DEG C~1100 DEG C annealing are formed by source metal contact 11, drain metal connects
Touching 12, time are 1~3 minute, and annealing atmosphere is also possible to Ar or H2+N2。
S8: it is connect using other deposition methods such as physical vapour deposition (PVD) or chemical vapor deposition in source metal referring to Fig. 9
The SiO2 and Si3N4 of 1 μm of the upper surface of touching 11, gate electrode 10 deposition or more are as passivation layer 13.Implement photolithography patterning, selection is carved
Gas dry etching passivation layer 13 is lost, metal throuth hole is formed.Lithographic method can be reactive ion etching (RIE) either inductance
Other physics and the chemical etching methods such as coupling plasma (ICP), etching gas can be fluorine-based gas.It is steamed using electron beam
The membrane deposition methods such as hair or sputtering deposit 1.5 μm of thick metal layers, and photolithography patterning on passivation layer 13, are interconnected and form
The region metal pad 14, this completes the preparations of device.
Describe the preferred embodiment of the present invention above, but the spirit and scope of the present invention be not limited to it is disclosed herein
Particular content.Those skilled in the art can it is according to the present invention introduction and make more embodiments and application, these realities
Applying mode and application would be within the spirit and scope of the present invention.The spirit and scope of the present invention are not limited by specific embodiment,
And it is defined by the claims.
Claims (9)
1. a kind of production method of the SiC base punch groove MOSFET with high blocking characteristics, which is characterized in that including following
Step:
The SiC epitaxial layer that epitaxial growth multilayer difference is adulterated on the substrate (1) of the first conduction type of SiC forms stepped construction
SiC substrate, from bottom to top successively are as follows: the buffer layer (2) of the first conduction type, the drift layer (3) of the first conduction type, second
The source region layer (5) of the body region layer (4) of conduction type, the first conduction type, wherein the thickness of the drift layer (3) of the first conduction type
Meet certain break-through condition；
Main line (6) are formed on the SiC substrate, the side wall of the main line (6) is the face { 11-20 } system, the main line
Two groove angles (60,61) at have radiused structure, channel bottom (63) is without radiused structure；
The SiC substrate is etched, is formed terminal structure (90,91)；
The SiC substrate is etched, the base area groove (802) for exposing the second conductivity type body region layer (4) upper surface is formed；
Formed in the main line (6) includes thick bottom silicon dioxide layer (501), primary gate oxide (502), secondary grid oxygen
Change the gate oxide of layer (503) three parts；
Gate electrode (10) are formed in the main line (6) for having formed the gate oxide；
Source metal contact (11) is formed in the base area groove (802), in the substrate (1) of first conduction type of SiC
The back side form drain metal contacts (12), and form it into Ohmic contact；And
Passivation layer is deposited on the gate electrode (10) and source metal contact (11), and via metal interconnects.
2. the production method of the SiC base punch groove MOSFET according to claim 1 with high blocking characteristics, special
Sign is, further includes steps of
High annealing twice will be carried out comprising the SiC substrate of the main line (6), for the first time 1600 DEG C~1800 DEG C,
SiH4With annealing in the atmosphere of Ar more than half an hour, second 1400 DEG C~1600 DEG C, H2Atmosphere in anneal half an hour
More than, being formed has radiused structure at two groove angles (60,61) of the main line (6), channel bottom (63) is without circular arc
The structure of change.
3. the production method of the SiC base punch groove MOSFET according to claim 1 with high blocking characteristics, special
Sign is, further includes steps of
The main line (6) is etched using reactive ion etching method to be greater than 1 minute, forms two slots of the main line (6)
There is radiused structure, channel bottom (63) is without radiused structure, etching gas Cl at angle (60,61)2And O2, gas
Ratio is 7:1, and radio-frequency power is 100W~250W, pressure 40mTorr.
4. the production method of the SiC base punch groove MOSFET according to claim 1 with high blocking characteristics, special
Sign is, further includes steps of
Will the SiC substrate comprising the main line (6) under conditions of 1200 DEG C~1500 DEG C dry-oxygen oxidation 2 hours with
On, wet etching removes removing oxide layer, this process is repeated, until having at two groove angles (60,61) of the formation main line (6)
Radiused structure, channel bottom (63) is without radiused structure.
5. the production method of the SiC base punch groove MOSFET according to claim 1 with high blocking characteristics, special
Sign is, further includes steps of
Filling silica and time quarter, form thick bottom silicon dioxide layer (501) in the main line (6)；
Dry-oxygen oxidation half an hour under conditions of 1100 DEG C~1300 DEG C, and in 1200 DEG C~1300 DEG C of temperature and NO atmosphere item
It anneals 1~3 hour under part, forms primary gate oxide (502)；
On the primary gate oxide (502), in N2And O2Atmosphere in the source reactive sputtering Al, and 900 DEG C at a temperature of move back
Fire obtains AlON, forms secondary gate oxide (503), the secondary gate oxide (503) with a thickness of 30nm.
6. the production method of the SiC base punch groove MOSFET according to claim 1 with high blocking characteristics, special
Sign is, further includes steps of
The multilayer of 60~100nm Ni, 20~40nm Ti, 60~100nm Al are successively deposited in the base area groove (802)
Metal, removing form the source metal contact (11), and the source metal contact (11) covers the base area groove (802)
Upper surface.
7. the system of the SiC base punch groove MOSFET described according to claim 1~any one of 6 with high blocking characteristics
Make method, which is characterized in that
The thickness of the drift layer (3) of first conduction type makes first conductive-type under the blocking state of the MOSFET
Electric field break-through in the drift layer (3) of type is into the buffer layer (2) of first conduction type, the drift of first conduction type
The ratio for being maximally depleted slice width degree that the doping concentration of the drift layer (3) of the thickness and first conduction type of shifting layer (3) is determined
Value is 0.7~0.8.
8. the system of the SiC base punch groove MOSFET described according to claim 1~any one of 6 with high blocking characteristics
Make method, which is characterized in that
The terminal structure (90) includes the terminal trenches (901~904) of the same depth formed by a dry etching, wherein
Wide groove far from the outermost terminal trenches (904) of device active region, remaining terminal trenches (901~903) with it is described
Main line (6) it is of same size.
9. the system of the SiC base punch groove MOSFET described according to claim 1~any one of 6 with high blocking characteristics
Make method, which is characterized in that
The terminal structure (91) include by least three times dry etching formed different depth terminal trenches (911~914),
In, the outermost terminal trenches (914) far from device active region are wide grooves, and the terminal trenches are conductive described second
Cut-off, remaining terminal trenches (911~913) are of same size with the main line (6) in the body region layer (4) of type.
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