CN106024727B - Packaging part and forming method thereof with UBM - Google Patents
Packaging part and forming method thereof with UBM Download PDFInfo
- Publication number
- CN106024727B CN106024727B CN201510667052.9A CN201510667052A CN106024727B CN 106024727 B CN106024727 B CN 106024727B CN 201510667052 A CN201510667052 A CN 201510667052A CN 106024727 B CN106024727 B CN 106024727B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- pattern
- integrated circuit
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 title abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 88
- 239000002184 metal Substances 0.000 claims abstract description 87
- 239000000565 sealant Substances 0.000 claims abstract description 48
- 239000010410 layer Substances 0.000 claims description 494
- 238000001465 metallisation Methods 0.000 claims description 133
- 239000012790 adhesive layer Substances 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 55
- 239000000463 material Substances 0.000 description 45
- 239000000758 substrate Substances 0.000 description 31
- 230000015572 biosynthetic process Effects 0.000 description 17
- 239000004020 conductor Substances 0.000 description 17
- 238000007747 plating Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 13
- 238000000059 patterning Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000004528 spin coating Methods 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 239000003292 glue Substances 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 239000005360 phosphosilicate glass Substances 0.000 description 8
- 229920002577 polybenzoxazole Polymers 0.000 description 8
- 238000000926 separation method Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 238000002844 melting Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000010276 construction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 239000012466 permeate Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 241000208340 Araliaceae Species 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000035508 accumulation Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000206 moulding compound Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses package structures and the method for forming package structure.According to some embodiments, package structure includes：Integrated circuit die；At least laterally seal the sealant of integrated circuit die；Redistribution structure on integrated circuit die and sealant；It is connected to the connector of the support metal layer of redistribution structure；Pseudo- pattern；Second dielectric layer；And the joint outer part on the connector of support metal layer.Redistribution structure includes the first dielectric layer, and the first dielectric layer has the first surface being arranged far from sealant and integrated circuit die.Pseudo- pattern is located on the first surface of the first dielectric layer and around the connector of support metal layer.Second dielectric layer is located on the first surface of the first dielectric layer with pseudo- pattern at least partially.Second dielectric layer does not contact the connector of support metal layer.The invention further relates to the packaging parts and forming method thereof with UBM.
Description
This application involves entitled " the Package with UBM and Methods of submitted on January 26th, 2015
The U.S. Patent Application No. of Forming " 14/605,848, entire contents are incorporated herein by reference as reference.This Shen
Relate to entitled " the UBM Metal Profile for Reliability submitted for 15th in September in 2014
The U.S. Provisional Patent Application of Improvement " the 62/050th, 550, entire contents are incorporated herein by reference as ginseng
It examines.
Technical field
The present invention relates to the packaging parts and forming method thereof with UBM.
Background technology
For example, semiconductor devices is in various electronic applications, such as PC, cell phone, digital camera and its
His electronic equipment.Insulation or dielectric layer, conductive layer and semiconductor material layer are usually sequentially depositing by side on a semiconductor substrate
And semiconductor devices is manufactured to be formed on circuit unit and element using each material layer of lithographic patterning.Usually exist
Tens of or hundreds of integrated circuits is manufactured on single semiconductor crystal wafer.By single to divide come sawing integrated circuit along scribing line
Tube core.Then for example, singulated dies individually or with multicore tablet mode or with other encapsulated types such as are separately packaged.
Semiconductor industry continuously improves various electronic building bricks (for example, crystal by the lasting size for reducing minimal parts
Pipe, diode, resistor, capacitor etc.) integration density, this allows more components to be integrated into given region.
In some applications, the smaller electronic building brick of these such as integrated circuit dies is also required to smaller packaging part, these are smaller
Packaging part utilizes less region than past packaging part.
Invention content
In order to solve the problems in the prior art, according to some embodiments of the present invention, a kind of package structure is provided,
Including：Integrated circuit die；Sealant at least laterally seals the integrated circuit die；Redistribution structure is located at the collection
At in circuit die and the sealant, the redistribution structure includes the first dielectric layer, and first dielectric layer has separate
The first surface of the sealant and integrated circuit die setting；Support the connector of metal layer, the metal layer
It is connected to the redistribution structure, the connector of the support metal layer has first part and a second part, and described first
Part is located on the first surface of first dielectric layer and the second part is across first dielectric layer
Extend in opening；Pseudo- pattern is located on the first surface of first dielectric layer and is located at the support metal layer
Connector around；Second dielectric layer is located on the first surface of first dielectric layer and positioned at the pseudo- pattern
At least partially, second dielectric layer does not contact the connector of the support metal layer；And joint outer part, it is located at
On the connector of the support metal layer.
Other embodiments according to the present invention provide a kind of package structure, including：Integrated circuit die；Sealing
Agent at least laterally seals the integrated circuit die；Redistribution structure is located at the integrated circuit die and the sealant
On, the redistribution structure includes the first dielectric layer, and first dielectric layer is far from the sealant and the integrated circuit pipe
Core is arranged；The connector of metal layer, the metal layer is supported to be connected to the redistribution structure, the support metal layer
Connector there is first part, second part and Part III, the first part is located at the first of first dielectric layer
On surface, the second part extends along the bottom surface of the first opening across first dielectric layer, and the third portion
Divide the side wall extension along first opening and between the first part and the second part, junction is formed in
The second part contacts at the position of the Part III；Second dielectric layer is located at described the first of first dielectric layer
On surface extremely with the first part, the Part III and the second part of the connector of the support metal layer
In a few part；And joint outer part, pass through second to be open and be located on the connector of the support metal layer, it is described
Second opening is across second dielectric layer.
Other embodiment according to the present invention, provides a method, including：Integrated circuit pipe is sealed with sealant
Core；Redistribution structure is formed on the integrated circuit die and the sealant, the redistribution structure includes the first dielectric
Layer, first dielectric layer have the first surface being arranged far from the integrated circuit die and the sealant；Described heavy
Underbump metallization layer (UBM) and pseudo- pattern are formed on distributed architecture, the puppet pattern is around the described of first dielectric layer
The UBM on first surface；On the first surface of first dielectric layer and at least one of the pseudo- pattern
Divide upper formation the second dielectric layer, wherein after forming second dielectric layer, second dielectric layer does not contact the UBM；
And form external electrical connections on the UBM.
Description of the drawings
When reading in conjunction with the accompanying drawings, from it is described in detail below can best understanding each aspect of the present invention.It should be noted that
According to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, the ruler of all parts
It is very little to arbitrarily increase or reduce.
Fig. 1 to Figure 14 is the intermediate steps in accordance with some embodiments during being used to form the technique of package structure
Sectional view.
Figure 15 is the sectional view of package structure in accordance with some embodiments.
Figure 16 is the sectional view of package structure in accordance with some embodiments.
Figure 17, Figure 18, Figure 19 A, Figure 20 and Figure 21 are in accordance with some embodiments in the work for being used to form package structure
The sectional view of intermediate steps during skill.
Figure 19 B are the layouts of underbump metallization layer in accordance with some embodiments (UBM) and pseudo- pattern.
Figure 22 is the sectional view of package structure in accordance with some embodiments.
Figure 23 is the sectional view of package structure in accordance with some embodiments.
Figure 24, Figure 25, Figure 26 A, Figure 27 and Figure 28 are in accordance with some embodiments in the work for being used to form package structure
The sectional view of intermediate steps during skill.
Figure 26 B are the sections of the intermediate steps in accordance with some embodiments during being used to form the technique of package structure
The more detailed part of figure.
Figure 26 C are the layout of the UBM across dielectric layer and opening in accordance with some embodiments.
Figure 29 is the sectional view of package structure in accordance with some embodiments.
Figure 30 is the sectional view of package structure in accordance with some embodiments.
Specific implementation mode
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme.
The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, and are not intended to be limited to this
Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second
Component is formed as the embodiment being in direct contact, and can also be included between the first component and second component can be formed it is additional
Component so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be in each reality
Repeat reference numerals and/or letter in example.The repetition is for purposes of simplicity and clarity, and itself not indicate to be discussed
Each embodiment and/or configuration between relationship.
Moreover, for ease of description, can use herein such as " ... under ", " in ... lower section ", " lower part ", " ... it
On ", the spatially relative term on " top " etc., it is (or another with another in order to describe an element as shown in the figure or component
The relationship of element or component a bit).Other than orientation shown in figure, spatially relative term is intended to include that device is being used or operated
In different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space as used herein
Relative descriptors can be explained similarly accordingly.
Embodiments discussed herein can be discussed in specific environment, that is, have and be fanned out to or fan-in wafer-level packaging part
Package structure.Other embodiment is expected other application, and such as different encapsulated types or different configurations are to reading this hair
It will be apparent for bright those of ordinary skill in the art.It should be noted that embodiments discussed herein need not be shown
Each component or the component being likely to be present in structure.For example, such as when one in the component of discussion can convey enough
When the various aspects of embodiment, multiple components can be omitted from figure.In addition, embodiment of the method discussed herein can be discussed
To implement according to particular order；However, it is possible to implement other methods embodiment with any logical order.
Fig. 1 to Figure 14 is the intermediate steps in accordance with some embodiments during being used to form the technique of package structure
Sectional view.Fig. 1 shows carrier substrates 20 and the releasing layer formed in carrier substrates 20 22.Carrier substrates 20 can be glass
Carrier substrates, ceramic monolith substrate etc..Carrier substrates 20 can be wafer.Releasing layer 22 can be formed by polymer-based material,
Releasing layer 22 and loading substrate 20 can be removed together from by the structure of the overlying formed in subsequent step.In some embodiments
In, releasing layer 22 is the hot releasable material of epoxy group of such as photothermal conversion (LTHC) release coating, will be lost when heated
Its bond properties.In other embodiments, releasing layer 22 can be ultraviolet (UV) glue, upon exposure to uv light, it is viscous lose it
Close performance.Releasing layer 22 can be used as liquid distribution and cure, and can be the laminated film etc. being laminated in carrier substrates 20.It can
With formation or spreading adhesive 24 on releasing layer 22.Adhesive 24 can be tube core attachment film (DAF), glue, polymer material
Deng.
Integrated circuit die 26 is attached to carrier substrates 20 (for example, by releasing layer 22) by adhesive 24.As schemed
Show, is attached an integrated circuit die 26, and in other embodiments, more integrated circuit dies can be attached.It is being attached
To before carrier substrates 20, integrated circuit die 26 can be handled in integrated circuit die 26 according to applicable manufacturing process
Middle formation integrated circuit.For example, integrated circuit die 26 include bulk semiconductor substrate, semiconductor-on-insulator (SOI) substrate,
MULTILAYER SUBSTRATE or gradient substrate etc..The semiconductor of substrate may include any semi-conducting material, and the element of silicon, germanium etc. is partly led
Body, including SiC, GaAs, GaP, InP, InAs, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/
Or the compound semiconductor or alloy semiconductor of GaInAsP etc.；Or combination thereof.Such as transistor, diode, capacitor,
The device of resistor etc. can be formed in semiconductor substrate and/or go up and can be interconnected by interconnection structure and be integrated to be formed
Circuit, interconnection structure are formed by, for example, the metallization pattern in one or more dielectric layers in semiconductor substrate.
Integrated circuit die 26 further includes the pad 28 of such as aluminum pad, is manufactured to the external connection of pad 28.Pad 28
Positioned at being properly termed as on the side of active side for integrated circuit die 26.Passivating film 30 is located on integrated circuit die 26 and part
On pad 28.Opening is across passivating film 30 to pad 28.The tube core connection of such as conductive column (e.g., including the metal of such as copper)
Part 32 is located across in the opening of passivating film 30 and mechanically and electrically to corresponding pad 28.For example, plating etc. can be passed through
Form tube core connector 32.Tube core connector 32 is electrically connected the integrated circuit of integrated circuit die 26.In order to what is understood and simplify
Purpose, shows a pad 28 and a tube core connector 32 on integrated circuit die 26, but ordinary skill
Personnel are appreciated that there may be more than one pads 28 and tube core connector 32.
Dielectric material 34 is located in the active side of integrated circuit die 26, such as positioned at passivating film 30 and tube core connector 32
On.Laterally package die connector 32 and dielectric material 34 are laterally total to terminal to dielectric material 34 with integrated circuit die 26.It is situated between
Electric material 34 can be polymer, polybenzoxazoles (PBO), polyimides, benzocyclobutene (BCB) etc..In other realities
It applies in example, dielectric material 34 is by the nitride of such as silicon nitride, such as silica, phosphosilicate glass (PSG), borosilicate
The formation such as the oxide of glass (BSG), boron doped phosphosilicate glass (BPSG) etc..Such as spin coating, chemistry can be passed through
Any acceptable depositing operation of gas deposition (CVD), lamination etc. or combination thereof forms dielectric material 34.It can be such as
By sawing or cutting to divide integrated circuit die 26, and will be collected by adhesive 24 using such as pickup and place tool
It is bonded to carrier substrates 20 at circuit die 26.
In fig. 2, each group on the adhesive 24 around integrated circuit die 26 and/or on integrated circuit die 26
Sealant 36 is formed on part.Sealant 36 can be moulding compound, epoxy resin etc., and can be by being compression molded, transmitting mould
The applications such as modeling.After hardening, sealant 36 can undergo grinding technics to expose tube core connector 32.Grinding technics it
Afterwards, the top surface of tube core connector 32, dielectric material 34 and sealant 36 is coplanar.In some embodiments, if exposed
Tube core connector 32 then can be omitted grinding.
In figure 3, the first dielectric layer 38 and the first metallization pattern 40 of redistribution structure are formed.Fig. 3 and figure later
Show the exemplary configuration of redistribution structure, and in other embodiments, redistribution structure may include any amount of
Dielectric layer, metallization pattern and through-hole, as shown in Figure 15 and Figure 16.
First dielectric layer 38 is formed on sealant 36, dielectric material 34 and tube core connector 32.In some embodiments,
First dielectric layer 38 is formed by polyme, and can use mask by easily patterned such as PBO, polyamides
The light-sensitive material of imines, BCB etc..In other embodiments, the first dielectric layer 38 is by the nitride of such as silicon nitride, such as oxygen
The formation such as oxide of SiClx, PSG, BSG, BPSG.First can be formed by spin coating, lamination, CVD etc. or combination thereof
Dielectric layer 38.Then the first dielectric layer 38 is patterned to form opening to expose part tube core connector 32.It can be by can
The technique of receiving is patterned, and such as when dielectric layer is light-sensitive material, the first dielectric layer 38 is exposed to light alternatively, example
Such as, it is etched by using anisotropic etching.
The first metallization pattern 40 with through-hole 42 is formed on the first dielectric layer 38.Scheme as the first metallization is formed
The example of case 40 and through-hole 42 forms seed layer (not shown) above the first dielectric layer 38.In some embodiments, seed layer
It is metal layer, can is single layer or includes the composite layer for the multiple sublayers being formed from different materials.In some embodiments,
The seed layer includes the layers of copper above titanium layer and titanium layer.It is, for example, possible to use physical vapor deposition (PVD) etc. forms seed layer.
Then it is formed on the seed layer and patterns photoresist.The photoresist can be formed by spin coating etc. and can be exposed to light
For patterning.The pattern of photoresist corresponds to the first metallization pattern 40.Pattern forms the opening across photoresist with sudden and violent
Reveal seed layer.Conductive material is formed in the opening of photoresist and on the expose portion of seed layer.It can be by such as electric
The plating of plating, chemical plating etc. forms conductive material.Conductive material may include metal, such as copper, titanium, tungsten, aluminium.Then, remove
The photoresist and part seed layer of conductive material are not formed thereon.It can be by using the acceptable of oxygen plasma etc.
Ashing or stripping technology remove photoresist.Once photoresist is removed, all such as by using acceptable etch process
The expose portion of seed layer is such as removed by wet or dry ecthing.The remainder of seed layer and conductive material forms the first metallization
Pattern 40 and through-hole 42.Through-hole 42 is formed in the opening across following layer (for example, first dielectric layer 38).
Technique by being recycled and reused for being formed the first dielectric layer 38 and the first metallization pattern 40 can be in redistribution structure
It is middle to form one or more additional metallization patterns and dielectric layer with through-hole.As set forth above, it is possible to metallize being formed
Through-hole is formed during pattern.Therefore through-hole can interconnect and be electrically connected each metallization pattern.One dielectric layer is described, for example,
First dielectric layer 38 and a metallization pattern, for example, the first metallization pattern 40 be for the ease of with the purpose that simply shows.
In Fig. 4, the second dielectric layer 44 is formed on the first metallization pattern 40 and the first dielectric layer 38.In some implementations
Example in, the second dielectric layer 44 is formed by polyme, can be using mask by it is easily patterned such as
The light-sensitive material of PBO, polyimides, BCB etc..In other embodiments, the second dielectric layer 44 is by the nitridation of such as silicon nitride
The formation such as oxide of object, silica, PSG, BSG, BPSG.Spin coating, lamination, CVD etc. or their group can be passed through
It closes and forms the second dielectric layer 44.Then the second dielectric layer 44 is patterned to form opening 46 to expose the first metallization of part figure
Case 40.It can be patterned by acceptable technique, it is such as when dielectric layer is light-sensitive material, the second dielectric layer 44 is sudden and violent
Dew is to light alternatively, for example, being etched by using anisotropic etching.
Fig. 5 to Figure 13 shows underbump metallization layer (UBM) 56 and the external electric on a corresponding UBM56
The formation of fitting 66.In Figure 5, above the second dielectric layer 44 and in opening 46, for example, in the side wall of the second dielectric layer 44
Above and on the first metallization pattern 40 form seed layer 48.In some embodiments, seed layer 48 is metal layer, can be
Single layer or the composite layer for including the multiple sublayers being formed from different materials.In some embodiments, which includes titanium
Layers of copper above layer and titanium layer.It is, for example, possible to use PVD etc. forms seed layer 48.
In figure 6, photoresist 50 is then formed on the seed layer.In this embodiment, photoresist 50 is negative photoresist
Material.Photoresist 50 can be formed on the seed layer by spin coating etc..
In the figure 7, photoresist 50 is patterned on seed layer 48.Photoresist 50 can be exposed to light and then develop with
For patterning.Due to the use of negative photoresist, after patterning, the part for being exposed to light of photoresist 50 still retains.
After being exposed to light, lithographic glue 50 is to remove the soluble fraction of photoresist 50, so that photoresist 50 is non-solvable
Part is retained on seed layer 48, and photoresist 50 has the opening 52 across photoresist 50.Opening 52 can have inclined side
Wall 54, for example, not with below photoresist 50 such as seed layer 48 and/or the vertical side of the major surfaces of the second dielectric layer 44
Wall.As described, inclined side wall 54 slopes inwardly on the direction far from following major surfaces towards opening.Sloped sidewall 54
With located immediately at opening 52 in below surface between corresponding angle, θ be less than 90 °, such as about 60 ° and about 85 ° it
Between.The pattern of photoresist corresponding with UBM56 or other metal patterns 50 will be formed.
In fig. 8, UBM56 and upper metal pattern are formed in the corresponding opening 52 of photoresist 50 and on seed layer 48
58.By plating (plating or chemical plating etc.) in the opening 52 of photoresist 50 and seed layer 48 expose portion
Upper formation conductive material.Conductive material may include metal, such as copper, titanium, tungsten, aluminium.UBM56 and upper metal pattern 58 can also
With sloped sidewall corresponding with the sloped sidewall 54 of photoresist 50.Therefore, by UBM56 and upper metal pattern 58 with it is following
The angle that major surfaces are formed can be less than 90 °, such as between about 60 ° and about 85 °.
Then, in fig.9, photoresist 50 is removed.(oxygen etc. can be used by acceptable ashing or stripping technology
Gas ions etc.) removal photoresist.In Fig. 10, the part that conductive material is not formed on seed layer 48 is removed.For example, by making
The expose portion of seed layer 48 is removed with such as wet or dry ecthing acceptable etch process.The remainder of seed layer 48 and
Conductive material forms UBM56 and upper metallization pattern 58.Their corresponding portion of UBM56 and seed layer 48 as shown is formed
In the opening 46 across the second dielectric layer 44 and on the first metallization pattern 40.Therefore, UBM56 can be electrically connected to
First metallization pattern 40.
In fig. 11, adhesive layer 60 is formed on the outer surface of UBM56 and upper metallization pattern 58.Adhesive layer 60 can be
Oxide.For example, when UBM56 and upper metallization pattern 58 include copper, adhesive layer 60 may include copper oxide.It can be by making
With acceptable processing, oxidation processes etc. form adhesive layer 60.In some embodiments, UBM 56 and upper metallization pattern
58 surface can be exposed to the plasma of oxygen carrier, for example, oxygen (O2) plasma, ozone (O3) plasma, inertia
The combination of gas and oxygen-containing gas, such as nitrogen (N2) and oxygen (O2) combination etc..Other processing can be used, and can be with
Form other adhesive layers.
In fig. 12, third dielectric layer 62 is formed on UBM56, upper metallization pattern 58 and the second dielectric layer 44.One
In a little embodiments, third dielectric layer 62 is formed by polyme, and can use mask by easily patterned
The light-sensitive material of PBO, polyimides, BCB etc..In other embodiments, third dielectric layer 62 is by such as silicon nitride
The formation such as oxide of nitride, silica, PSG, BSG, BPSG.Can by spin coating, lamination, CVD etc. or they
Combination form third dielectric layer 62.Then patterning third dielectric layer 62 with formed opening 64 with expose portion UBM56 and/or
Part adhesive layer 60 on UBM56.It can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material
When, third dielectric layer 62 is exposed to light alternatively, for example, being etched by using anisotropic etching.
In fig. 13, the part for the adhesive layer 60 that removal is exposed by opening 64, and pass through the shape on UBM56 of opening 64
At external electrical connections 66.In some embodiments, during ball mounting process, for example, forming external electric by melting
When fitting 66, the expose portion of adhesive layer 60 is removed.In some embodiments, external electrical connections 66, which may include use, to connect
The ball received falls the reflowable material of low temperature that technique is formed on UBM56, such as solder, such as lead-free solder.In some embodiments
In, external electrical connections 66 are ball grid array (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block etc..Other
In embodiment, external electrical connections 66 may include metal column.
In fig. 14, implement carrier substrates separation so that carrier substrates 20 are detached (unsticking) from package structure.According to one
A little embodiments, separation include by the light projection of such as laser or UV light on releasing layer 22, so that releasing layer 22 is in light
It is decomposed under heat and carrier substrates 20 can be removed.
Although not describing, then the structure can overturn and be placed on adhesive tape and divide.The common skill in this field
Art personnel will be understood that many such package structures can simultaneously form in carrier substrates 20, and therefore, such as scheme
The individual packaging part of description in 14 can such as be divided by sawing or cutting from other packaging parts.
Figure 15 shows another sectional view of package structure in accordance with some embodiments.In Figure 15 described embodiments
In, redistribution structure includes additional dielectric layer and metallization pattern.It, can be by above in order to form this package structure
The step of being discussed in conjunction with Fig. 1 to Fig. 3 carries out technique.It is then possible to the shape on the first dielectric layer 38 and the first metallization pattern 40
At the second dielectric layer 70.Second dielectric layer 70 can be and 38 same or similar material of the first dielectric layer and can be with above
It is formed in conjunction with the same or similar mode that the first dielectric layer 38 describes.Then such as with identical above in association with the first dielectric layer 38
Or similar mode patterns the second dielectric layer 70 to form opening to expose the first metallization pattern of part 40.Such as with
Same or similar material that the first metallization pattern of upper combination 40 and through-hole 42 describe and with above in association with the first metallization
The same or similar mode that pattern 40 and through-hole 42 describe is on the second dielectric layer 70 and across the second dielectric layer 70
The second metallization pattern 72 with through-hole 74 is formed in opening.First metallization pattern 40 is electrically connected to the second gold medal by through-hole 74
Categoryization pattern 72.The technique then can be according to the progress discussed above in association with Fig. 4 to Figure 14, wherein 44 He of the second dielectric layer
Third dielectric layer 62 corresponds respectively to the third dielectric layer 76 in Figure 15 and the 4th dielectric layer 78.
Figure 16 shows the further sectional view of package structure in accordance with some embodiments.It is real shown in figure 16
It applies in example, redistribution structure includes additional dielectric layer and metallization pattern.In order to form this package structure, technique can be with
The step of continuing to discuss above in association with Fig. 1 to Fig. 3.It is then possible in the first dielectric layer 38 and the first metallization pattern 40
The second dielectric layer 70 of upper formation.Second dielectric layer 70 can be with 38 same or similar material of the first dielectric layer, and can be with
By above in association with the first dielectric layer 38 describe it is same or similar in a manner of formed.Then such as with above in association with the first dielectric layer
38 same or similar modes pattern the second dielectric layer 70 to form opening to expose the first metallization pattern of part 40.It is all
As with above in association with described in the first metallization pattern 40 and through-hole 42 same or similar material and with above in association with first
The same or similar mode that metallization pattern 40 and through-hole 42 describe is on the second dielectric layer 70 and across the second dielectric
The second metallization pattern 72 with through-hole 74 is formed in the opening of layer 70.First metallization pattern 40 is electrically connected to by through-hole 74
Second metallization pattern 72.
It is then possible to form third dielectric layer 80 on the second dielectric layer 70 and the second metallization pattern 72.Third dielectric
Layer 80 can be with 38 same or similar material of the first dielectric layer, and can be to describe above in association with the first dielectric layer 38
Same or similar mode is formed.Then, patterning third dielectric layer 80 exposes the metallization of part second to form opening
Pattern 72, such as by above in association with the first dielectric layer 38 describe it is same or similar in a manner of.Such as with above in association with the first gold medal
Same or similar material that categoryization pattern 40 and through-hole 42 describe and with above in association with the first metallization pattern 40 and through-hole
The same or similar modes of 42 descriptions form on third dielectric layer 80 and in the opening across third dielectric layer 80 and have
The third metallization pattern 82 of through-hole 84.Second metallization pattern 72 is electrically connected to third metallization pattern 82 by through-hole 84.It can
With then to carry out the technique above in association with the discussion of Fig. 4 to Figure 14, wherein the second dielectric layer 44 and third dielectric layer 62 are distinguished
Corresponding to the 4th dielectric layer 86 and the 5th dielectric layer 88 in figure 16.
Figure 17 to Figure 21 shows the centre in accordance with some embodiments during being used to form the technique of package structure
The sectional view of step.Processing is according to the progress discussed above in association with Fig. 1 to Fig. 5.Then, in fig. 17, the shape on seed layer 48
At photoresist 90.In this embodiment, photoresist 90 can be positive-tone photo glue material or negative photo glue material.It can pass through
Spin coating etc. forms photoresist 90 on seed layer 48.Photoresist 90 is patterned on seed layer 48.Photoresist 90 can be exposed to
It light and is then developed to for patterning.After being exposed to light, lithographic glue 90 is to remove the solvable of photoresist 90
Part, so that the non-soluble fraction of photoresist 90 is maintained on seed layer 48, opening 92 passes through photoresist 90.Opening 92 can
With with inclined side wall or vertical side wall.The pattern of photoresist 90 corresponds to UBM 94, pseudo- pattern 96 or its by formation
His metallization pattern.
In figure 18, UBM 94, pseudo- pattern 96 are formed in the corresponding opening 92 of photoresist 90 and on seed layer 48
With upper metallization pattern 98.By plating, plating or chemical plating etc. in the opening 92 of photoresist 90 and in crystal seed
Conductive material is formed on the expose portion of layer 48.Conductive material may include metal, such as copper, titanium, tungsten, aluminium.UBM 94, pseudo- figure
Case 96 and upper metallization pattern 98 can also correspond to the side wall of the opening 92 of photoresist 90 with side wall.
Then, in fig. 19 a, photoresist 50 is removed；Remove the expose portion of seed layer 48；And pseudo- pattern 96, on
Third dielectric layer 100 is formed on metallization pattern 98 and the second dielectric layer 44.It can be by using oxygen plasma etc.
Acceptable ashing or stripping technology remove photoresist.Then, the part that conductive material is not formed on seed layer 48 is removed.Example
Such as, the expose portion of seed layer 48 is removed by using such as wet or dry ecthing acceptable etch process.Seed layer 48
Remainder and conductive material form UBM94, pseudo- pattern 96 and upper metallization pattern 98.UBM94 and seed layer 48 as shown
Their corresponding portion be formed in the opening 46 of the second dielectric layer 44 and on the first metallization pattern 40.
Therefore, UBM94 can be electrically connected to the first metallization pattern 40.Pseudo- pattern 96 can be electrically isolated and be not electrically connected to another gold
Categoryization or device.Upper metallization pattern 98 can be electrically connected to another metallization pattern and/or device.
Third dielectric layer 100 is formed on pseudo- pattern 96, upper metallization pattern 98 and the second dielectric layer 44.In some implementations
Example in, third dielectric layer 100 is formed by polyme, can be using mask by it is easily patterned such as
The light-sensitive material of PBO, polyimides, BCB etc..In other embodiments, third dielectric layer 100 is by the nitridation of such as silicon nitride
The formation such as oxide of object, silica, PSG, BSG, BPSG.Spin coating, lamination, CVD etc. or their group can be passed through
Conjunction forms third dielectric layer 100.Then for patterning third dielectric layer 100 to form opening 102, each opening 102 is sudden and violent by UBM94
Reveal to the part of adjacent pseudo- pattern 96.It can be patterned by acceptable technique, such as when dielectric layer is photosensitive material
When material, third dielectric layer 100 is exposed to light such as is etched by using anisotropic etching.
Figure 19 B show the opening 102 of UBM 94 in accordance with some embodiments, pseudo- pattern 96 and third dielectric layer 100
Exemplary layout.In layout, UBM 94 has octagonal shape, and pseudo- pattern 96 is with annular shape, such as exists
Octagonal ring around UBM 94.The layout of Figure 19 B shows the section A-A shown in fig. 19 a.Figure 19A and Figure 19B is shown
The size of separation D1 that UBM 94 is detached with pseudo- pattern 96.In addition, Figure 19A and Figure 19B shows that dimension D 2, dimension D 2 are pseudo-
The width of pattern 96.In some embodiments, size of separation D1 is greater than or equal to about 40 μm, and dimension D 2 can be from about 5 μ
In the range of m to about 10 μm.
Third dielectric layer 100 covers pseudo- pattern 96 at least partly, but does not cover UBM 94.In the illustrated embodiment,
Opening 102 has the side wall for pseudo- pattern 96 but not contacting or having a common boundary with the second dielectric layer 44.At opening 102, it is not present
The interface of second dielectric layer 44 and third dielectric layer 100.By opening 102, the part of pseudo- pattern 96, and pseudo- pattern are exposed
96 expose portion has dimension D 3.Dimension D 3 can be dimension D 2 about half or it is less.
In fig. 20, external electrical connections 104 are formed on the UBM94 of opening 102.In some embodiments, outside
Portion's electrical connector 104 may include falling such as solder (such as Pb-free coating that technique is formed on UBM94 using acceptable ball
Material) the reflowable material of low temperature.In some embodiments, external electrical connections 66 are BGA balls, C4 convex blocks, dimpling block etc..In volume
In outer embodiment, external electrical connections 104 may include metal column.
In figure 21, implement carrier substrates separation so that carrier substrates 20 are detached (unsticking) from package structure.According to one
A little embodiments, separation include by the light projection of such as laser or UV light on releasing layer 22, so that releasing layer 22 is in light
It is decomposed under heat and carrier substrates 20 can be removed.
Although not describing, then the structure can overturn and be placed on adhesive tape and divide.The common skill in this field
Art personnel will be understood that many such package structures can simultaneously form in carrier substrates 20, and therefore, such as scheme
The individual packaging part of description in 21 can such as be divided by sawing or cutting from other packaging parts.
Figure 22 shows another sectional view of package structure in accordance with some embodiments.It is described in fig. 22 to implement
In example, redistribution structure includes additional dielectric layer and metallization pattern.In order to form this package structure, can by with
The step of upper combination Fig. 1 to Fig. 3 is discussed carries out technique.It is then possible on the first dielectric layer 38 and the first metallization pattern 40
Form the second dielectric layer 70.Second dielectric layer 70 can be with 38 same or similar material of the first dielectric layer and can with
The same or similar mode that the first dielectric layer of upper combination 38 describes is formed.Then such as with above in association with 38 phase of the first dielectric layer
Same or similar mode patterns the second dielectric layer 70 to form opening to expose the first metallization pattern of part 40.Such as with
The same or similar material that is described above in association with the first metallization pattern 40 and through-hole 42 and with above in association with the first metal
Change the same or similar mode of pattern 40 and the description of through-hole 42 on the second dielectric layer 70 and across the second dielectric layer 70
Opening in formed with through-hole 74 the second metallization pattern 72.First metallization pattern 40 is electrically connected to second by through-hole 74
Metallization pattern 72.The technique then can be according to the progress discussed above in association with Fig. 4, Fig. 5 and Figure 17 to Figure 21, wherein the
Two dielectric layers 44 and third dielectric layer 100 correspond respectively to the third dielectric layer 76 in Figure 22 and the 4th dielectric layer 106.
Figure 23 shows the further sectional view of package structure in accordance with some embodiments.It is real shown in fig 23
It applies in example, redistribution structure includes additional dielectric layer and metallization pattern.In order to form this package structure, technique can be with
The step of continuing to discuss above in association with Fig. 1 to Fig. 3.It is then possible in the first dielectric layer 38 and the first metallization pattern 40
The second dielectric layer 70 of upper formation.Second dielectric layer 70 can be with 38 same or similar material of the first dielectric layer, and can be with
By above in association with the first dielectric layer 38 describe it is same or similar in a manner of formed.Then such as with above in association with the first dielectric layer
38 same or similar modes pattern the second dielectric layer 70 to form opening to expose the first metallization pattern of part 40.It is all
As with above in association with described in the first metallization pattern 40 and through-hole 42 same or similar material and with above in association with first
The same or similar mode that metallization pattern 40 and through-hole 42 describe is on the second dielectric layer 70 and across the second dielectric
The second metallization pattern 72 with through-hole 74 is formed in the opening of layer 70.First metallization pattern 40 is electrically connected to by through-hole 74
Second metallization pattern 72.
It is then possible to form third dielectric layer 80 on the second dielectric layer 70 and the second metallization pattern 72.Third dielectric
Layer 80 can be with 38 same or similar material of the first dielectric layer and can with above in association with the first dielectric layer 38 describe
Same or analogous mode is formed.Then, patterning third dielectric layer 80 exposes the metallization of part second to form opening
Pattern 72, such as by above in association with the first dielectric layer 38 describe it is same or similar in a manner of.Such as with above in association with the first gold medal
Same or similar material that categoryization pattern 40 and through-hole 42 describe and with above in association with the first metallization pattern 40 and through-hole
The same or similar modes of 42 descriptions form on third dielectric layer 80 and in the opening across third dielectric layer 80 and have
The third metallization pattern 82 of through-hole 84.Second metallization pattern 72 is electrically connected to third metallization pattern 82 by through-hole 84.It should
Then technique can carry out the technique discussed above in association with Fig. 4, Fig. 5 and Figure 17 to Figure 21, wherein the second dielectric layer 44 and third
Dielectric layer 100 corresponds respectively to the 4th dielectric layer 86 and the 5th dielectric layer 108 in fig 23.
Figure 24 to Figure 28 shows the centre in accordance with some embodiments during being used to form the technique of package structure
The sectional view of step.Processing is according to the progress discussed above in association with Fig. 1 to Fig. 5.Then, in fig. 24, the shape on seed layer 48
At photoresist 120.In this embodiment, photoresist 120 can be positive-tone photo glue material or negative photo glue material.It can lead to
It crosses spin coating etc. and forms photoresist 120 on seed layer 48.Photoresist 120 is patterned on seed layer 48.Photoresist 120 can be sudden and violent
Dew is to light and is then developed to for patterning.After being exposed to light, lithographic glue 120 is to remove photoresist 120
Soluble fraction so that the non-soluble fraction of photoresist 120 is maintained on seed layer 48, opening 122 passes through photoresist
120.Opening 122 can have inclined side wall or vertical side wall.The pattern of photoresist 120 corresponds to UBM 124 or by shape
At upper metallization pattern 126.
In fig. 25, UBM 94 and upper metal are formed in the corresponding opening 122 of photoresist 120 and on seed layer 48
Change pattern 126.Such as by plating, plating or chemical plating etc. are in the opening 122 of photoresist 120 and in seed layer 48
Conductive material is formed on expose portion.Conductive material may include metal, such as copper, titanium, tungsten, aluminium.UBM 124 and upper metallization
Pattern 126 can also have the side wall of the opening 122 corresponding to photoresist 120.
Then, in Figure 26 A, photoresist 120 is removed；Remove the expose portion of seed layer 48；And scheme in upper metallization
Third dielectric layer 128 is formed on case 126, the second dielectric layer 44 and part UBM124.It can be by such as using oxygen plasma
Deng acceptable ashing or stripping technology remove photoresist.Then, the portion that conductive material is not formed on seed layer 48 is removed
Point.For example, removing the expose portion of seed layer 48 by using such as wet or dry ecthing acceptable etch process.Seed layer
48 remainder and conductive material forms UBM124 and upper metallization pattern 126.UBM124's and seed layer 48 as shown
Their corresponding portion is formed in the opening 46 of the second dielectric layer 44 and on the first metallization pattern 40.Cause
This, UBM124 can be electrically connected to the first metallization pattern 40.
Third dielectric layer 128 is formed on upper metallization pattern 126 and the second dielectric layer 44 and part UBM124.One
In a little embodiments, third dielectric layer 128 is formed by polyme, and can use mask by easily patterned
The light-sensitive material of PBO, polyimides, BCB etc..In other embodiments, third dielectric layer 128 is by such as silicon nitride
The formation such as oxide of nitride, silica, PSG, BSG, BPSG.Can by spin coating, lamination, CVD etc. or they
Combination form third dielectric layer 128.Then patterning third dielectric layer 128 is to form opening 130,130 exposure of each opening
Go out part UBM124.It can be patterned by acceptable technique, such as when dielectric layer is light-sensitive material, third is situated between
Electric layer 128 is exposed to light such as is etched by using anisotropic etching.
Figure 26 B show the more detailed section of the UBM 124 in Figure 26 A and the opening 130 across third dielectric layer 128
Figure, and Figure 26 C show the layout of UBM 124 and the opening 130 across third dielectric layer 128.Figure 26 C, which are shown, to scheme
Section A-A shown in 26A and Figure 26 B.Figure 26 B and Figure 26 C show the first planar section 124a, the side of sidewall portion of UBM 124
Divide 124b and the second planar section 124c.The first planar section 124a plane earths of UBM 124 extend in third dielectric layer 128
On top surface.The sidewall sections 124b of UBM 124 extends along the side wall of the opening 46 of the second dielectric layer 44.The second of UBM 124
Planar section 124c be positioned at the second dielectric layer 44 opening 46 in and along the top surface plane of the first metallization pattern 40
Extend.Across the opening 130 of third dielectric layer 128, the second planar section 124c of part is exposed.Third dielectric layer 128 covers
First planar section 124a and sidewall sections 124b.Third dielectric layer 128 is from sidewall sections 124b and the second planar section 124c
Between binding site extension size D4.In some embodiments, dimension D 4 is greater than or equal to about 10 μm.
In figure 27, external electrical connections 132 are formed on the UBM124 of opening 130.In some embodiments, outside
Portion's electrical connector 132 may include falling such as solder (such as Pb-free coating that technique is formed on UBM124 using acceptable ball
Material) the reflowable material of low temperature.In some embodiments, external electrical connections 132 are BGA balls, C4 convex blocks, dimpling block etc..
In additional embodiment, external electrical connections 132 may include metal column.
In Figure 28, implement carrier substrates separation so that carrier substrates 20 are detached (unsticking) from package structure.According to one
A little embodiments, separation include by the light projection of such as laser or UV light on releasing layer 22, so that releasing layer 22 is in light
It is decomposed under heat and carrier substrates 20 can be removed.
Although not describing, then the structure can overturn and be placed on adhesive tape and divide.The common skill in this field
Art personnel will be understood that many such package structures can simultaneously form in carrier substrates 20, and therefore, such as scheme
The individual packaging part of description in 28 can such as be divided by sawing or cutting from other packaging parts.
Figure 29 shows another sectional view of package structure in accordance with some embodiments.Implementation described in Figure 29
In example, redistribution structure includes additional dielectric layer and metallization pattern.In order to form this package structure, can by with
The step of upper combination Fig. 1 to Fig. 3 is discussed carries out technique.It is then possible on the first dielectric layer 38 and the first metallization pattern 40
Form the second dielectric layer 70.Second dielectric layer 70 can be with 38 same or similar material of the first dielectric layer and can with
The same or similar mode that the first dielectric layer of upper combination 38 describes is formed.Then such as with above in association with 38 phase of the first dielectric layer
Same or similar mode patterns the second dielectric layer 70 to form opening to expose the first metallization pattern of part 40.Such as with
The same or similar material that is described above in association with the first metallization pattern 40 and through-hole 42 and with above in association with the first metal
Change the same or similar mode of pattern 40 and the description of through-hole 42 on the second dielectric layer 70 and across the second dielectric layer 70
Opening in formed with through-hole 74 the second metallization pattern 72.First metallization pattern 40 is electrically connected to second by through-hole 74
Metallization pattern 72.The technique then can be according to the progress discussed above in association with Fig. 4, Fig. 5 and Figure 24 to Figure 28, wherein the
Two dielectric layers 44 and third dielectric layer 128 correspond respectively to the third dielectric layer 76 in Figure 29 and the 4th dielectric layer 134.
Figure 30 shows the further sectional view of package structure in accordance with some embodiments.Shown in fig. 30
In embodiment, redistribution structure includes additional dielectric layer and metallization pattern.In order to form this package structure, technique can
With the step of continuing to discuss above in association with Fig. 1 to Fig. 3.It is then possible in the first dielectric layer 38 and the first metallization pattern
The second dielectric layer 70 is formed on 40.Second dielectric layer 70 can be with 38 same or similar material of the first dielectric layer, and can
By by above in association with the first dielectric layer 38 describe it is same or similar in a manner of formed.Then such as with above in association with the first dielectric
38 same or similar mode of layer pattern the second dielectric layer 70 to form opening to expose the first metallization pattern of part 40.
Such as with above in association with the first metallization pattern 40 and the description of through-hole 42 same or similar material and with above in association with the
The same or similar mode that one metallization pattern 40 and through-hole 42 describe is situated between on the second dielectric layer 70 and across second
The second metallization pattern 72 with through-hole 74 is formed in the opening of electric layer 70.First metallization pattern 40 is electrically connected by through-hole 74
To the second metallization pattern 72.
It is then possible to form third dielectric layer 80 on the second dielectric layer 70 and the second metallization pattern 72.Third dielectric
Layer 80 can be with 38 same or similar material of the first dielectric layer and can with above in association with the first dielectric layer 38 describe
Same or analogous mode is formed.Then, patterning third dielectric layer 80 exposes the metallization of part second to form opening
Pattern 72, such as by above in association with the first dielectric layer 38 describe it is same or similar in a manner of.Such as with above in association with the first gold medal
Same or similar material that categoryization pattern 40 and through-hole 42 describe and with above in association with the first metallization pattern 40 and through-hole
The same or similar modes of 42 descriptions form on third dielectric layer 80 and in the opening across third dielectric layer 80 and have
The third metallization pattern 82 of through-hole 84.Second metallization pattern 72 is electrically connected to third metallization pattern 82 by through-hole 84.It should
Then technique can carry out the technique discussed above in association with Fig. 4, Fig. 5 and Figure 24 to Figure 28, wherein the second dielectric layer 44 and third
Dielectric layer 128 corresponds respectively to the 4th dielectric layer 86 and the 5th dielectric layer 136 in fig. 30.
Advantage may be implemented in embodiment.By forming adhesive layer 60, third dielectric on UBM56 and upper metallization pattern 58
Layer 62 can have to the adherency of the enhancing of UBM 56 and upper metallization pattern 58, can reduce third dielectric layer 62 in turn
Layering.Further, by the sloped sidewall of sloped sidewall and upper metallization pattern 58 with UBM56, third dielectric layer 62 can
It can be obtained with more surface areas of adherency, layering can be reduced.Equally, the sloped sidewall of UBM 56 can be reduced
The protuberance of third dielectric layer 62 on UBM 56 or other accumulations, such as when third dielectric layer 62 is PBO or another polymeric layers
When.This can improve the uniformity of third dielectric layer 62, can improve the reliability of packaging part.
In addition, by with upper dielectric layer, such as in a manner of some discussed above in 100 He of third dielectric layer that configures
128, it is possible to reduce permeate caused layering by melting.For example, do not contact UBM by making upper dielectric layer, institute in such as Figure 21
Show, the melting on the UBM that ball falls technique or convex block lands technique may not contact between upper dielectric layer and another component
Interface.If melting does not contact such interface, can be layered to avoid caused by melting infiltration interface.Equally, pass through tool
There is the upper dielectric layer of the large area of covering UBM, all as shown in Figure 28, melting may have to further permeate dielectric
Interface between layer and UBM is to cause any significant layering of upper dielectric layer.Further seepage distance, which can reduce, to be caused
The possibility for the infiltration being significantly layered.
Although discussing each embodiment respectively, one ordinarily skilled in the art will readily appreciate that some realities
Other embodiment can be applied to by applying the aspect of example.For example, adhesive layer 60 can be applied in the embodiment of Figure 21 and Figure 28
Upper metallization pattern and/or UBM.In addition, upper metallization pattern and/or UBM in the embodiment being shown in FIG. 16 inclines
Oblique side wall can be applied in the embodiment of Figure 21 and Figure 28.
First embodiment is a kind of package structure.Package structure includes：Integrated circuit die；At least laterally seal
The sealant of integrated circuit die；Redistribution structure on integrated circuit die and sealant；It is connected to redistribution structure
Support metal layer connector and positioned at support metal layer connector on joint outer part.Redistribution structure includes
First dielectric layer, the first dielectric layer are arranged far from sealant and integrated circuit die.The connector of metal layer is supported to have the
A part and second part, first part is located on the first surface of the first dielectric layer and second part is across the first dielectric
Extend in the opening of layer.The first part of the connector of metal layer is supported to have in the first surface far from the first dielectric layer
The sloped sidewall just upwardly extended.
Another embodiment is a kind of package structure.Package structure includes：Composite construction is located on composite construction
Redistribution structure and the underbump metallization layer (UBM) on redistribution structure.Composite construction includes integrated circuit die
At least laterally seal the sealing material of integrated circuit die.The first surface of redistribution structure is far from composite construction.UBM has
There is the first part on first surface.The side wall of first part forms non-perpendicular angles with first surface, and inside UBM
Measure non-perpendicular angles.Adhesive layer is located in the first part of UBM.First dielectric layer is located on redistribution structure and adjacent bonding
Layer.External electrical connections are arranged through the first dielectric layer and on UBM.
Further embodiment is a kind of method.This method includes：Integrated circuit die is sealed with sealant and integrated
Redistribution structure is formed on circuit die and sealant.Redistribution structure includes metallization pattern and on metallization pattern
First dielectric layer.First dielectric layer has the first surface far from integrated circuit die and sealant.This method further includes in weight
Underbump metallization layer (UBM) is formed on distributed architecture.UBM has the first part being located on first surface and is provided through
To the second part of metallization pattern in the opening of first dielectric layer.The first part of UBM has first with the first dielectric layer
The sidewall surfaces of surface out of plumb.This method further includes on the first surface of the first dielectric layer and in the first part of UBM
It forms the second dielectric layer and forms the external electrical connections across opening to UBM, be open across the second dielectric layer.
Another embodiment is a kind of package structure.The package structure includes integrated circuit die；At least laterally
Seal the sealant of integrated circuit die；Redistribution structure on integrated circuit die and sealant, is connected to redistribution
The connector of the support metal layer of structure, pseudo- pattern, the second dielectric layer, and it is outer on the connector of support metal layer
Portion's connector.Redistribution structure includes the first dielectric layer, and the first dielectric layer has to be arranged far from sealant and integrated circuit die
First surface.Support the connector of metal layer that there is first part and second part, first part to be located at the first dielectric layer
First surface on and second part extend in the opening across the first dielectric layer.Pseudo- pattern is located at the of the first dielectric layer
On one surface and around the connector of support metal layer.Second dielectric layer is located on the first surface of the first dielectric layer and pseudo- figure
Case is at least partially.Second dielectric layer does not contact the connector of support metal layer.
Further embodiment is a kind of package structure.The package structure includes integrated circuit die；At least laterally
Ground seals the sealant of integrated circuit die；Redistribution structure on integrated circuit die and sealant, is connected to and divides again
Cloth structure support metal layer connector, the second dielectric layer, and positioned at support metal layer connector on outside connect
Fitting.Redistribution structure includes the first dielectric layer, and the first dielectric layer is arranged far from sealant and integrated circuit die.Support metal
There is the connector for changing layer first part, second part and Part III, first part to be located at the first surface of the first dielectric layer
On, second part extends along the bottom surface of the first opening across the first dielectric layer, and Part III is along the first opening
Side wall extends and between first part and second part.Junction is formed in the position of second part contact Part III
Place.Second dielectric layer is located on the first surface of the first dielectric layer and the first part of the connector of support metal layer, third
Part and second part are at least partially.Joint outer part passes through the second opening, and the second opening is across the second dielectric layer.
Another embodiment is a kind of method.This method includes：Integrated circuit die is sealed with sealant；In integrated circuit
Redistribution structure is formed on tube core and sealant, redistribution structure includes the first dielectric layer, and the first dielectric layer has far from integrated
The first surface of circuit die and sealant；Underbump metallization layer (UBM) and pseudo- pattern, puppet figure are formed on redistribution structure
UBM of the case on the first surface of the first dielectric layer；On the first surface of the first dielectric layer and in at least portion of pseudo- pattern
Divide upper formation the second dielectric layer, wherein after forming the second dielectric layer, the second dielectric layer does not contact UBM；And on UBM
Form external electrical connections.
Foregoing has outlined the features of several embodiments so that the side of the present invention may be better understood in those skilled in the art
Face.It should be appreciated by those skilled in the art that they can be easily using designing or modifying based on the present invention for real
Now with other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.People in the art
Member it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from the present invention essence
In the case of refreshing and range, they can make a variety of variations, replace and change herein.
In order to solve the problems in the prior art, according to some embodiments of the present invention, a kind of package structure is provided,
Including：Integrated circuit die；Sealant at least laterally seals the integrated circuit die；Redistribution structure is located at the collection
At in circuit die and the sealant, the redistribution structure includes the first dielectric layer, and first dielectric layer has separate
The first surface of the sealant and integrated circuit die setting；Support the connector of metal layer, the metal layer
It is connected to the redistribution structure, the connector of the support metal layer has first part and a second part, and described first
Part is located on the first surface of first dielectric layer and the second part is across first dielectric layer
Extend in opening；Pseudo- pattern is located on the first surface of first dielectric layer and is located at the support metal layer
Connector around；Second dielectric layer is located on the first surface of first dielectric layer and positioned at the pseudo- pattern
At least partially, second dielectric layer does not contact the connector of the support metal layer；And joint outer part, it is located at
On the connector of the support metal layer.
Further include the adhesive layer at least partially for being located at the pseudo- pattern in above-mentioned packaging part.
In above-mentioned packaging part, wherein the puppet pattern surrounds and limit the first surface of first dielectric layer
Region, in the region of the connector first surface that is located at first dielectric layer of the support metal layer,
Second dielectric layer does not contact the region of the first surface of first dielectric layer.
In above-mentioned packaging part, wherein the first surface of the width and first dielectric layer of the puppet pattern is flat
Row, second dielectric layer are located at the width of the pseudo- pattern for the connector for being laterally away from the support metal layer
At least half on.
In above-mentioned packaging part, wherein the first surface of the width and first dielectric layer of the puppet pattern is flat
Row, second dielectric layer are located at the width of the pseudo- pattern for the connector for being laterally away from the support metal layer
Half on, second dielectric layer is not located at the pseudo- pattern for the connector for being laterally adjacent the support metal layer
In the half of the width.
In above-mentioned packaging part, wherein the first surface of the width and first dielectric layer of the puppet pattern is flat
Row, the width are in the range of from 5 μm to 10 μm.
In above-mentioned packaging part, wherein the puppet pattern supports the connector of metal layer laterally and physics with described
Ground detaches.
In above-mentioned packaging part, wherein the puppet pattern supports the connector of metal layer laterally and physics with described
Ground detaches；Wherein, the connector of the pseudo- pattern and the support metal layer laterally and is physically separated at least 40 μm.
Other embodiments according to the present invention provide a kind of package structure, including：Integrated circuit die；Sealing
Agent at least laterally seals the integrated circuit die；Redistribution structure is located at the integrated circuit die and the sealant
On, the redistribution structure includes the first dielectric layer, and first dielectric layer is far from the sealant and the integrated circuit pipe
Core is arranged；The connector of metal layer, the metal layer is supported to be connected to the redistribution structure, the support metal layer
Connector there is first part, second part and Part III, the first part is located at the first of first dielectric layer
On surface, the second part extends along the bottom surface of the first opening across first dielectric layer, and the third portion
Divide the side wall extension along first opening and between the first part and the second part, junction is formed in
The second part contacts at the position of the Part III；Second dielectric layer is located at described the first of first dielectric layer
On surface extremely with the first part, the Part III and the second part of the connector of the support metal layer
In a few part；And joint outer part, pass through second to be open and be located on the connector of the support metal layer, it is described
Second opening is across second dielectric layer.
In above-mentioned packaging part, wherein second dielectric layer is located at the described of the connector of the support metal layer
The center of the first part in first part from the junction towards the connector of the support metal layer extends to
Few 10 μm of distance.
In above-mentioned packaging part, further include：Adhesive layer is located at least described the of the connector of the support metal layer
In a part.
In above-mentioned packaging part, wherein the redistribution structure includes metallization pattern, and the metallization pattern limits institute
State at least part of the bottom surface of the first opening.
In above-mentioned packaging part, wherein the second part contact of the connector of the support metal layer is described heavy
The metallization pattern of distributed architecture.
In above-mentioned packaging part, wherein the joint outer part includes solder.
Other embodiment according to the present invention, provides a method, including：Integrated circuit pipe is sealed with sealant
Core；Redistribution structure is formed on the integrated circuit die and the sealant, the redistribution structure includes the first dielectric
Layer, first dielectric layer have the first surface being arranged far from the integrated circuit die and the sealant；Described heavy
Underbump metallization layer (UBM) and pseudo- pattern are formed on distributed architecture, the puppet pattern is around the described of first dielectric layer
The UBM on first surface；On the first surface of first dielectric layer and at least one of the pseudo- pattern
Divide upper formation the second dielectric layer, wherein after forming second dielectric layer, second dielectric layer does not contact the UBM；
And form external electrical connections on the UBM.
In the above-mentioned methods, further include：Adhesive layer is formed on at least described part of the pseudo- pattern.
In the above-mentioned methods, wherein the width of the puppet pattern is parallel with the first surface of the first dielectric layer,
Second dielectric layer is located in at least half of the width for the pseudo- pattern for being laterally away from the UBM.
In the above-mentioned methods, wherein the width of the puppet pattern is parallel with the first surface of the first dielectric layer,
Second dielectric layer is located in the half of the width for the pseudo- pattern for being laterally away from the UBM, and described second is situated between
Electric layer is not located in the half of the width for the pseudo- pattern for being laterally adjacent the UBM.
In the above-mentioned methods, wherein the puppet pattern is physically separated with the UBM.
In the above-mentioned methods, wherein the UBM contacts the metallization pattern of the redistribution structure.
Claims (19)
1. a kind of package structure, including：
Integrated circuit die；
Sealant at least laterally seals the integrated circuit die；
Redistribution structure is located on the integrated circuit die and the sealant, and the redistribution structure includes the first dielectric
Layer, first dielectric layer have the first surface being arranged far from the sealant and the integrated circuit die；
Connector supports metal layer, the connector support metal layer to be connected to the redistribution structure, the connector
Support metal layer that there is first part and second part, the first part to be located at first table of first dielectric layer
On face and the second part extends in the opening across first dielectric layer；
Pseudo- pattern was located on the first surface of first dielectric layer and positioned at connector support metal layer week
It encloses；
Second dielectric layer is located on the first surface of first dielectric layer and is located at the pseudo- pattern at least partly
On, second dielectric layer does not contact the connector support metal layer；And
Joint outer part is located on connector support metal layer.
2. package structure according to claim 1 further includes the adhesive layer at least partially for being located at the pseudo- pattern.
3. package structure according to claim 1, wherein the puppet pattern surrounds and limit first dielectric layer
The region of the first surface, the connector support metal layer are located at the institute of the first surface of first dielectric layer
It states in region, second dielectric layer does not contact the region of the first surface of first dielectric layer.
4. package structure according to claim 1, wherein the institute of the width and first dielectric layer of the puppet pattern
State that first surface is parallel, second dielectric layer is located at the pseudo- pattern for being laterally away from the connector support metal layer
The width at least half on.
5. package structure according to claim 1, wherein the institute of the width and first dielectric layer of the puppet pattern
State that first surface is parallel, second dielectric layer is located at the pseudo- pattern for being laterally away from the connector support metal layer
The width half on, second dielectric layer, which is not located at, is laterally adjacent the described of connector support metal layer
In the half of the width of pseudo- pattern.
6. package structure according to claim 1, wherein the institute of the width and first dielectric layer of the puppet pattern
It is parallel to state first surface, the width is in the range of from 5 μm to 10 μm.
7. package structure according to claim 1, wherein the puppet pattern and connector support metal layer are horizontal
To ground and it is physically separated.
8. package structure according to claim 7, wherein the puppet pattern and connector support metal layer are horizontal
To ground and it is physically separated at least 40 μm.
9. a kind of package structure, including：
Integrated circuit die；
Sealant at least laterally seals the integrated circuit die；
Redistribution structure is located on the integrated circuit die and the sealant, and the redistribution structure includes the first dielectric
Layer, first dielectric layer are arranged far from the sealant and the integrated circuit die；
Connector supports metal layer, the connector support metal layer to be connected to the redistribution structure, the connector
Support metal layer that there is first part, second part and Part III, the first part to be located at first dielectric layer
On first surface, the second part extends along the bottom surface of the first opening across first dielectric layer, and described the
Three parts extend along the side wall of first opening and between the first part and the second part, engage dot
At at the position that the second part contacts the Part III；
Second dielectric layer, is located on the first surface of first dielectric layer and the connector supports the institute of metal layer
In at least part for stating first part, the Part III and the second part, wherein second dielectric layer is located at
Metal layer is supported from the junction towards the connector in the first part of the connector support metal layer
The center of the first part extend at least 10 μm of distance；And
Joint outer part, pass through second be open and positioned at the connector support metal layer on, it is described second opening across
Second dielectric layer.
10. package structure according to claim 9, further includes：Adhesive layer is located at the connector and supports metal layer
At least described first part on.
11. package structure according to claim 9, wherein the redistribution structure includes metallization pattern, the gold
Categoryization pattern limits at least part of the bottom surface of first opening.
12. package structure according to claim 9, wherein described second of the connector support metal layer
Tap touches the metallization pattern of the redistribution structure.
13. package structure according to claim 9, wherein the joint outer part includes solder.
14. a kind of method forming package structure, including：
Integrated circuit die is sealed with sealant；
Redistribution structure is formed on the integrated circuit die and the sealant, the redistribution structure includes the first dielectric
Layer, first dielectric layer have the first surface being arranged far from the integrated circuit die and the sealant；
Underbump metallization layer (UBM) and pseudo- pattern are formed on the redistribution structure, the puppet pattern surrounds described first
The underbump metallization layer on the first surface of dielectric layer；
The second dielectric is formed on the first surface of first dielectric layer and at least part of the pseudo- pattern
Layer, wherein after forming second dielectric layer, second dielectric layer does not contact the underbump metallization layer；And
External electrical connections are formed in the underbump metallization layer.
15. according to the method for claim 14, further including：Bonding is formed on at least described part of the pseudo- pattern
Layer.
16. according to the method for claim 14, wherein described the of width and first dielectric layer of the puppet pattern
One surface is parallel, and second dielectric layer is located at the width for the pseudo- pattern for being laterally away from the underbump metallization layer
In at least half of degree.
17. according to the method for claim 14, wherein described the of width and first dielectric layer of the puppet pattern
One surface is parallel, and second dielectric layer is located at the width for the pseudo- pattern for being laterally away from the underbump metallization layer
In the half of degree, second dielectric layer is not located at the described of the pseudo- pattern for being laterally adjacent the underbump metallization layer
In the half of width.
18. according to the method for claim 14, wherein the puppet pattern physically divides with the underbump metallization layer
From.
19. according to the method for claim 14, wherein the underbump metallization layer contacts the gold of the redistribution structure
Categoryization pattern.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/671,477 US10147692B2 (en) | 2014-09-15 | 2015-03-27 | Package with UBM and methods of forming |
| US14/671,477 | 2015-03-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106024727A CN106024727A (en) | 2016-10-12 |
| CN106024727B true CN106024727B (en) | 2018-10-26 |
Family
ID=57082522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510667052.9A Active CN106024727B (en) | 2015-03-27 | 2015-10-15 | Packaging part and forming method thereof with UBM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106024727B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102601553B1 (en) * | 2016-12-08 | 2023-11-15 | 삼성전자주식회사 | Semiconductor light emitting device |
| US10340198B2 (en) * | 2017-02-13 | 2019-07-02 | Mediatek Inc. | Semiconductor package with embedded supporter and method for fabricating the same |
| US10354964B2 (en) * | 2017-02-24 | 2019-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated devices in semiconductor packages and methods of forming same |
| US10297561B1 (en) * | 2017-12-22 | 2019-05-21 | Micron Technology, Inc. | Interconnect structures for preventing solder bridging, and associated systems and methods |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428329A (en) * | 2014-09-15 | 2016-03-23 | 台湾积体电路制造股份有限公司 | Package with UBM and Methods of Forming |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7858441B2 (en) * | 2008-12-08 | 2010-12-28 | Stats Chippac, Ltd. | Semiconductor package with semiconductor core structure and method of forming same |
| JP5582811B2 (en) * | 2010-02-15 | 2014-09-03 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| US9117682B2 (en) * | 2011-10-11 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of packaging semiconductor devices and structures thereof |
-
2015
- 2015-10-15 CN CN201510667052.9A patent/CN106024727B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428329A (en) * | 2014-09-15 | 2016-03-23 | 台湾积体电路制造股份有限公司 | Package with UBM and Methods of Forming |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106024727A (en) | 2016-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11069656B2 (en) | Three-layer package-on-package structure and method forming same | |
| US10833030B2 (en) | Semiconductor device and method of manufacture | |
| US10090284B2 (en) | Semiconductor device and method of manufacture | |
| CN105428329B (en) | Packaging part and forming method with UBM | |
| CN107026092B (en) | Method of manufacturing fingerprint scanner and semiconductor device | |
| KR101731683B1 (en) | Methods of packaging semiconductor devices and packaged semiconductor devices | |
| TWI593082B (en) | Semiconductor device and method of manufactures | |
| KR101746269B1 (en) | Semiconductor device and manufacturing method thereof | |
| US8810006B2 (en) | Interposer system and method | |
| KR101823225B1 (en) | Package structures and method of forming the same | |
| CN106997855A (en) | Ic package and forming method thereof | |
| TWI529892B (en) | Chip package and method for forming the same | |
| CN105789062A (en) | Package Structure And Method Of Forming The Same | |
| CN106024727B (en) | Packaging part and forming method thereof with UBM | |
| CN106409816A (en) | Integrated circuit dies having alignment marks and methods of forming same | |
| US11430776B2 (en) | Semiconductor devices and methods of manufacturing | |
| CN112542449A (en) | Semiconductor device and method for manufacturing the same | |
| TWI821476B (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |