CN106024641B - Thin film transistor, array substrate, manufacturing method of array substrate and display device - Google Patents
Thin film transistor, array substrate, manufacturing method of array substrate and display device Download PDFInfo
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- CN106024641B CN106024641B CN201610617050.3A CN201610617050A CN106024641B CN 106024641 B CN106024641 B CN 106024641B CN 201610617050 A CN201610617050 A CN 201610617050A CN 106024641 B CN106024641 B CN 106024641B
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- 239000010409 thin film Substances 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000010408 film Substances 0.000 claims abstract description 184
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 126
- 238000005530 etching Methods 0.000 claims abstract description 112
- 239000002184 metal Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000007788 liquid Substances 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims abstract description 14
- 230000014759 maintenance of location Effects 0.000 claims description 36
- 238000011282 treatment Methods 0.000 claims description 6
- 238000005984 hydrogenation reaction Methods 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000002923 metal particle Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 148
- 238000010586 diagram Methods 0.000 description 9
- 150000002739 metals Chemical class 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Abstract
The invention relates to a thin film transistor, an array substrate, a manufacturing method of the thin film transistor and the array substrate, and a display device, and aims to solve the problems that in a TFT manufacturing process, etching offset between photoresist and source and drain metal is small, and metal particles falling from the source and drain metal easily pollute a channel when the channel is etched. The method comprises the following steps: sequentially forming an active layer, an additional film layer and a pattern of a source electrode and a drain electrode on a substrate; the patterns of the additional film layer are respectively arranged at two ends of the active layer and can be completely covered by the patterns of the source and the drain; the additional film layer and the source and drain electrodes can be etched by adopting different etching liquids. Because the additional film layer is added between the active layer and the source and drain electrodes, the etching rate of the source and drain electrode metal can be accelerated by increasing the contact area of the etching liquid and the source and drain electrode metal, so that the etching offset between the photoresist and the source and drain electrode metal can be increased on the premise of slightly increasing the etching time, and the pollution of metal particles to a channel when the channel is etched by adopting a dry etching method is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, an array substrate, manufacturing methods of the thin film transistor and the array substrate and a display device.
Background
At present, in the existing TFT (Thin Film Transistor) manufacturing process, the etching offset between the photoresist and the source and drain metal is small, when etching the TFT channel N + by using a dry etching method, it may be caused that metal particles of the source and drain metal are easy to pollute the TFT channel due to the poor anisotropic property of the dry etching process, thereby affecting the TFT characteristics, thereby causing the defects of mura (i.e. uneven brightness of the display, and various traces), and the like, and there are certain problems in the existing two solutions:
the first scheme is as follows: the length of a channel is reduced, PR glue is easily formed at the position of the channel for adhesion, the channel cannot be normally formed, the condition that the length of the channel is too short, even a source electrode and a drain electrode are short-circuited is easily caused, and the function of a TFT device cannot be realized;
scheme II: the source and drain electrodes are reduced by increasing the etching time, the process easily causes the problems of source and drain electrode metal open circuit and process time increase, and because the line width at each position is reduced to the same extent when the source and drain electrode etching time is increased, the open circuit problem is easily caused at the positions where the source and drain electrode metal routing is narrow.
In summary, in the existing TFT manufacturing process, the etching offset between the photoresist and the source and drain metals is small, and when N + at the TFT channel is etched, metal particles falling from the source and drain metals easily contaminate the channel, affecting the TFT characteristics, and thus causing defects such as mura.
Disclosure of Invention
In view of this, the thin film transistor, the array substrate, the manufacturing method thereof and the display device provided by the embodiments of the present invention are used to solve the problems that in the existing TFT manufacturing process, the etching offset between the photoresist and the source and drain metals is small, and when N + at the TFT channel is etched, metal particles dropped from the source and drain metals easily contaminate the channel, affecting the TFT characteristics, and causing mura and other defects.
Therefore, a method for manufacturing a thin film transistor provided by an embodiment of the present invention includes:
sequentially forming an active layer, an additional film layer and a pattern of a source electrode and a drain electrode on a substrate; wherein,
the patterns of the additional film layer are respectively arranged at two ends of the active layer and can be completely covered by the patterns of the source and drain electrodes; the additional film layer and the source and drain electrodes can be etched by adopting different etching liquids.
According to the manufacturing method of the thin film transistor, the additional film layer is manufactured between the active layer and the source and drain electrodes, and the additional film layer and the source and drain electrodes can be etched by different etching liquids, so that the method provided by the invention can etch the additional film layer firstly to form offset between the additional film layer and the source and drain electrodes, further, when the source and drain electrode metal is etched, the contact area between the etching liquid and the source and drain electrode metal is increased on the premise of not reducing the size of a channel, the etching rate of the source and drain electrode metal is accelerated, further, on the premise of slightly increasing the etching time, the etching offset between the photoresist and the source and drain electrode metal is increased, the pollution of metal particles falling from the source and drain electrode metal to the TFT channel is reduced when the N + at the position of the TFT channel is etched by adopting a dry etching method, and the uniformity effect of the TFT is improved. Meanwhile, the etching rate of the region with the drain electrode needing etching is accelerated, and the etching rate of the other regions of the source electrode and the drain electrode needing not etching is not changed, so that the probability of the open circuit phenomenon of the metal of the source electrode and the drain electrode can be reduced.
Preferably, the active layer, the additional film layer, and the source/drain pattern are sequentially formed on the substrate, and specifically include:
sequentially forming an active layer and an additional film layer capable of covering the active layer on a substrate;
sequentially forming a whole layer of metal film and a photoresist layer with a photoresist completely removed area and a photoresist reserved area on the additional film layer;
and respectively etching the additional film layer and the metal film by using different etching liquids by utilizing the shielding of the photoresist in the photoresist retention region to form a pattern of the additional film layer and a pattern of the source and drain electrodes, which are smaller than the pattern of the photoresist retention region.
Preferably, the additional film layer and the metal film are etched respectively by using different etching liquids by using the shielding of the photoresist in the photoresist retention region, so as to form a pattern of the additional film layer and a pattern of the source and drain electrodes, which are smaller than the pattern of the photoresist retention region, and the method specifically comprises the following steps:
carrying out first etching on the metal film by using a first etching liquid by utilizing the shielding of the photoresist in the photoresist retention area, removing the metal film in the completely removed area of the photoresist, and forming a pattern of the metal film, which is the same as the pattern of the photoresist retention area;
etching the additional film layer by using a second etching liquid by utilizing the shielding of the photoresist in the photoresist retention area, removing the completely removed photoresist area and part of the additional film layer in the photoresist retention area, and obtaining a pattern of the additional film layer smaller than the pattern of the metal film;
carrying out second etching on the graph of the metal film obtained after the first etching by using first etching liquid by utilizing the shielding of the photoresist in the photoresist retention area, removing part of metal on the graph of the metal film, which is close to the completely removed area of the photoresist, and obtaining the graph of the source and drain with preset offset with the graph in the photoresist retention area;
and forming a channel region on the active layer by using the shielding of the photoresist in the photoresist retention region and adopting a dry etching process.
Preferably, after forming a whole metal film on the additional film layer, before forming a photoresist layer having a photoresist completely removed region and a photoresist remaining region, the method further includes:
and carrying out hydrogenation treatment on the additional film layer.
Preferably, before the sequentially forming the active layer, the additional film layer, and the source and drain patterns on the substrate, the method further includes:
forming a pattern of a grid electrode on a substrate through a one-time composition process;
and forming a gate insulating layer on the substrate with the pattern of the gate electrode.
The embodiment of the invention provides a thin film transistor, which comprises: the semiconductor device comprises an active layer, a source drain electrode and an additional film layer, wherein the additional film layer is arranged on the active layer and close to one side of the source drain electrode; wherein,
the patterns of the additional film layer are respectively arranged at two ends of the active layer and can be completely covered by the patterns of the source and the drain.
Preferably, the thickness of the additional film layer is smaller than that of the source and drain electrodes.
Preferably, the orthographic projection of the pattern of the additional film layer on the active layer is positioned in the orthographic projection of the pattern of the source and drain electrodes on the active layer.
Preferably, the additional film layer is a film layer after hydrogenation treatment.
Preferably, the material of the additional film layer is Indium Tin Oxide (ITO).
An array substrate provided in an embodiment of the present invention includes: a pixel electrode, and the thin film transistor provided by the embodiment of the present invention; and the additional film layer in the thin film transistor and the pixel electrode are arranged at the same layer.
The display device provided by the embodiment of the invention comprises the array substrate provided by the embodiment of the invention.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a thin film transistor according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first thin film transistor according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a second method for fabricating a thin film transistor according to an embodiment of the present invention;
fig. 4a is a schematic structural diagram of a second thin film transistor according to an embodiment of the present invention;
fig. 4b is a schematic structural diagram of a third thin film transistor according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating the overall steps of the method for fabricating the thin film transistor according to the embodiment of the present invention;
fig. 6 is a schematic structural diagram of a fourth thin film transistor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The thickness of each layer of thin film and the size and shape of the area in the drawings do not reflect the actual proportion of the thin film transistor and the array substrate, and are only used for schematically illustrating the content of the invention.
The manufacturing method of the thin film transistor provided by the embodiment of the invention comprises the following steps: sequentially forming an active layer, an additional film layer and a pattern of a source electrode and a drain electrode on a substrate; the patterns of the additional film layer are respectively arranged at two ends of the active layer and can be completely covered by the patterns of the source and the drain; the additional film layer and the source and drain electrodes can be etched by adopting different etching liquids.
In the manufacturing method of the thin film transistor provided by the embodiment of the invention, because the additional film layer is added between the active layer and the source and drain electrodes, the etching rate of the source and drain electrodes can be accelerated by increasing the contact area of the etching liquid and the source and drain electrodes, so that the etching offset between the photoresist and the source and drain electrodes can be increased on the premise of slightly increasing the etching time, the pollution of metal particles falling from the source and drain electrodes to the TFT channel when the N + at the TFT channel is etched by adopting a dry etching method is reduced, and the uniformity effect of the TFT is improved.
At present, in the existing TFT manufacturing process, the etching offset between the photoresist and the source and drain metal is small, and when a dry etching method is adopted to etch N + at a TFT channel, the problem that metal particles falling from the source and drain metal are easy to pollute the TFT channel and influence the TFT characteristics due to the poor anisotropic property of the dry etching process is likely to occur, so that mura and other adverse problems are caused.
In the existing solution, although the etching offset between the photoresist and the source and drain metal can be increased, the manufacturing process of the photoresist needs to reduce the length of the channel, so that PR (photo-resist) glue is easy to adhere at the channel, and the channel cannot be normally formed; or because the etching time is increased when the source and drain electrodes are reduced, the problem of open circuit is easily caused at the positions where the metal routing of the source and drain electrodes is narrow.
Based on this, in the manufacturing method of the thin film transistor provided by the embodiment of the present invention, an additional film layer is manufactured between the active layer and the source/drain electrode, and the additional film layer and the source/drain electrode can be etched by using different etching solutions, so that an offset is formed between the additional film layer and the source/drain electrode by etching the additional film layer first, and when a source/drain electrode metal is etched, an etching rate of the source/drain electrode metal is increased by increasing a contact area between the etching solution and the source/drain electrode metal, and a processing time is reduced; meanwhile, the etching rate of the region with the drain electrode needing etching is accelerated, and the etching rate of the other regions of the source electrode and the drain electrode needing not etching is not changed, so that the probability of the open circuit phenomenon of the metal of the source electrode and the drain electrode can be reduced.
Specifically, in a specific implementation, in the manufacturing method of the thin film transistor provided in the embodiment of the present invention, the active layer, the additional film layer, and the source and drain patterns are sequentially formed on the substrate, as shown in fig. 1, which is a step flow diagram of the manufacturing method of the first thin film transistor provided in the embodiment of the present invention, and the method can be specifically implemented by the following steps:
step 101, sequentially forming an active layer and an additional film layer capable of covering the active layer on a substrate;
102, sequentially forming a whole layer of metal film and a photoresist layer with a photoresist completely removed area and a photoresist reserved area on the additional film layer;
and 103, etching the additional film layer and the metal film respectively by using different etching liquids by using the shielding of the photoresist in the photoresist reserved area to form a pattern of the additional film layer and a pattern of the source and drain which are smaller than the pattern of the photoresist reserved area.
In specific implementation, when the step 101 is implemented, and when an active layer 200 and an additional film layer 300 capable of covering the active layer are sequentially formed on the substrate 100, as shown in fig. 2, for a structural schematic diagram of the first thin film transistor provided in the embodiment of the present invention, the active layer 200 with a certain thickness may be deposited by magnetron sputtering, and preferably, an amorphous silicon material is adopted, which is easy to prepare in a large area at a low temperature, and the manufacturing technology is mature; after that, an additional film 300 with a certain thickness is deposited by magnetron sputtering, and the size of the additional film can be set according to the requirement, for example, the entire active layer can be covered.
In specific implementation, as shown in fig. 2, a whole metal thin film 400 for manufacturing a source/drain and a photoresist layer 500 with a mask pattern are sequentially formed on the additional film layer 300 in the step 102, where the photoresist layer 500 may be exposed and developed by using a mask plate, so as to obtain a photoresist layer with a photoresist completely removed region a and a photoresist remaining region b.
In specific implementation, the step 103 forms the pattern of the additional film layer and the pattern of the source and drain electrodes smaller than the pattern of the photoresist reserved region by using the shielding of the photoresist reserved region, which can be implemented in the following manner, as shown in fig. 3, and is a step flow chart of a manufacturing method of a second thin film transistor provided by the embodiment of the present invention, and specifically includes the following steps:
1031, using the photoresist shielding of the photoresist retention region to perform a first etching on the metal film by using a first etching solution, removing the metal film in the photoresist completely removed region, and forming a metal film pattern which is the same as the pattern of the photoresist retention region;
step 1032, etching the additional film layer by using a second etching solution by using the photoresist shielding of the photoresist reserved area, and removing the completely removed photoresist area and the additional film layer of a part of the photoresist reserved area to obtain a pattern of the additional film layer smaller than the pattern of the metal film;
1033, by using the shielding of the photoresist in the photoresist retention region, performing a second etching on the pattern of the metal film obtained after the first etching by using a first etching solution to remove a part of metal on the pattern of the metal film, which is close to the completely removed region of the photoresist, and obtaining a pattern of the source and drain with a preset offset with the pattern of the photoresist retention region;
step 1034, a channel region on the active layer is formed by a dry etching process using the photoresist mask of the photoresist reserved region.
In specific implementation, when the step 1031 is implemented, as shown in fig. 4a, for a structural schematic diagram of a second thin film transistor provided in an embodiment of the present invention, a first etching solution capable of etching a metal film is used to perform a first etching on a whole formed metal film by using the shielding of a photoresist in the photoresist retention region b, so as to remove the metal film of a portion of the photoresist completely removed region a, and a pattern, as shown in fig. 4a, where an edge of a pattern 4001 of the metal film is flush with an edge of the photoresist retention region is formed.
In specific implementation, when the step 1032 is implemented, as shown in fig. 4b, for a structural schematic diagram of the third thin film transistor provided in the embodiment of the present invention, by using the shielding of the photoresist in the photoresist retention region b, and using a second etching solution capable of etching the additional film layer, etching the additional film layer covering the active layer, removing the additional film layer in the area a where the photoresist is completely removed, and an additional film layer at the additional film layer c of a part of the photoresist reserved area to obtain a pattern of the additional film layer with the size of the pattern smaller than that of the pattern 4001 of the metal film, so that when the metal film is etched for the second time, the contact area of the etching liquid and the source and drain electrode metal can be increased through the region c, the etching rate of the source and drain electrode metal is accelerated, and further, the etching offset between the photoresist and the source and drain metal can be increased on the premise of slightly increasing the etching time.
In specific implementation, when the step 1033 is implemented, the thin film transistor shown in fig. 2 is obtained, in the step 1033, the first etching solution capable of etching the metal film is used to perform second etching on the pattern of the metal film obtained after the first etching by using the shielding of the photoresist in the photoresist retention region b, so as to remove a part of metal on the pattern of the metal film, which is close to the photoresist complete removal region (i.e., the region d shown in the figure), and obtain a pattern 400 of the source and drain with a preset offset d from the pattern of the photoresist retention region; the value of the preset offset d can be set as required, and preferably, the preset offset d is the minimum offset at which the source and drain metal does not pollute the channel when the channel region is etched.
In specific implementation, when the step 1034 is implemented, a channel region on the active layer is formed by a dry etching process using the photoresist in the photoresist retention region b for shielding. According to the method, the contact area of the etching liquid and the source and drain metal can be increased through the region c, the etching rate of the source and drain metal is accelerated, the etching offset between the photoresist and the source and drain metal can be increased on the premise of slightly increasing the etching time, the pollution of metal particles falling from the source and drain metal to a TFT channel is increased and reduced when the N + at the position of the TFT channel is etched by adopting a dry etching method, and the uniformity effect of the TFT is improved.
In specific implementation, after the step 1034 is implemented, the photoresist layer needs to be stripped to obtain a thin film transistor to be manufactured.
Preferably, before implementing step 1031, the method further includes:
firstly, forming a grid pattern on a substrate by a one-time composition process;
then, a gate insulating layer is formed on the substrate having the pattern of the gate electrode formed thereon.
That is, when the method for manufacturing a thin film transistor according to the embodiment of the present invention is applied to a bottom gate thin film transistor, as shown in fig. 2, a pattern of a gate electrode 600 is first manufactured, and then an active layer 200, an additional film layer 300, and a pattern of a source drain 400 are sequentially formed on a gate insulating layer 700 according to the method, and a protective layer is generally manufactured next, so that when the thin film transistor is applied to an array substrate, a drain of the thin film transistor is connected to a pixel electrode manufactured on the protective layer through a via hole in the protective layer.
In the implementation, in order to reduce the process time, it is necessary to increase the etching rate of the additional film as much as possible and to accelerate the etching of the additional film, and preferably, after forming a whole metal film on the additional film, before forming a photoresist layer having a photoresist completely removed region and a photoresist reserved region, the method further includes: the additional film layer is subjected to a hydrogenation treatment. Other treatments can be performed on the additional film layer according to needs, or the material with the higher etching rate is selected to manufacture the additional film layer.
Based on the same inventive concept, the embodiment of the invention also provides a manufacturing method of the array substrate, which comprises the following steps: manufacturing the thin film transistor provided by the embodiment of the invention; and forming patterns of an additional film layer and a pixel electrode on the thin film transistor through a one-step composition process. The additional film layer can be arranged in the same layer with the pixel electrode, and can also be arranged in the same layer with other film layers according to design requirements.
The manufacturing method of the thin film transistor provided by the embodiment of the invention is not limited to the type of the thin film transistor, and can be applied to a top gate type thin film transistor and a bottom gate type thin film transistor. For convenience of description, the thin film transistor included in the array substrate provided in the embodiment of the present invention is a bottom gate type, and as shown in fig. 5, the overall step flowchart of the method for manufacturing the thin film transistor provided in the embodiment of the present invention includes the following steps:
step 501, forming a grid pattern on a substrate through a one-time composition process;
step 502, forming a gate insulating layer on a substrate having a pattern of a gate electrode formed thereon;
step 503, sequentially forming an active layer and an additional film layer capable of covering the active layer on the substrate base plate;
step 504, sequentially forming a whole layer of metal film and a photoresist layer with a photoresist completely removed area and a photoresist reserved area on the additional film layer;
505, performing first etching on the metal film by using a first etching solution by using the shielding of the photoresist in the photoresist retention region, removing the metal film in the photoresist completely removed region, and forming a pattern of the metal film, which is the same as the pattern of the photoresist retention region;
step 506, etching the additional film layer by using a second etching solution by using the photoresist shielding of the photoresist reserved area, and removing the completely removed photoresist area and the additional film layer of a part of the photoresist reserved area to obtain a pattern of the additional film layer smaller than that of the metal film;
step 507, performing second etching on the graph of the metal film obtained after the first etching by using a first etching solution by using the shielding of the photoresist in the photoresist retention region, removing part of metal on the graph of the metal film, which is close to the completely removed region of the photoresist, and obtaining a graph of the source and drain with a preset offset with the graph in the photoresist retention region;
and step 508, forming a channel region on the active layer by using a dry etching process by using the photoresist shielding of the photoresist reserved region.
Based on the same inventive concept, an embodiment of the present invention provides a thin film transistor, including: the active layer 200, the source and drain 400, and the additional film layer 300 arranged on the active layer 200 near one side of the source and drain 400; the patterns of the additional film 300 are respectively disposed at two ends of the active layer 200 and can be completely covered by the patterns of the source and drain electrodes 400. As shown in fig. 2, the additional film layer 300 is located between the active layer 200 and the source and drain electrodes 400, and the pattern of the additional film layer 300 can be completely covered by the pattern of the source and drain electrodes 400.
As shown in fig. 2, in order to accelerate the etching of the additional film and reduce the processing time, preferably, the thickness of the additional film is smaller than the thickness of the source/drain. Therefore, the contact area between the etching liquid and the source and drain electrodes can be increased through the offset between the additional film layer and the source and drain electrodes, and excessive processing time caused by etching of the additional film layer can be avoided.
In specific implementation, the size of the pattern of the additional film layer may be set as required, as shown in fig. 2, one end of the additional film layer, which is far away from the channel region, is flush with the edge of the active layer; the pattern of the additional film layer can be reduced according to the requirement, and preferably, the orthographic projection of the pattern of the additional film layer on the active layer is positioned in the orthographic projection of the pattern of the source and the drain on the active layer. Fig. 6 is a schematic structural diagram of a fourth thin film transistor according to an embodiment of the present invention, in which an end of the additional film layer away from the channel region has a certain offset from an edge of the active layer.
In the specific implementation, in order to increase the etching independence of the additional film layer, preferably, the additional film layer is a film layer subjected to hydrogenation treatment. In order to avoid increasing the number of masks, the additional film layer may be disposed on the same layer as the pixel electrode, and preferably, the material of the additional film layer is ITO.
Based on the same inventive concept, an embodiment of the present invention further provides an array substrate, including: a pixel electrode, and the thin film transistor provided by the embodiment of the present invention; the additional film layer in the thin film transistor and the pixel electrode are arranged on the same layer.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the array substrate provided in the embodiment of the present invention, where the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can refer to the above embodiments of the array substrate, and repeated descriptions are omitted.
In summary, in the method for manufacturing a thin film transistor of the present invention, an additional film layer is formed between the active layer and the source/drain electrode, and the additional film layer and the source/drain electrode can be etched with different etching solutions, so that the method of the present invention can etch the additional film layer first, so as to form an offset between the additional film layer and the source/drain electrode, and further increase the etching offset between the photoresist and the source/drain electrode metal on the premise of not reducing the size of the channel, increasing the contact area between the etching solution and the source/drain electrode metal, increasing the etching rate of the source/drain electrode metal, and further increasing the etching time, thereby reducing the pollution of metal particles dropped from the source/drain electrode metal to the TFT channel when etching the N + of the TFT channel by using a dry etching method, and improving the uniformity of the TFT. Meanwhile, the etching rate of the region with the drain electrode needing etching is accelerated, and the etching rate of the other regions of the source electrode and the drain electrode needing not etching is not changed, so that the probability of the open circuit phenomenon of the metal of the source electrode and the drain electrode can be reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method for manufacturing a thin film transistor includes:
sequentially forming an active layer, an additional film layer and a pattern of a source electrode and a drain electrode on a substrate; wherein,
the patterns of the additional film layer are respectively arranged at two ends of the active layer and can be completely covered by the patterns of the source and drain electrodes; the additional film layer and the source and drain electrodes can be etched by adopting different etching liquids;
the method for forming the active layer, the additional film layer and the source and drain electrode patterns on the substrate comprises the following steps:
sequentially forming an active layer and an additional film layer capable of covering the active layer on a substrate;
sequentially forming a whole layer of metal film and a photoresist layer with a photoresist completely removed area and a photoresist reserved area on the additional film layer;
respectively etching the additional film layer and the metal film by using different etching liquids by utilizing the shielding of the photoresist in the photoresist retention region to form a pattern of the additional film layer and a pattern of the source and drain electrodes, wherein the pattern of the additional film layer is smaller than the pattern of the photoresist retention region;
the method comprises the following steps of utilizing the shielding of the photoresist retention region, and respectively etching the additional film layer and the metal film by adopting different etching liquids to form a pattern of the additional film layer and a pattern of the source drain electrode, wherein the pattern of the additional film layer is smaller than the pattern of the photoresist retention region, and the method specifically comprises the following steps:
carrying out first etching on the metal film by using a first etching liquid by utilizing the shielding of the photoresist in the photoresist retention area, removing the metal film in the completely removed area of the photoresist, and forming a pattern of the metal film, which is the same as the pattern of the photoresist retention area;
etching the additional film layer by using a second etching liquid by utilizing the shielding of the photoresist in the photoresist retention area, removing the completely removed photoresist area and part of the additional film layer in the photoresist retention area, and obtaining a pattern of the additional film layer smaller than the pattern of the metal film;
carrying out second etching on the graph of the metal film obtained after the first etching by using first etching liquid by utilizing the shielding of the photoresist in the photoresist retention area, removing part of metal on the graph of the metal film, which is close to the completely removed area of the photoresist, and obtaining the graph of the source and drain with preset offset with the graph in the photoresist retention area;
and forming a channel region on the active layer by using the shielding of the photoresist in the photoresist retention region and adopting a dry etching process.
2. The method of claim 1, wherein after forming a full layer of the metal film on the additional film layer, prior to forming the photoresist layer having the photoresist fully removed region and the photoresist remaining region, further comprising:
and carrying out hydrogenation treatment on the additional film layer.
3. The method of claim 1 or 2, wherein before sequentially patterning the active layer, the additional film layer, and the source and drain electrodes on the substrate base plate, further comprising:
forming a pattern of a grid electrode on a substrate through a one-time composition process;
and forming a gate insulating layer on the substrate with the pattern of the gate electrode.
4. A thin film transistor, comprising: the semiconductor device comprises an active layer, a source drain electrode and an additional film layer, wherein the additional film layer is arranged on the active layer and close to one side of the source drain electrode; wherein,
the additional film layers comprise a first additional film layer and a second additional film layer, the patterns of the first additional film layer are all arranged at one end of the upper surface of the active layer, and the patterns of the second additional film layer are all arranged at the other end of the upper surface of the active layer;
the source and drain electrodes comprise a first source and drain electrode and a second source and drain electrode, the graph of the first source and drain electrode and the graph of the first additional film layer are positioned on the same side of the active layer, and the graph of the second source and drain electrode and the graph of the second additional film layer are positioned on the same side of the active layer;
the pattern of the first additional film layer can be completely covered by the pattern of the first source drain electrode, the pattern of the first additional film layer and the pattern of the first source drain electrode are not flush in the middle area close to the upper surface of the active layer, the extending size of the pattern of the first additional film layer close to the middle area is D, and the difference of the extending size of the pattern of the first additional film layer close to the middle area and the extending size of the pattern of the first source drain electrode close to the middle area is D; the pattern of the second additional film layer can be completely covered by the pattern of the second source drain electrode, the pattern of the second additional film layer and the pattern of the second source drain electrode are not flush near the middle region, the extending size of the pattern of the first additional film layer near the middle region and the extending size of the pattern of the first source drain electrode near the middle region have a difference D; d is used for representing the minimum offset that the source and drain metal can not pollute the channel when the channel region is etched; the channel region is positioned between the first source drain electrode and the second source drain electrode;
the additional film layer and the source and drain electrodes can be etched by adopting different etching liquids.
5. The thin film transistor of claim 4, in which a thickness of the additional film layer is less than a thickness of the source and drain electrodes.
6. The thin film transistor of claim 4, wherein an orthographic projection of the pattern of the additional film layer on the active layer is within an orthographic projection of the pattern of the source and drain electrodes on the active layer.
7. The thin film transistor of claim 4, wherein the additional film layer is a hydrotreated film layer.
8. The thin film transistor of any of claims 4-7, wherein the additional film layer is made of Indium Tin Oxide (ITO).
9. An array substrate, comprising: a pixel electrode, and the thin film transistor according to any one of claims 4 to 8; and the additional film layer in the thin film transistor and the pixel electrode are arranged at the same layer.
10. A display device comprising the array substrate according to claim 9.
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