CN105990423A - Transverse dual-field-effect tube - Google Patents
Transverse dual-field-effect tube Download PDFInfo
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- CN105990423A CN105990423A CN201510054806.3A CN201510054806A CN105990423A CN 105990423 A CN105990423 A CN 105990423A CN 201510054806 A CN201510054806 A CN 201510054806A CN 105990423 A CN105990423 A CN 105990423A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The present invention provides a transverse dual-field-effect tube. More than one gate groove structures are added into the source structure of a single cell, a gate lead-out terminal is led out from the gate groove to be taken as a gate electrode, so that when a certain voltage is supplied to the gate electrode, the gate insulation layers at two sides of the groove and a first conductive type trap form inversion layers, namely conductive channels; and when a drain structure (a first conductive type drain doping area) has voltage, there is current flowing in the conductive channels. If the number of the gate groove structures is N, the number of the conductive channels flowing the current are 2N, and the current density is substantially increased compared to the current density in the single cell structure of a traditional LDMOS, and therefore the current density of each device may be entirely improved in the multi-cell structure. In the same work current, the transverse insulated gate bipolar transistor allows the area of the device to be reduced and the conduction resistance to be decreased because of the bigger work current of the single cell structure.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly to a kind of horizontal dual pervasion field effect pipe.
Background technology
Power field effect pipe mainly includes vertical bilateral diffusion field-effect pipe (Vertical Double-Diffused
MOSFET, VDMOS) and horizontal dual pervasion field effect pipe (Lateral Double-Diffused MOSFET,
LDMOS) two types.Wherein, compared to vertical bilateral diffusion field-effect pipe VDMOS, horizontal double diffusion
Field effect transistor LDMOS has plurality of advantages, and such as, the latter has more preferable heat stability and frequency stable
Property, higher gain and durability, lower feedback capacity and thermal resistance, and constant input impedance and more
Simple biasing circuit.
Traditional LDMOS device, the conducting channel of device and drift region are all laterally, so at device just
When conducting, carrier is moved by the drift of device surface；Reverse pressure time, from drain terminal along device
Surface drift region exhausts.Electric current can only all concentrate on table by lateral drift to the other end, the injection of carrier
Face, the most such individual devices operating current when conducting is the least.In order to reach higher work electricity
Stream, obtains the longest by drift region design, and the size of device is elongated the most therewith, so causes device area very big,
The electric conduction resistive also resulting in device is big, and the switching characteristic of device weakens the most therewith.
Summary of the invention
, conducting resistance the most at least within a kind of shortcoming big based on tradition LDMOS device area, it is necessary to carry
For a kind of horizontal dual pervasion field effect pipe, this horizontal dual pervasion field effect pipe has that operating current is big, device side
Amass the advantage little, conducting resistance is little.
A kind of horizontal dual pervasion field effect pipe, including:
First conductivity type substrate；
Insulating barrier, is formed in described first conductivity type substrate；
Second conductive type epitaxial layer, is formed on described insulating barrier；
Field oxide structure, is formed on described second conductive type epitaxial layer；
First conductive type of trap, is formed on described second conductive type epitaxial layer, and is positioned at the oxidation of described field
The side of Rotating fields；
More than one gate trench structure, described more than one trench gate structure is the most interspersed is arranged on institute
Stating in the first conductive type of trap, the bottom land of described gate trench structure extends to described second conduction type extension
Layer；Described gate trench structure includes groove and the conductive material being filled in described groove, in described groove
Surface be also formed with gate insulation layer；
Second conduction type source doping region, is formed at described the first of each described gate trench structure both sides and leads
On the top layer of electricity type trap；
First conduction type source doping region, is formed at described second conduction type doped region away from described grid
On the top layer of described first conductive type of trap of groove structure side；
Second conductivity type drain doped region, is formed on described second conductive type epitaxial layer, and is positioned at institute
State field oxide structure and differ from the side of described first conductive type of trap side；
Gate terminal, described gate terminal electrically connects with the conductive material in described groove；
Source terminal, described source terminal and the second conduction type source doping region, the first conduction type
Source doping region electrically connects；
And drain terminal, described drain terminal electrically connects with described second conductivity type drain doped region.
Wherein in an embodiment:
Described first conduction type is p-type, and described second conduction type is N-type.
Wherein in an embodiment:
Described first conductivity type substrate is P+ type substrate, and described second conductive type epitaxial layer is N-type extension
Layer；Described first conductive type of trap is P-type trap, and described second conduction type source doping region is that N+ source electrode is mixed
Miscellaneous district, described first conduction type source doping region is P+ source doping region；Described second conductivity type drain
Doped region is n+ type drain doping region.
Wherein in an embodiment:
Also include the second conductive type of trap, be formed on described second conductive type epitaxial layer, and be positioned at described
Field oxide structure differs from the side of described first conductive type of trap side；Described second conductivity type drain is mixed
Miscellaneous district is formed on the top layer of described second conductive type of trap；
Wherein in an embodiment:
Also include that conducting material structure, described conducting material structure are formed on described field oxide structure close
One end of described second conductivity type drain doped region；Described drain terminal also with described conducting material structure
Electrical connection.
Wherein in an embodiment:
Also including that the first conduction type embeds district, described first conduction type embedding district is formed at described first and leads
Between electricity type source doping region and described first conductive type of trap so that described first conduction type source electrode is mixed
Completely cut off between miscellaneous district and described first conductive type of trap；It is that p-type embeds district that described first conduction type embeds district.
Wherein in an embodiment:
Also including that the second conduction type embeds district, described second conduction type embeds district and is formed at described grid ditch
In place of the bottom land of groove structure and the handing-over of the second conductive type epitaxial layer；It is N that described second conduction type embeds district
Type embeds district.
Wherein in an embodiment, the material of described first conductivity type substrate and the second conduction type extension
The material of layer is silicon, carborundum, GaAs, indium phosphide or germanium silicon.
Wherein in an embodiment, the material of described insulating barrier, field oxide and gate insulation layer is silicon
Oxide.
Wherein in an embodiment, described conductive material is polysilicon.
Above-mentioned horizontal dual pervasion field effect pipe, adds more than one to the source configuration part in single cellular
Gate trench structure, and from this gate trench structure extraction gate terminal as gate electrode, thus when at grid
When electrode is plus certain voltage, gate insulation layer and first conductive type of trap of groove both sides all form inversion layer,
I.e. conducting channel；When having voltage on drain electrode structure (the second conductivity type drain doped region), conducting channel
In have electric current to flow through.If the number of gate trench structure is N number of, then the conducting channel that electric current flows through just has
2N, dramatically increase than electric current density in the single structure cell of traditional LDMOS, such that it is able to
The electric current density of individual devices is totally improve under multi cell structure.Thus, under same operating current,
Above-mentioned horizontal dual pervasion field effect pipe because the bigger operating current of single structure cell make device area little,
Conducting resistance is little.And under same device area, above-mentioned horizontal dual pervasion field effect Guan Ze has bigger
Operating current.
Accompanying drawing explanation
Fig. 1 is the structural representation of first embodiment horizontal dual pervasion field effect pipe；
Fig. 2 is the structural representation of gate trench structure；
Fig. 3 is the structural representation of the second embodiment horizontal dual pervasion field effect pipe；
Fig. 4 is the structural representation of the 3rd embodiment horizontal dual pervasion field effect pipe；
Fig. 5 is the structural representation of the 4th embodiment horizontal dual pervasion field effect pipe；
Fig. 6 is the structural representation of the 5th embodiment horizontal dual pervasion field effect pipe.
Detailed description of the invention
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.
Accompanying drawing gives presently preferred embodiments of the present invention.But, the present invention can come real in many different forms
Existing, however it is not limited to embodiment described herein.On the contrary, providing the purpose of these embodiments is to make this
The understanding of disclosure of the invention content is more thorough comprehensively.
Unless otherwise defined, all of technology used herein and scientific terminology and the technology belonging to the present invention
The implication that the technical staff in field is generally understood that is identical.The art used the most in the description of the invention
Language is intended merely to describe the purpose of specific embodiment, it is not intended that limit the present invention.Art used herein
Language "and/or" includes the arbitrary and all of combination of one or more relevant Listed Items.
Semiconductor applications vocabulary cited herein is the technical words that those skilled in the art commonly use, the most right
In p-type and N-type impurity, for distinguishing doping content, easily P+ type is represented the p-type of heavy dopant concentration,
The p-type of doping content in p-type representative, P-type represents the p-type that concentration is lightly doped, and it is dense that N+ type represents heavy doping
The N-type of degree, the N-type of doping content in N-type representative, N-type represents the N-type that concentration is lightly doped.
Below in conjunction with the accompanying drawings, the detailed description of the invention of the present invention is described in detail.In below describing, the
One conduction type is p-type, and the second conduction type is N-type.
Fig. 1 is the structural representation of first embodiment horizontal dual pervasion field effect pipe.
First embodiment:
A kind of horizontal dual pervasion field effect pipe, including: the first conductivity type substrate 100, insulating barrier 200, the
Two conductive type epitaxial layers 300, field oxide structure the 400, first conductive type of trap 500, gate trench are tied
The 710, second conduction type source doping region 720, structure the 600, first conduction type source doping region, second lead
Electricity type drain doped region 910, gate terminal 10, source terminal 20 and drain terminal 30.
The material of the first conductivity type substrate 100 is silicon, carborundum, GaAs, indium phosphide or germanium silicon, the
One conductivity type substrate is P+ type substrate (psub).
Insulating barrier 200 is formed in the first conductivity type substrate 100, and the material of insulating barrier is the oxide of silicon,
Can be silicon dioxide.Insulating barrier 200 functionally for be oxygen buried layer.Obstruct due to insulating barrier 200
Effect, the first conductivity type substrate 100 is little to component influences, thus the first conductivity type substrate 100 can
To be heavily doped (P+).
Second conductive type epitaxial layer 300 is formed on insulating barrier 200, the second conductive type epitaxial layer 300
For N-type epitaxial layer.Second conductive type epitaxial layer 300 is as drift region, the conduction type having and first
Conductivity type substrate 100 is contrary.The material of the second conductive type epitaxial layer 300 is silicon, carborundum, arsenic
Gallium, indium phosphide or germanium silicon.
Field oxide structure 400 is formed on the second conductive type epitaxial layer 300, field oxide structure 400
The oxide that material is silicon, can be silicon dioxide.Field oxide structure 400 is mainly used in separating source electrode
Structure and drain electrode structure.
First conductive type of trap 500 is formed on the second conductive type epitaxial layer 300, and is positioned at field oxide
The side of structure 400.First conductive type of trap is P-type trap, as source configuration buffer area, to device
Conducting hole is injected and is played a role with pressure.
More than one trench gate structure 600 is the most interspersed to be arranged in the first conductive type of trap 500, grid
The bottom land of groove structure 600 extends to the second conductive type epitaxial layer 300.Gate trench structure 600 includes ditch
Groove 610 and the conductive material 620 being filled in groove, the surface in groove 610 is also formed with gate insulation layer
630.Conductive material 620 is polysilicon, and the material of gate insulation layer 630 is the oxide of silicon, can be dioxy
SiClx.Gate terminal 10 electrically connects with the conductive material 620 in groove 610, and gate terminal 10 is just
It it is gate contact electrode.
Fig. 2 is the structural representation of gate trench structure.
Grid is imbedded in the first conductive type of trap 500 with the form of groove, thus when at gate electrode (grid
Exit 10) plus certain voltage time, the gate insulation layer 630 of both sides and the first conduction type in groove 610
Trap 500 all forms inversion layer, i.e. conducting channel；When drain electrode structure (the second conductivity type drain doped region 910)
On when having voltage, conducting channel has electric current flow through.If the number of gate trench structure 600 is N number of,
The conducting channel that then electric current flows through just has 2N, than the single cellular of traditional single-groove road SOI-LIGBT
In structure, electric current density dramatically increases, such that it is able to totally improve the electricity of individual devices under multi cell structure
Current density.Thus, under same operating current, operating current that single structure cell is bigger so that
Device area is little, conduction voltage drop is little.And under same device area, so that above-mentioned horizontal double diffusion
Field effect transistor then has bigger operating current.
Second conduction type source doping region 720 is formed at the first conduction of each gate trench structure 600 both sides
On the top layer of type trap 500.Second conduction type source doping region 720 is N+ source doping region, by first
Conductive type of trap 500 encases.
First conduction type source doping region 710 is formed at the second conduction type doped region 720 away from grid ditch
On the top layer of the first conductive type of trap 500 of groove structure 600 side.First conduction type source doping region is
P+ source doping region, is encased by the first conductive type of trap 500 equally.I.e. from gate trench structure 600 both sides
Extend, be the 720, first conduction type source doping region 710, the second conduction type source doping region the most respectively.
Source terminal 20 and the 720, first conduction type source doping region, the second conduction type source doping region
710 electrical connections, source terminal 20 is exactly Source contact electrode.
Second conductivity type drain doped region 910 is formed on the second conductive type epitaxial layer 300, and is positioned at
Field oxide structure 400 differs from the side of the first conductive type of trap 500 side.Second conductivity type drain is mixed
Miscellaneous district 910 is n+ type drain doping region.The i.e. side of field oxide structure 400 is the first conductive type of trap 500,
Opposite side is the second conductivity type drain doped region 910.
Drain terminal 30 electrically connects with the second conductivity type drain doped region 910, and drain terminal 30 is just
It it is drain contact electrode.
Gate terminal 10, source terminal 20 and drain terminal 30 are generally formed by conductive material, example
Such as copper, aluminum, alusil alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide etc., thing can be passed through
Reason/chemical gaseous phase formation of deposits.
Using at the raw material realized is with the oxygen buried layer (insulating barrier 200) sandwich structure as intermediate layer, i.e.
Soi structure, it is also possible to be that dielectric substrate (the first conductivity type substrate 100) adds top monocrystalline silicon (second leads
Electricity type epitaxial layer 300) double layer material.When soi structure making devices, only use the silicon layer (of top layer
Two conductive type epitaxial layers 300) it is used as element manufacturing layer, i.e. form the structures such as source, leakage, channel region, lining
The end (the first conductivity type substrate 100), only plays a supportive role, and the oxygen buried layer in this structure and substrate are in electricity
On achieve and keep apart, and medium isolation structure the most in addition between device and device, it is possible to realize whole
Individual device completely isolated.
In original material, top layer silicon (the second conductive type epitaxial layer 300) needs have certain thickness,
The degree of depth of trench gate structure 600 to be thicker than, so can make trench gate structure 600 to oxygen buried layer (insulating barrier
200) there is sufficiently large distance between so that the circulation path of electronics is the broadest, and makes in conducting state
Under ON resistance less, also make simultaneously reverse pressure time electric field distribution more uniform.
Fig. 3 is the structural representation of the second embodiment horizontal dual pervasion field effect pipe.
Second embodiment:
It is with first embodiment difference, also includes the second conductive type of trap 800.Second conductive type of trap
800 are formed on the second conductive type epitaxial layer 300, and are positioned at field oxide structure 400 and differ from the first conduction
The side of type trap 500 side.Second conductive type of trap is N-type trap, belongs to middle doping content.Oxygen on the spot
The side changing Rotating fields 400 is the first conductive type of trap 500, and opposite side is the second conductive type of trap 800.
Under this structure, the second conductivity type drain doped region 910 is formed at the second conductive type of trap 800
On top layer.Second conductivity type drain doped region 910 is n+ type drain doping region, by the second conductive type of trap
800 encase.
The effect of the second conductive type of trap 800 be by drain electrode structure around drift region concentration improve, work as device
Reverse pressure time, protection drain terminal structure the second conductivity type drain doped region 910 the most depleted, by adjust
The implantation dosage of whole second conductive type of trap 800 can ensure that laterally also have surplus when the most completely depleted,
Thus can ensure that this device longitudinally punctures and can move to from surface internal, also reduce drain terminal drift simultaneously
The conducting resistance in district.
Fig. 4 is the structural representation of the 3rd embodiment horizontal dual pervasion field effect pipe
3rd embodiment:
It is with first embodiment difference, also includes conducting material structure 40.Conducting material structure 40 shape
Become one end near the second conductivity type drain doped region 910 on field oxide structure 400.Drain electrode is drawn
End 30 also electrically connects with conducting material structure 40.The material of conducting material structure can be polysilicon.
When device reverse pressure time, conducting material structure 40 and drain electrode structure have identical current potential so that
The current potential of oxide layer structure 400 has one to be similar to linear change from drain electrode structure to source configuration, drift
Electric Field Distribution in district's (the second conductive type epitaxial layer 300) approximates a linear change, so the most therewith
Drift region can be assisted to exhaust, allow the speed reversely exhausted can keep uniformly, when the concentration of drift region is omited
The electric field line that will not produce local time big is assembled and peak value electric field is occurred.So can properly increase drift region
Concentration reduces conduction voltage drop and does not change breakdown voltage and breakdown point.
Fig. 5 is the structural representation of the 4th embodiment horizontal dual pervasion field effect pipe
4th embodiment:
It is with first embodiment difference, also includes that the first conduction type embeds district 730.First conductive-type
It is p-type doped region that type embeds district 730, belongs to middle doping content.First conduction type embeds district 730 and is formed
Between the first conduction type source doping region 710 and the first conductive type of trap 500, namely the first conductive-type
Type embeds district 730 and is encased the first conduction type source doping region 710 so that the first conduction type source electrode is mixed
Completely cut off between miscellaneous district 710 and the first conductive type of trap 500.
When break-over of device, there is a parasitic NPN audion below source structure, when the base meeting audion
After the condition that few son can be getted over, may be such that this audion is opened, such that device is being opened
Stage lost efficacy.A p-type doped region is added below the first conduction type source doping region 710, permissible
Improving the base concentration of NPN pipe, minority carrier life time reduces and cannot get over to emitter stage, the most effectively keeps away
Exempt from the phenomenon that source parasitic triode is opened.
Fig. 6 is the structural representation of the 5th embodiment horizontal dual pervasion field effect pipe
5th embodiment:
It is with first embodiment difference, also includes that the second conduction type embeds district 740.Second conductive-type
Type embeds district 740 and embeds district for N-type, belongs to middle doping content.Second conduction type embeds district 740 and is formed
In place of the bottom land and the second conductive type epitaxial layer (drift region) 300 handing-over of gate trench structure 600, also
I.e. second conduction type embeds district 740 and is encased by the bottom land of gate trench structure 600 so that longitudinally conduction ditch
N-type carrier concentration below road becomes big.When device forward conduction, after electronics passes through conducting channel, by
Relatively big in the carrier concentration of this panel region, conducting resistance is obviously reduced, and electric current density is obviously enhanced.Adjust
After the degree of depth of good gate trench structure 600 and the second conduction type embed the impurity concentration in district 740, permissible
Device lateral breakdown voltage and drift region conducting resistance is made to obtain the most reasonably compromising.When lateral breakdown voltage is big
When longitudinal breakdown voltage, breakdown point is the most in vivo.
Above-mentioned horizontal dual pervasion field effect pipe, adds more than one to the source configuration part in single cellular
Gate trench structure, and from this gate trench structure extraction gate terminal as gate electrode, thus when at grid
When electrode is plus certain voltage, gate insulation layer and first conductive type of trap of groove both sides all form inversion layer,
I.e. conducting channel.When having voltage on drain electrode structure (the second conductivity type drain doped region), conducting channel
In have electric current to flow through.If the number of gate trench structure is N number of, then the conducting channel that electric current flows through just has
2N, dramatically increase than electric current density in the single structure cell of traditional single-groove road LDMOS, thus
The electric current density of individual devices can be totally improve under multi cell structure.Thus, at same work electricity
Flowing down, above-mentioned horizontal dual pervasion field effect pipe makes device side because of the operating current that single structure cell is bigger
Long-pending little, conduction voltage drop is little.And under same device area, above-mentioned horizontal dual pervasion field effect Guan Ze has
Bigger operating current.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for this area
Those of ordinary skill for, without departing from the inventive concept of the premise, it is also possible to make some deformation and
Improving, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended
Claim is as the criterion.
Claims (10)
1. a horizontal dual pervasion field effect pipe, it is characterised in that including:
First conductivity type substrate；
Insulating barrier, is formed in described first conductivity type substrate；
Second conductive type epitaxial layer, is formed on described insulating barrier；
Field oxide structure, is formed on described second conductive type epitaxial layer；
First conductive type of trap, is formed on described second conductive type epitaxial layer, and is positioned at the oxidation of described field
The side of Rotating fields；
More than one gate trench structure, described more than one trench gate structure is the most interspersed is arranged on institute
Stating in the first conductive type of trap, the bottom land of described gate trench structure extends to described second conduction type extension
Layer；Described gate trench structure includes groove and the conductive material being filled in described groove, in described groove
Surface be also formed with gate insulation layer；
Second conduction type source doping region, is formed at described the first of each described gate trench structure both sides and leads
On the top layer of electricity type trap；
First conduction type source doping region, is formed at described second conduction type doped region away from described grid
On the top layer of described first conductive type of trap of groove structure side；
Second conductivity type drain doped region, is formed on described second conductive type epitaxial layer, and is positioned at institute
State field oxide structure and differ from the side of described first conductive type of trap side；
Gate terminal, described gate terminal electrically connects with the conductive material in described groove；
Source terminal, described source terminal and the second conduction type source doping region, the first conduction type
Source doping region electrically connects；
And drain terminal, described drain terminal electrically connects with described second conductivity type drain doped region.
Horizontal dual pervasion field effect pipe the most according to claim 1, it is characterised in that:
Described first conduction type is p-type, and described second conduction type is N-type.
Horizontal dual pervasion field effect pipe the most according to claim 2, it is characterised in that:
Described first conductivity type substrate is P+ type substrate, and described second conductive type epitaxial layer is N-type extension
Layer；Described first conductive type of trap is P-type trap, and described second conduction type source doping region is that N+ source electrode is mixed
Miscellaneous district, described first conduction type source doping region is P+ source doping region；Described second conductivity type drain
Doped region is n+ type drain doping region.
Horizontal dual pervasion field effect pipe the most according to claim 3, it is characterised in that:
Also include the second conductive type of trap, be formed on described second conductive type epitaxial layer, and be positioned at described
Field oxide structure differs from the side of described first conductive type of trap side；Described second conductivity type drain is mixed
Miscellaneous district is formed on the top layer of described second conductive type of trap.
Horizontal dual pervasion field effect pipe the most according to claim 3, it is characterised in that:
Also include that conducting material structure, described conducting material structure are formed on described field oxide structure close
One end of described second conductivity type drain doped region；Described drain terminal also with described conducting material structure
Electrical connection.
Horizontal dual pervasion field effect pipe the most according to claim 3, it is characterised in that:
Also including that the first conduction type embeds district, described first conduction type embedding district is formed at described first and leads
Between electricity type source doping region and described first conductive type of trap so that described first conduction type source electrode is mixed
Completely cut off between miscellaneous district and described first conductive type of trap；It is that p-type embeds district that described first conduction type embeds district.
Horizontal dual pervasion field effect pipe the most according to claim 3, it is characterised in that:
Also including that the second conduction type embeds district, described second conduction type embeds district and is formed at described grid ditch
In place of the bottom land of groove structure and the handing-over of the second conductive type epitaxial layer；It is N that described second conduction type embeds district
Type embeds district.
8. according to the horizontal dual pervasion field effect pipe described in any one of claim 1～7, it is characterised in that institute
The material of the material and the second conductive type epitaxial layer of stating the first conductivity type substrate is silicon, carborundum, arsenic
Gallium, indium phosphide or germanium silicon.
9. according to the horizontal dual pervasion field effect pipe described in any one of claim 1～7, it is characterised in that institute
The material stating insulating barrier, field oxide and gate insulation layer is the oxide of silicon.
10. according to the horizontal dual pervasion field effect pipe described in any one of claim 1～7, it is characterised in that
Described conductive material is polysilicon.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054806.3A CN105990423A (en) | 2015-02-02 | 2015-02-02 | Transverse dual-field-effect tube |
| PCT/CN2016/072281 WO2016124086A1 (en) | 2015-02-02 | 2016-01-27 | Lateral double-diffused field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510054806.3A CN105990423A (en) | 2015-02-02 | 2015-02-02 | Transverse dual-field-effect tube |
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| CN105990423A true CN105990423A (en) | 2016-10-05 |
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| CN201510054806.3A Pending CN105990423A (en) | 2015-02-02 | 2015-02-02 | Transverse dual-field-effect tube |
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| WO (1) | WO2016124086A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108198853A (en) * | 2018-03-02 | 2018-06-22 | 成都信息工程大学 | A kind of binary channels varying doping LDMOS device and its manufacturing method |
| CN111933687A (en) * | 2020-07-07 | 2020-11-13 | 电子科技大学 | Lateral power device with high safety working area |
| CN112531026A (en) * | 2019-09-17 | 2021-03-19 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
| WO2022227858A1 (en) * | 2021-04-30 | 2022-11-03 | 无锡华润上华科技有限公司 | Diode and manufacturing method therefor, and semiconductor device |
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| DE102018113282A1 (en) * | 2017-06-05 | 2018-12-06 | Maxim Integrated Products, Inc. | LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS AND ASSOCIATED METHODS |
| CN109037337A (en) * | 2018-06-28 | 2018-12-18 | 华为技术有限公司 | A kind of power semiconductor and manufacturing method |
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| WO2016124086A1 (en) | 2016-08-11 |
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