CN105990118A - Semiconductor device, fabrication method thereof and electronic apparatus - Google Patents
Semiconductor device, fabrication method thereof and electronic apparatus Download PDFInfo
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- CN105990118A CN105990118A CN201510086377.8A CN201510086377A CN105990118A CN 105990118 A CN105990118 A CN 105990118A CN 201510086377 A CN201510086377 A CN 201510086377A CN 105990118 A CN105990118 A CN 105990118A
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 135
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 239000012298 atmosphere Substances 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000009434 installation Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 abstract description 3
- 238000006056 electrooxidation reaction Methods 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 229910003071 TaON Inorganic materials 0.000 description 6
- 229910010282 TiON Inorganic materials 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 229910016909 AlxOy Inorganic materials 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000002002 slurry Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004567 concrete Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000011513 prestressed concrete Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004490 TaAl Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron Ethoxysilane Chemical compound 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 230000003902 lesion Effects 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- XRFHCHCLSRSSPQ-UHFFFAOYSA-N strontium;oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Sr+2] XRFHCHCLSRSSPQ-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a semiconductor device, a fabrication method thereof and an electronic apparatus. The fabrication method includes the following steps that: a front end device which includes a semiconductor substrate, a gate trench formed on the semiconductor substrate and an interlayer dielectric layer which surrounds the gate trench is provided; a high-k dielectric layer is formed at the bottom and side wall of the gate trench; a work function metal layer is formed on the high-k dielectric layer; a metal gate material layer is formed on the work function metal layer so as to fill the gate trench and cover the interlayer dielectric layer; chemical mechanical polishing is carried out on the metal gate material layer and is stopped at the upper surface of the interlayer dielectric layer, so that a metal gate can be formed in the gate trench; and two times of high-temperature annealing process is carried out in an oxygen and nitrogen-containing atmosphere, so that the surfaces of the work function metal layer and the metal gate can be nitridized. According to the fabrication method of the invention, the problem of subsequent electrochemical corrosion is solved, so that the reliability and performance of the semiconductor device can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and
Manufacture method and electronic installation.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly by not
Break and reduce the size of IC-components, to improve what its speed realized.At present, pursue
The semi-conductor industry of high device density, high-performance and low cost has advanced to nanotechnology technique
Node, particularly when dimensions of semiconductor devices drops to lower Nano grade, semiconductor device
Preparation is limited by various physics limits.
When the size of semiconductor device drops to lower Nano grade, gate critical dimension in device
The most correspondingly reduce.Along with the arrival of 28nm manufacturing process, traditional gate dielectric layer constantly becomes
Thin, transistor leakage amount increases therewith, causes the problems such as semiconductor device power wastage.For solving
Certainly the problems referred to above, avoid high-temperature process simultaneously, and prior art provides one to utilize high k gold
Belong to grid and substitute the solution of polysilicon gate.
" post tensioned unbonded prestressed concrete " technique is the main technique forming high-k/metal gate at present.Use
" post tensioned unbonded prestressed concrete " technique forms the method for high-k/metal gate and includes: provide substrate, described substrate
On be formed with pseudo-grid structure and be positioned at the inter-level dielectric covering dummy gate structure in described substrate
Layer；Using dummy gate structure as stop-layer, described interlayer dielectric layer is carried out chemical machinery throwing
Light technique；Groove is formed after removing dummy gate structure；Finally described trench fill height k is situated between
Matter and metal level, to form high-k/metal gate.
In existing high-k/metal gate technique, aluminum diffusion always affect device reliability with
One of subject matter of performance, such as to time correlation dielectric breakdown (Time Dependent
Dielectric Breakdown, be called for short TDDB), Negative Bias Temperature Instability (Negative
Bias Temperature Instability, is called for short NBTI), positive bias temperature instability
Reliabilities such as (Positive Bias Temperature Instability are called for short PBTI) causes negatively
Impact, aluminum diffusion simultaneously also can affect the mobility of carrier, reduce the performance of device.
In 28nm high-k/metal gate technique, it is generally subjected to compared to NMOS, PMOS
More aluminum diffused lesion.Such as, in PMOS, Al can be diffused in TaN layer, from
And form TaNAl material, NMOS is being carried out CMP (cmp) period,
Owing to the pH value of ground slurry is between 2-3, therefore, at TaNAl and PMOS formed
Workfunction layers TiN between couple corrosion can be occurred to react.As shown in circle in Figure 1A
With in Figure 1B shown in arrow, near the part of TaN layer it is observed that corrosion in PMOS
Phenomenon.
Therefore, it is necessary to propose the manufacture method of a kind of new semiconductor device, existing to solve
The deficiency of technology.
Summary of the invention
For the deficiencies in the prior art, the present invention provides a kind of semiconductor device and preparation method thereof
And electronic installation.
According to an aspect of the present invention, it is provided that the manufacture method of a kind of semiconductor device, the party
Method includes:
Step S101: provide and include Semiconductor substrate, formed on the semiconductor substrate
Gate trench and surround the front-end devices of interlayer dielectric layer of described gate trench；
Step S102: form high k dielectric layer on the bottom and sidewall of described gate trench；
Step S103: form workfunction layers in described high k dielectric layer；
Step S104: form metal gate material layer in described workfunction layers, to fill out
Fill described gate trench and cover described interlayer dielectric layer；
Step S105: described metal gate material layer is carried out cmp, stops at
Described interlayer dielectric layer upper surface, to form metal gates in described gate trench；
Step S106: successively carry out twice high-temperature annealing process in oxygen-containing and nitrogen containing atmosphere,
To nitrogenize described workfunction layers and metal gates surface.
Alternatively, described metal gates is the metal gates of PMOS.
Alternatively, step S102 is further comprising the steps of: formed in described high k dielectric layer
Cover layer.
Alternatively, step S102 is further comprising the steps of: form diffusion on described cover layer
Barrier layer.
Alternatively, the material of described metal gates is Al.
Alternatively, the material of described workfunction layers is TiN.
Alternatively, the material of described diffusion impervious layer is TaN.
Alternatively, in step s 106, the temperature of high-temperature annealing process is higher than described work function
The depositing temperature of metal level.
According to a further aspect in the invention, it is provided that a kind of semiconductor device prepared according to said method
Part.
According to a further aspect in the invention, it is provided that a kind of electronics dress including above-mentioned semiconductor device
Put.
In sum, according to the manufacture method of the present invention, by the metal gate to PMOS
Pole material layer carries out cmp to be formed after metal gates, oxygen-containing and containing nitrogen
Atmosphere successively carries out twice high-temperature annealing process so that the TaN/TiN nitrogen in gate trench sidewalls
Turn to TaON or TiON, and the aluminum surface of PMOS is formed as AlxOyNzNitrogen oxidation
Thing.The thin film of nitridation will stop the generation of couple corrosion problem subsequently, thus improve and partly lead
The reliability of body device and performance.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A shows the scanning electricity of the high-k/metal gate of the technique making according to prior art
Mirror is intended to；
Figure 1B shows the structure of the high-k/metal gate of the technique making according to prior art
Sectional view；
Fig. 2 A to 2E is the phase of the manufacture method of the semiconductor device according to the embodiment of the present invention
Close the sectional view of the structure that step is formed；
Fig. 3 is that the high-k/metal gate that the technique according to prior art makes is real with according to the present invention
The scanning electron microscope of the high-k/metal gate that the manufacture method of the semiconductor device executing example makes compares
Schematic diagram；
Fig. 4 is the schematic stream of the manufacture method of the semiconductor device according to the embodiment of the present invention
Cheng Tu.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " connect
To " or " being coupled to " other element or during layer, its can directly on other element or layer,
Adjacent thereto, be connected or coupled to other element or layer, or can exist element between two parties or
Layer.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " directly connect
Receive " or " being directly coupled to " other element or during layer, the most there is not element between two parties or layer.
Although it should be understood that and term first, second, third, etc. can being used to describe various element, portion
Part, district, floor and/or part, these elements, parts, district, floor and/or part the most should be by
These terms limit.These terms are used merely to distinguish an element, parts, district, floor or portion
Divide and another element, parts, district, floor or part.Therefore, without departing from present invention teach that
Under, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ...
Under ", " ... on ", " above " etc., here can describe for convenience and be used
Thus shown in figure a element or feature and other element or the relation of feature are described.Should
Understanding, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and grasping
The different orientation of the device in work.Such as, if the device upset in accompanying drawing, then, describe
To take for " below other element " or " under it " or " under it " element or feature
To for other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, in order to the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention describes in detail
As follows, but in addition to these describe in detail, the present invention can also have other embodiments.
The embodiment provides the manufacture method of a kind of semiconductor device.Below, reference
Fig. 2 A to Fig. 2 E and Fig. 4 describes the manufacturer of the semiconductor device of the embodiment of the present invention
The detailed step of one illustrative methods of method.Wherein, Fig. 2 A to 2E is real according to the present invention
The sectional view of the structure that the correlation step of the manufacture method executing the semiconductor device of example is formed；Fig. 4
Indicative flowchart for the manufacture method of the semiconductor device according to the embodiment of the present invention.
The manufacture method of the semiconductor device of the present embodiment, comprises the steps:
Step A1: provide and include Semiconductor substrate 100, in described Semiconductor substrate 100
Before the gate trench 102 formed and the interlayer dielectric layer 103 surrounding described gate trench 102
End-apparatus part, as shown in Figure 2 A.
In the present embodiment, front-end devices refers to form certain assembly the most on a semiconductor substrate
But not yet it is finally completed the device of the manufacture of whole semiconductor device.Certainly, the tool of front-end devices
Body structure is not limited with Fig. 2 A, it is also possible to include other assemblies.
Semiconductor substrate 100 can be monocrystalline substrate, silicon-on-insulator (SOI) substrate,
Stacking SiGe (S-SiGeOI) lining on stacking silicon (SSOI) substrate, insulator on insulator
The end, germanium on insulator SiClx (SiGeOI) substrate and germanium on insulator (GeOI) substrate
In at least one.Semiconductor substrate 100 could be formed with isolation structure, PMOS and
NMOS, isolation structure can be shallow trench isolation (STI) structure or selective oxidation silicon
(LOCOS) isolation structure, described Semiconductor substrate 100 can be divided into NMOS by isolation structure
Region and PMOS area.Semiconductor substrate 100 can also comprise other structures and device
Part, to put it more simply, omitted in Tu Shi.Interlayer dielectric layer 103 can be silicon oxide layer, bag
Include and utilize thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma
(HDP) manufacturing process formed the material layer having doped or undoped silicon oxide, such as without
Silica glass (USG), phosphorosilicate glass (PSG) or the boron-phosphorosilicate glass (BPSG) of doping.Additionally,
Interlayer dielectric layer 103 can also be the spin cloth of coating-type glass of doped with boron or Doping Phosphorus
The tetraethoxysilane (PTEOS) of (spin-on-glass, SOG), Doping Phosphorus or the four of doped with boron
Ethoxysilane (BTEOS).Gate trench 102 can be formed by dummy gate technique.
Step A2: in PMOS area, shape on the bottom and sidewall of gate trench 102
Become high k dielectric layer 104, as shown in Figure 2 B.
The PMOS part of CMOS and the metal gate structure needs of NMOS part have not
Same work function, therefore, the metal gate structure of the two is formed respectively.In the present embodiment
Introduce is each step forming metal gate structure in PMOS part.
The k value (dielectric constant) of high k dielectric layer 104 is usually more than 3.9, and it constitutes material
Material include hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconium oxide, zirconium silicon oxide,
Titanium oxide, tantalum oxide, strontium barium oxide titanium, Barium monoxide titanium, strontium oxide titanium, aluminium oxide etc., relatively
It is hafnium oxide, zirconium oxide or aluminium oxide goodly.CVD, ALD or PVD can be used
High k dielectric layer 104 is formed Deng the technique being suitable for.The thickness range of high k dielectric layer 104 is permissible
Being 10 angstroms to 30 angstroms, the numerical value of above-mentioned thickness range is only exemplarily, also can be according to reality
Technique is adjusted.
Alternatively, step A2 is further comprising the steps of: before forming high k dielectric layer 104,
The bottom and sidewall of gate trench 102 are formed boundary layer.The constituent material of boundary layer includes
Si oxide (SiOx), the effect forming boundary layer is to improve high k dielectric layer 104 and partly lead
Interfacial characteristics between body substrate 100.Boundary layer can be thermal oxide layer, nitrogen oxide
Layer, chemical oxide layer or other thin layers being suitable for.Can use thermal oxide, CVD,
The technique that ALD or PVD etc. are suitable for forms boundary layer.The thickness range of boundary layer can be
5 angstroms to 10 angstroms, the numerical value of above-mentioned thickness range is only exemplarily, also can be according to actual work
Skill is adjusted.
Alternatively, step A2 is further comprising the steps of: shape in described high k dielectric layer 104
Become cover layer 105.The material of cover layer 105 can be La2O3、Al2O3、Ga2O3、In2O3、
MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other are fitted
The thin layer closed.The process deposits shape that CVD, ALD or PVD etc. are suitable for can be used
Become cover layer 105, it is preferred that the method for formation of deposits cover layer 105 is atomic layer deposition method.
In the present embodiment, the material of the most described cover layer 105 is TiN.The cover layer 105 of deposition
Thickness range can be 5 angstroms to 30 angstroms, the numerical value of above-mentioned thickness range is only exemplarily,
Also can be adjusted according to actual process.
Alternatively, step A2 is further comprising the steps of: is formed on described cover layer 105 and expands
Dissipate barrier layer 106.The material of diffusion impervious layer 106 can be chosen as TaN, Ta, TaAl or
Other thin layers being suitable for of person.The work that CVD, ALD or PVD etc. are suitable for can be used
Skill forms barrier layer.The thickness range of diffusion impervious layer 106 can be 5 angstroms to 40 angstroms, on
The numerical value stating thickness range is only exemplarily, also can be adjusted according to actual process.At this
In embodiment, the material of described diffusion impervious layer 106 is TaN.
Step A3: form workfunction layers 107 in high k dielectric layer 104, such as Fig. 2 C
Shown in.
P-type workfunction layers 107, P is formed on barrier layer 106 in PMOS area
Type workfunction layers 107 is PMOS workfunction metal tunable layer, p-type workfunction layers
(PWF) material can be chosen as but be not limited to TixN1-x, TaC, MoN, TaN or
Other thin layers being suitable for.In the present embodiment, the material of described workfunction layers 107 is
TiN.The technique that CVD, ALD or PVD etc. can be used to be suitable for forms p-type work function
Metal level.The thickness range of p-type workfunction layers can be 10 angstroms to 580 angstroms, above-mentioned
The numerical value of thickness range is only exemplarily, also can be adjusted according to actual process.
Step A4: form metal gate material layer 108 in workfunction layers 107, with
Fill gate trench 102 and cover interlayer dielectric layer 103, as shown in Figure 2 D.
Workfunction layers 107 is formed and fills gate trench 102 and cover interlayer dielectric layer
The metal gate material layer 108 of 103, the end face of metal gate material layer 108 is situated between higher than interlayer
Electric layer 103.Exemplarily, metal gate material can be chosen as but be not limited to Al, W or
Other thin layers being suitable for of person.In the present embodiment, the material of metal gate material layer 108 is
Al.The technique that CVD, ALD or PVD etc. can be used to be suitable for forms metal gates.
Step A5: metal gate material layer 108 is carried out cmp, stops at layer
Between dielectric layer 103 upper surface, to form metal gates 109, as shown in Figure 2 E.
Metal gate material layer 108 is carried out cmp, stops at interlayer dielectric layer
103 upper surfaces, at this moment, the metal gate material not being milled away is filled up completely with gate trench
102, the metal gate material in gate trench 102 defines metal gates 109.
Step A6: successively carry out twice high-temperature annealing process in oxygen-containing and nitrogen containing atmosphere,
With nitridation workfunction layers 107 and metal gates 109 surface.
Exemplarily, at oxygen-containing (such as, O2Atmosphere) and nitrogenous (such as, NH3With
N2Atmosphere) atmosphere successively carries out twice high-temperature annealing process, to nitrogenize workfunction layers
107 and/or diffusion impervious layer 106, and be formed as Al on the aluminium gate surface of PMOSxOyNz
Nitrogen oxides.Concrete process is the process of nitridation after an initial oxidation.Move back at twice high temperature
During fire, TiN initial oxidation is that TiON nitrogenizes as TiON, TaN initial oxidation again is TaON
Nitridation is Al for TaON, Al initial oxidation again203Nitridation is Al againxOyNz.Exemplarily,
Once anneal and carry out, such as at O in oxygen-containing atmosphere2Atmosphere is carried out, the technique ginseng of annealing
Number is: temperature 350 DEG C～450 DEG C, time 3min～6min, gas flow rate 400
Sccm～1000sccm, pressure 1torr～5torr；Second time annealing is carried out in nitrogen containing atmosphere,
Such as at NH3And N2Carrying out in atmosphere, the technological parameter of annealing is: temperature 350 DEG C～450 DEG C,
Time 3min～6min, gas flow rate 400sccm～1000sccm, pressure 1torr～5torr.
After this high-temperature annealing process, on sidewall formed TaN/TiN by nitridation be TaON or
TiON, and the aluminium gate surface of PMOS is formed as AlxOyNzNitrogen oxides, nitridation
Thin film by stop subsequently due to NMOS is being carried out CMP (cmp) period
The generation of the couple corrosion problem caused by ground slurry (its pH value is between 2 to 3).
Alternatively, the temperature of high-temperature annealing process is higher than the depositing temperature of described workfunction layers, with
Stress is released completely.
After having carried out above-mentioned steps, can continue to be formed metal gate in NMOS area
Pole.Due in the manufacture method of the present invention, by the metal gate material to PMOS
Layer carries out cmp to be formed after metal gates, oxygen-containing and containing atmosphere in successively
Carry out twice high-temperature annealing process so that the TaN/TiN nitridation in gate trench sidewalls is
TaON or TiON, and the aluminium gate surface of PMOS is formed as AlxOyNzNitrogen oxidation
Thing.Therefore, in subsequent technique, the thin film of nitridation will stop subsequently due to NMOS
Carry out CMP (cmp) period by ground slurry (its pH value is between 2 to 3)
The generation of the couple corrosion problem caused, thus improve reliability and the property of semiconductor device
Energy.
Fig. 3 shows high-k/metal gate that technique according to prior art makes with according to this
The scanning electricity of the high-k/metal gate that the manufacture method of the semiconductor device of inventive embodiments makes
Mirror compares schematic diagram, and wherein the figure on the left side is the high k metal that the technique according to prior art makes
The scanning electron microscope (SEM) photograph of grid, the figure on the right is the system of semiconductor device according to embodiments of the present invention
Make the scanning electron microscope (SEM) photograph of the high-k/metal gate that method makes.From figure 3, it can be seen that pass through
Scanning electron microscope, it can be observed that the sidewall nitridation of 60 angstroms, the thin film of nitridation will stop subsequently
The generation of couple corrosion problem.
Fig. 4 shows the manufacture method of a kind of semiconductor device that the embodiment of the present invention provides
Indicative flowchart, for schematically illustrating the typical process of this manufacture method.
Step S101: provide and include Semiconductor substrate, formed on the semiconductor substrate
Gate trench and surround the front-end devices of interlayer dielectric layer of described gate trench；
Step S102: form high k dielectric layer on the bottom and sidewall of described gate trench；
Step S103: form workfunction layers in described high k dielectric layer；
Step S104: form metal gate material layer in described workfunction layers, to fill out
Fill described gate trench and cover described interlayer dielectric layer；
Step S105: described metal gate material layer is carried out cmp, stops at
Described interlayer dielectric layer upper surface, to form metal gates in described gate trench；
Step S106: successively carry out twice high-temperature annealing process in oxygen-containing and nitrogen containing atmosphere,
To nitrogenize described workfunction layers and metal gates surface.
Embodiments of the invention provide a kind of semiconductor device, and it uses described in above-described embodiment
The manufacture method of semiconductor device prepares.
The semiconductor device prepared by method described in the embodiment of the present invention, by right
The metal gate material layer of PMOS carries out cmp to be formed after metal gates,
Oxygen-containing and successively carry out twice high-temperature annealing process containing in atmosphere so that in gate trench sidewalls
TaN/TiN nitridation for TaON or TiON, and the aluminium gate surface of PMOS is formed as
AlxOyNzNitrogen oxides, the thin film of nitridation will stop the generation of couple corrosion problem subsequently,
Thus improve reliability and the performance of semiconductor device.
Embodiments of the invention provide a kind of electronic installation, it include electronic building brick and with this electricity
The semiconductor device of sub-component electrical connection.Wherein, described semiconductor device is above-mentioned semiconductor device
Part.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, on
Net basis, game machine, television set, VCD, DVD, navigator, photographing unit, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment, it is possible to include for any
The intermediate products of this semiconductor device.Wherein, this electronic building brick can be any feasible assembly,
It is not defined at this.
The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus
There is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, described method includes:
Step S101: provide and include Semiconductor substrate, formed on the semiconductor substrate
Gate trench and surround the front-end devices of interlayer dielectric layer of described gate trench；
Step S102: form high k dielectric layer on the bottom and sidewall of described gate trench；
Step S103: form workfunction layers in described high k dielectric layer；
Step S104: form metal gate material layer in described workfunction layers, to fill out
Fill described gate trench and cover described interlayer dielectric layer；
Step S105: described metal gate material layer is carried out cmp, stops at
Described interlayer dielectric layer upper surface, to form metal gates in described gate trench；
Step S106: successively carry out twice high-temperature annealing process in oxygen-containing and nitrogen containing atmosphere,
To nitrogenize described workfunction layers and metal gates surface.
Method the most according to claim 1, it is characterised in that described metal gates is
The metal gates of PMOS.
Method the most according to claim 1, it is characterised in that step S102 also includes
Following steps: form cover layer in described high k dielectric layer.
Method the most according to claim 3, it is characterised in that step S102 also includes
Following steps: form diffusion impervious layer on described cover layer.
Method the most according to claim 1, it is characterised in that described metal gates
Material is Al.
Method the most according to claim 1, it is characterised in that described workfunction metal
The material of layer is TiN.
Method the most according to claim 4, it is characterised in that described diffusion impervious layer
Material be TaN.
Method the most according to claim 1, it is characterised in that in step s 106,
The temperature of high-temperature annealing process is higher than the depositing temperature of described workfunction layers.
9. the semiconductor device prepared according to the method one of claim 1-8 Suo Shu.
10. an electronic installation, including semiconductor device according to claim 9.
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| CN108630608A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110349851A (en) * | 2018-04-08 | 2019-10-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacturing method |
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| CN102437032A (en) * | 2010-09-29 | 2012-05-02 | 中国科学院微电子研究所 | Method for manufacturing metal gate in gate-last process |
| CN103545256A (en) * | 2012-07-12 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming CMOS (complementary metal oxide semiconductor) device |
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| US20110156166A1 (en) * | 2009-12-31 | 2011-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | High Temperature Anneal for Aluminum Surface Protection |
| CN102437032A (en) * | 2010-09-29 | 2012-05-02 | 中国科学院微电子研究所 | Method for manufacturing metal gate in gate-last process |
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Application publication date: 20161005 |