CN105958951B

CN105958951B - Transimpedance circuit

Info

Publication number: CN105958951B
Application number: CN201510524953.2A
Authority: CN
Inventors: 常次幸男
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2015-03-09
Filing date: 2015-08-25
Publication date: 2020-02-14
Anticipated expiration: 2035-08-25
Also published as: JP2016167703A; US9837969B2; JP6461652B2; US20160268975A1; CN105958951A

Abstract

According to one embodiment, a transimpedance circuit includes: a transimpedance amplifier that converts a current signal into a voltage signal; a reference voltage generating circuit that generates a reference voltage signal; and a comparator that generates a pulse signal corresponding to the current signal based on the voltage levels of the voltage signal and the reference voltage signal. The transimpedance amplifier has: a first transistor amplifying the current signal; a voltage converter that voltage-converts the current signal amplified by the first transistor; and a bypass circuit that bypasses the current signal when the current signal flowing through the control terminal of the first transistor exceeds a predetermined value.

Description

Transimpedance circuit

Reference to related applications

This application enjoys priority based on Japanese patent application No. 2015-046300 (application date: 2015 03/09). The present application is incorporated by reference in its entirety.

Technical Field

The embodiments described herein generally relate to a transimpedance circuit that converts a current signal into a voltage signal.

Background

The photodiode outputs a current signal corresponding to the received optical signal. The current signal is converted into a voltage signal in the transimpedance circuit, and then a pulse signal is generated. The more the amount of the optical signal received by the photodiode, the more the current signal is output.

However, if the current signal output from the photodiode becomes large, the primary transistor provided in the transimpedance circuit may be saturated. If the primary transistor is saturated, the voltage signal is distorted, and the resulting pulse signal is also distorted.

Disclosure of Invention

Embodiments provide a transimpedance circuit capable of suppressing distortion of a pulse signal even if a current signal is large.

According to one embodiment, a transimpedance circuit includes: a transimpedance amplifier that converts a current signal into a voltage signal; a reference voltage output circuit that generates a reference voltage signal; a comparator that generates a pulse signal corresponding to the current signal based on voltage levels of the voltage signal and the reference voltage signal, wherein the transimpedance amplifier includes: a first transistor for amplifying the current signal; a voltage converter for voltage-converting the current signal amplified by the first transistor; and a bypass circuit configured to bypass the current signal when the current signal flowing through the control terminal of the first transistor exceeds a predetermined value.

According to the transimpedance circuit having the above configuration, a transimpedance circuit capable of suppressing distortion of a pulse signal can be provided.

Drawings

Fig. 1 is a block diagram of a transimpedance circuit 1 according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing an example of the internal configuration of the transimpedance amplifier 2 of fig. 1.

Fig. 3 is a voltage waveform diagram of each part in the transimpedance circuit 1 of fig. 1 and 2.

Fig. 4 is a voltage waveform diagram of each part in transimpedance circuit 1 of one comparative example in which bypass circuit 13 of fig. 2 is not provided.

Fig. 5 is a circuit diagram showing an example of the circuit configuration of the emitter-grounded primary transistor 11.

Fig. 6 is a circuit diagram showing an example in which the primary transistor 11 is of a drain-grounded type.

Fig. 7 is a circuit diagram showing an example in which the primary transistor 11 is of a source-grounded type.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the description will be given mainly on the characteristic configuration and operation within the transimpedance circuit, but there is a configuration and operation in the transimpedance circuit that is not described below. However, these omitted configurations and operations are also included in the scope of the present embodiment.

Fig. 1 is a block diagram of a transimpedance circuit 1 according to an embodiment of the present invention. The transimpedance circuit 1 of fig. 1 includes a transimpedance amplifier (TIA)2, a reference voltage generation circuit (dummy circuit) 3, a current source 4, a peak hold circuit 5, and a comparator 6.

The transimpedance amplifier 2 converts the current signal Ipd into a voltage signal Vpd 1. In general, the transimpedance amplifier 2 converts a current signal Ipd output from a light-receiving element such as a photodiode into a voltage signal Vpd 1. The light receiving element is incorporated in the transimpedance amplifier 2 or externally mounted. The light receiving element generates and outputs a current signal Ipd having a magnitude corresponding to the light intensity of the received optical signal.

The reference voltage generation circuit 3 has substantially the same circuit configuration as the transimpedance amplifier 2, and the reference voltage generation circuit 3 generates a reference voltage signal Vdm 1. The reference voltage generation circuit 3 is provided to be less susceptible to environmental noise such as common mode noise, variations in characteristics of circuit elements in the transimpedance amplifier 2, and the like. More specifically, the voltage signal Vpd1 output from the transimpedance amplifier 2 is about several tens mV and is susceptible to environmental noise, variations in element characteristics, and the like. Therefore, by comparing the voltage signal Vpd1 output from the transimpedance amplifier 2 with the reference voltage signal Vdm1 output from the reference voltage generation circuit 3 configured by the same circuit as the transimpedance amplifier 2, the amount of fluctuation due to the environmental noise and the like included in both signals is cancelled.

The current source 4 generates a reference current shared by the transimpedance amplifier 2 and the reference voltage generation circuit 3. Although the specific configuration of the current source 4 is not limited, it is preferable to adjust the current supplied from the current source 4.

The peak hold circuit 5 generates an intermediate voltage level signal using the voltage signal Vpd1 output from the transimpedance amplifier 2 and the reference voltage signal Vdm1 output from the reference voltage generation circuit 3. Such an intermediate level signal is generated because the signal distortion of the intermediate voltage level is minimal. The peak hold circuit 5 incorporates an offset adjustment circuit. The bias adjustment circuit outputs a signal obtained by adding a predetermined bias voltage to the new intermediate voltage level signal as a final reference voltage signal Vatc so that the voltage signal Vpd1 when the light receiving element in the transimpedance amplifier 2 does not receive the optical signal is not erroneously determined to be larger than the reference voltage signal.

The reference voltage generating circuit 3 and the peak holding circuit 5 are combined to be a reference voltage output circuit 7. The peak hold circuit 5 may be omitted in some cases, and in this case, the reference voltage output circuit 7 is equivalent to the reference voltage generation circuit 3.

The comparator 6 generates a pulse signal Vout of 2 value indicating whether or not the voltage signal Vpd1 output from the transimpedance amplifier 2 exceeds the reference voltage signal Vatc held by the peak hold circuit 5. Here, the comparator 6 may compare the voltage signal Vpd1 with the reference voltage signal Vatc, or may compare voltage signals obtained by relatively changing both the voltage signal Vpd1 and the reference voltage signal Vatc with each other. That is, the comparator 6 compares the voltage signal associated with the voltage signal Vpd1 with the voltage signal associated with the reference voltage signal Vatc, and generates the pulse signal Vout indicating the comparison result.

Fig. 2 is a circuit diagram showing an example of the internal configuration of the transimpedance amplifier 2 of fig. 1. In the following, an example in which the built-in or externally-mounted optical element is the photodiode 10 will be described. The transimpedance amplifier 2 of fig. 2 has: a first transistor (first transistor) 11 that amplifies a current signal Ipd from the photodiode 10, a voltage converter 12 that voltage-converts the current signal amplified by the first transistor 11, a bypass circuit 13 that bypasses the current signal Ipd if a current flowing through a base (control terminal) of the first transistor 11 exceeds a predetermined value, and an inverting amplifier 15 that inverts and amplifies the voltage signal output from the voltage converter 12.

Each transistor in the transimpedance amplifier 2 of fig. 2 is a bipolar transistor. For example, the primary transistor 11 has 2 npn transistors Q1, Q2 that are darlington connected. The base of the transistor Q1 is connected to the anode of the photodiode 10. The collector of the transistor Q1 is connected to the power supply voltage node Vcc via the resistor element R1. The emitter of the transistor Q1 is connected to the ground node Vss via the resistor element R2. Further, the emitter of the transistor Q1 is connected to the base of a transistor Q2 connected to the transistor Q1. The emitter of transistor Q2 is connected to ground.

The bypass circuit 13 is connected between the collector of the transistor Q2 and the anode of the photodiode 10. The bypass circuit 13 includes an npn transistor (second transistor) Q3 diode-connected and a resistor element R3 connected in series to the transistor Q3. The resistor R3 is a current limiting resistor, and as will be described later, when the transimpedance amplifier 2 is formed of a MOS transistor, the resistor R3 can be omitted.

The base and the collector of the transistor Q3 are connected to the anode of the photodiode 10, the emitter of the transistor Q3 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the collector of the transistor Q2.

When the photodiode 10 is mounted outside the transimpedance amplifier 2, a resistance element and a capacitor are connected in series in accordance with the electrical characteristics of the photodiode 10, instead of a dummy photodiode, in the reference voltage generation circuit 3. The resistance value of the resistance element in this case is set to the extent of the parasitic resistance of the photodiode 10, and the capacitance of the capacitor is set to the extent of the junction capacitance of the photodiode 10.

A level shifter 14 is connected between the collector of the transistor Q2 and the current source 4 shown in fig. 1. The level shifter 14 is a circuit in which an npn transistor Q4 diode-connected and a resistance element R5 are connected in series. One end side of resistor element R5 is connected to current source 4 and the base of npn transistor Q5. From the viewpoint of high-speed operation of the transistor Q5, it is preferable that the amplitude change of the base voltage of the transistor Q5 is small. Therefore, the diode-connected transistor Q4 is connected between the other end of the resistor element R5 and the collector of the transistor Q2. This raises the base voltage of the transistor Q5, and enables the transistor Q5 to operate at high speed. The level shifter 14 is not essential and may be omitted in some cases.

A capacitor C2 and a resistance element R6 are connected in parallel between the anode of the photodiode 10 and the emitter (node z1) of the transistor Q5. Most of the current signal Ipd output from the photodiode 10 flows through the resistance element R6. Therefore, the resistor element R6 functions as a voltage converter 12 that converts the voltage of the current signal Ipd output from the photodiode 10, and a voltage signal obtained by voltage-converting the current signal appears at the node z 1. The capacitor C2 connected in parallel with the resistance element R6 is a phase compensation capacitance for realizing oscillation prevention of the transimpedance amplifier 2.

On the rear stage side of the voltage converter 12, an inverting amplifier 15 and a current source 16 are provided. The inverting amplifier 15 includes npn transistors Q6 to Q8, resistance elements R7 and R8 that determine the gain of the inverting amplifier 15, resistance elements R9 to R15, a diode-connected transistor Q9, and a capacitor C3. The inverting amplifier 15 generates a signal Vpd1 obtained by inverting and amplifying the voltage signal at the node z1 by the gain of R8/R7.

Next, a circuit operation of the transimpedance amplifier 2 of fig. 2 will be described. When the photodiode 10 receives the optical signal, a current signal Ipd corresponding to the optical signal is output from the photodiode 10. In response to the current signal Ipd, an emitter current flows through the transistor Q1, the base voltage of the transistor Q2 becomes high, and the collector voltage of the transistor Q2 becomes low. Since a constant current flows from the current source 4 to the collector of the transistor Q2, when the collector voltage of the transistor Q2 decreases, the base voltage of the transistor Q5 also decreases, and accordingly, the voltage of the emitter (node z1) of the transistor Q5 also decreases. Therefore, most of the current signal Ipd from the photodiode 10 flows through the resistance element R6, and negative feedback control is performed in which the increase in the base voltage of the transistor Q1 is suppressed. When the current value of the current signal Ipd increases to a value exceeding the negative feedback control and the collector voltage of the transistor Q2 (the voltage at the node x 1) decreases to a predetermined voltage level, the current signal Ipd from the photodiode 10 flows into the bypass circuit 13, and the base current of the transistor Q1 decreases. Therefore, the transistors Q1, Q2 as the primary transistor 11 are prevented from becoming saturated, and the voltage signal Vpd1 and the pulse signal are not distorted.

As described above, the diode-connected transistor Q3 in the bypass circuit 13 monitors the collector voltage of the transistor Q2, and when the collector voltage of the transistor Q2 falls to a predetermined voltage level, bypasses the current signal Ipd from the photodiode 10 to the bypass circuit 13 side.

A diode-connected transistor Q4 and a resistor element R5 constituting the level shifter 14 are connected in series between the collector of the transistor Q2 and the current source 4. Thus, the collector voltage of the transistor Q2 is reduced by R5 × I4+ VBE compared to the base voltage of the transistor Q5. Here, R5 is a resistance value of the resistor element R5, I4 is a collector-emitter current of the transistor Q4, and VBE is a base-emitter voltage of the transistor Q4. In the following description, the base-emitter voltages of all transistors in the transimpedance amplifier 2 are the same and are set to the voltage VBE. In this case, the collector voltage of the transistor Q2 (the voltage at node x 1) varies from 2 VBE-R5 × I4 to VBE, and the amplitude at node x1 is VBE-R5 × I4. On the other hand, if the level shifter 14 is not provided, the amplitude of the node x1 is 2VBE from 3VBE to VBE, and the voltage amplitude of the node x1 can be further suppressed when the level shifter 14 is provided. Therefore, by providing the level shifter 14, the recovery time of the transistor Q5 can be shortened.

The inverting amplifier 15 disposed on the rear stage side in the transimpedance amplifier 2 inverts and amplifies the voltage signal converted by the voltage converter 12 by a gain obtained by dividing the resistance value of the resistance element R8 by the resistance value of the resistance element R7. The voltage converter 12 inverts the current signal to convert the current signal into a voltage signal, and further inverts the current signal in the inverting amplifier 15 to generate a voltage signal Vpd1 having the same logic as the current signal Ipd of the photodiode 10.

The reference voltage generation circuit 3 is configured by the same circuit as the transimpedance amplifier 2, but the photodiode in the reference voltage generation circuit 3 does not receive an optical signal. Therefore, the reference voltage generation circuit 3 generates the reference voltage signal Vdm1 corresponding to the low level. The reference voltage signal Vdm1 includes environmental noise such as common mode noise and noise caused by variations in characteristics of circuit elements in the reference voltage generating circuit 3.

Fig. 3 is a voltage waveform diagram of each part in transimpedance circuit 1 in fig. 1 and 2, and fig. 4 is a voltage waveform diagram of each part in transimpedance circuit 1 of one comparative example in which bypass circuit 13 in fig. 2 is not provided.

A waveform w1 in fig. 3 and 4 is a collector voltage waveform of the transistor Q2 in the transimpedance amplifier 2 in fig. 2, a waveform w2 is a waveform of the current signal Ipd output from the photodiode 10, and a waveform w3 is a waveform of the pulse signal Vout output from the transimpedance circuit 1.

If the bypass circuit 13 is not provided in the transimpedance amplifier 2, the transistor Q2 in fig. 2 is saturated, and the collector voltage of the transistor Q2 is in a low voltage level state (waveform w1 in fig. 4) even if the current signal Ipd is not output from the photodiode 10. On the other hand, when the bypass circuit 13 of the present embodiment is provided, the current signal Ipd from the photodiode 10 flows to the bypass circuit 13 when the collector voltage of the transistor Q2 becomes low, and therefore the transistor Q2 becomes unsaturated. Therefore, as shown by the waveform w1 in fig. 3, the collector voltage of the transistor Q3 also changes in synchronization with the current signal Ipd from the photodiode 10, and the followability to the current signal Ipd improves. In the present embodiment, the waveform w3 of the pulse signal output from the transimpedance circuit 1 is steep. The waveform w3 is steep because the bypass circuit 13 and the level shifter 14 are provided. In a comparative example, the rising edge and the falling edge of the waveform w3 of the pulse signal Vout become not steep, and the logic of the pulse signal Vout also becomes abnormal.

In fig. 3 and 4, a waveform w4 is a waveform of the output voltage Vpd1 of the transimpedance amplifier 2, a waveform w5 is a waveform of the output voltage Vdm1 of the reference voltage generation circuit 3, a waveform w6 is a waveform of the intermediate voltage Vdiv generated in the peak hold circuit 5, and a waveform w7 is a waveform of the voltage Varc held in the peak hold circuit 5. All of the waveforms w4 to w7 in the present embodiment have voltage levels that change in synchronization with changes in the current value of the current signal Ipd output from the photodiode 10, and have small waveform distortion. On the other hand, the waveforms w4 to w7 of the comparative example are not correctly synchronized with the change in the current value of the current signal Ipd, and the waveform distortion is also large.

In the transimpedance amplifier 2 of fig. 2, the primary transistor 11 is of a collector-grounded type, but may be of an emitter-grounded type. Fig. 5 is a circuit diagram showing an example of the circuit configuration of the emitter-grounded primary transistor 11. The primary transistor 11 of fig. 5 is one of npn transistors Q1. Transistor Q1 has its emitter grounded and its collector connected to current source 4 via diode-connected npn transistor Q4.

The bypass circuit 13 of fig. 5 has a diode 20 having a forward voltage Vf less than 0.6V (e.g., around 0.3V). The diode 20 of fig. 5 is a schottky barrier diode 20 using a schottky barrier generated by bonding a metal and a semiconductor. The schottky barrier diode 20 has a feature of small forward voltage drop and fast switching speed. In the bypass circuit 13 of fig. 5, the resistor element R3 necessary in fig. 2 can be omitted.

The anode of the diode 20 in fig. 5 is connected to the gate of the transistor and the anode of the photodiode 10, and the cathode of the diode 20 is connected to the collector of the transistor Q1.

In fig. 2 and 5, although an example is shown in which a bipolar transistor is used as a transistor in the transimpedance amplifier 2, a MOS transistor may be used.

Fig. 6 and 7 are circuit diagrams showing an example in which a MOS transistor is used as the primary transistor 11, fig. 6 is a circuit diagram showing an example of a drain-grounded type, and fig. 7 is a circuit diagram showing an example of a source-grounded type.

In fig. 6 and 7, NMOS transistors are used as the transistors in the transimpedance amplifier 2. In the following, each NMOS transistor is simply referred to as a transistor. The primary transistor 11 of fig. 6 includes darlington-connected transistors Q21 and Q22. The transistor Q21 corresponds to the transistor Q1 of fig. 2, and the transistor Q22 corresponds to the transistor Q2 of fig. 2.

The bypass circuit 13 in fig. 6 and 7 is configured only by the diode-connected transistor Q23, and the current limiting resistor element R3 in fig. 2 is omitted. This is because the current flowing through the MOS transistor can be arbitrarily adjusted by the ratio of the gate width W to the gate length L, and therefore, the current can be limited even if the resistance element is not provided.

In addition, the transistor Q23 in the bypass circuit 13 has a lower threshold voltage than the primary transistor 11. This makes it easier for more current to flow through the bypass circuit 13.

As described above, in the present embodiment, since the bypass circuit 13 is provided to bypass the current signal Ipd from the light receiving element flowing to the base and gate of the primary transistor 11 in the transimpedance amplifier 2, the primary transistor 11 is not saturated, and distortion of the pulse signal output from the transimpedance circuit 1 can be suppressed.

Further, by providing the level shifter 14 on the output side of the primary transistor 11 in addition to the bypass circuit 13, the recovery time when the primary transistor 11 is turned off can be shortened, the operation of the inverting amplifier 15 on the subsequent stage side can be speeded up, and the pulse signal can be made steeper.

Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in other various manners, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Claims

1. A transimpedance circuit is provided with:

a transimpedance amplifier that converts a current signal into a voltage signal;

a reference voltage output circuit that generates a reference voltage signal;

a comparator for generating a pulse signal corresponding to the current signal based on the voltage levels of the voltage signal and the reference voltage signal,

the transimpedance amplifier includes:

a first transistor for amplifying the current signal;

a voltage converter for voltage-converting the current signal amplified by the first transistor;

and a bypass circuit configured to bypass the current signal when the current signal flowing through the control terminal of the first transistor exceeds a predetermined value.

2. The transimpedance circuit according to claim 1, wherein,

the bypass circuit has a diode-connected second transistor.

3. The transimpedance circuit according to claim 2, wherein,

the bypass circuit includes a resistor element connected in series with the diode-connected second transistor.

4. The transimpedance circuit according to claim 3, wherein,

the first transistor and the diode-connected transistor are bipolar transistors.

5. The transimpedance circuit according to claim 2 or 3, wherein,

the first transistor and the diode-connected transistor are MOS transistors,

the diode-connected transistor has a threshold voltage lower than a threshold voltage of the first transistor.

6. The transimpedance circuit according to claim 1, wherein,

the bypass circuit has a diode with a forward voltage of less than 0.6V.

7. The transimpedance circuit according to any one of claims 1 to 4 and 6, wherein,

comprises a light receiving element for outputting a current signal corresponding to a received optical signal,

the bypass circuit is connected between the anode of the light receiving element and the control terminal of the first transistor.