CN105915219B - Analog-digital conversion circuit - Google Patents
Analog-digital conversion circuit Download PDFInfo
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- CN105915219B CN105915219B CN201610217816.9A CN201610217816A CN105915219B CN 105915219 B CN105915219 B CN 105915219B CN 201610217816 A CN201610217816 A CN 201610217816A CN 105915219 B CN105915219 B CN 105915219B
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- 230000010354 integration Effects 0.000 claims description 12
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
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Abstract
The embodiment of the invention discloses an analog-digital conversion circuit, which comprises: a modulation circuit; a modulation circuit, comprising: the chopper comprises a first chopper, a second chopper, a third chopper, a fourth chopper and an analog-to-digital converter; the analog signal is connected with the input end of the analog-to-digital converter through the first chopper and the second chopper; the output end of the analog-to-digital converter is connected with the input end of the signal extractor through a third chopper and a fourth chopper; the control ends of the first chopper and the fourth chopper are connected with first chopping signals, and the control ends of the second chopper and the third chopper are connected with second chopping signals; the frequency of the first chopping signal is less than the frequency of the second chopping signal. The analog-to-digital conversion circuit provided by the invention can reduce the influence of low-frequency noise and offset voltage generated by an operational amplifier in the analog-to-digital converter on analog-to-digital conversion, improve the signal-to-noise ratio of the processed signal and improve the precision of a signal processing system.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of analog to digital conversion circuits.
Background technique
With the development of the communication technology and integrated circuit technique, modulus conversion technique development is swift and violent.In the mould of numerous types
In number converter (ADC, Analog to Digital Converter), Sigma-Delta adc circuit can reach very high essence
Degree and good noise suppressed performance, without stringent on piece device matching.
The design of existing Sigma-Delta adc circuit, mainly by Sigma-Delta modulator and digital withdrawal device group
At.Along with the frequency overlapped-resistable filter for being located at Sigma-Delta modulator front end, a complete Sigma- is just constituted
Delta adc circuit structure.Referring to Fig. 1, which is the structure chart of Sigma-Delta ADC in the prior art.It is existing
Sigma-Delta ADC, comprising: frequency overlapped-resistable filter, Sigma-Delta modulator and digital withdrawal device.Frequency overlapped-resistable filter,
For eliminating the noise signal for being higher than 1/2 sample frequency in signal spectrum；Sigma-Delta modulator is used for signal sampling
And quantify, output digit signals；Digital decimation device, for filtering out quantizing noise, and according to nyquist sampling theorem to number
Signal resampling.Wherein, Sigma-Delta modulator, comprising: integration module, analog-to-digital conversion module, D/A converter module and
Comparison module.Due in integration module include operational amplifier, and operational amplifier generate low-frequency noise and offset voltage with
The frequency of required useful signal is close to be filtered out by digital decimation device, can impact to the result of analog-to-digital conversion.Also,
When analog-digital converter is applied to read the small-signal of the devices such as sensor output, the low-frequency noise and offset voltage can be serious
Influence the precision of signal-obtaining.
Therefore, those skilled in the art need to provide a kind of analog to digital conversion circuit, can reduce operation in analog-digital converter
Influence of the low-frequency noise and offset voltage that amplifier generates to analog-to-digital conversion, the signal-to-noise ratio of signal, promotes letter after raising processing
The precision of number processing system.
Summary of the invention
In order to solve prior art problem, the present invention provides a kind of analog to digital conversion circuits, can reduce analog-digital converter
Influence of the low-frequency noise and offset voltage that middle operational amplifier generates to analog-to-digital conversion, the signal-to-noise ratio of signal after raising processing,
The precision of promotion signal processing system.
Analog to digital conversion circuit provided in an embodiment of the present invention, comprising: modulation circuit；
The modulation circuit, comprising: the first chopper, the second chopper, third chopper, the 4th chopper and modulus turn
Parallel operation；
The input terminal of first chopper connects analog signal, the output end connection described second of first chopper
The control terminal of the input terminal of chopper, first chopper connects the first chopping signal；
The output end of second chopper connects the input terminal of the analog-digital converter, the control of second chopper
The second chopping signal of end connection；
The output end of the analog-digital converter connects the input terminal of the third chopper；
The output end of the third chopper connects the input terminal of the 4th chopper, the control of the third chopper
End connects second chopping signal；
The control terminal of the input terminal of the output end connection signal withdrawal device of 4th chopper, the 4th chopper connects
Connect first chopping signal；
The frequency of first chopping signal is less than the frequency of second chopping signal.
Preferably, further includes: first filter；
The input terminal of the first filter connects the output end of the third chopper, and the second of the first filter
End connects the input terminal of the 4th chopper.
Preferably, further includes: second filter
The input terminal of the second filter connects the output end of the 4th chopper, the output end of second filtering
Connect the input terminal of the signal extraction device.
Preferably, first chopper, comprising: first switch network, second switch network, third switching network and
Four switching networks；
The input terminal of the first switch network connects the anode of the input terminal of first chopper, the first switch
The output end of network connects the anode of the output end of first chopper, first switch network-based control end connection first
Control signal；
The input terminal of the second switch network connects the anode of the output end of first chopper, the second switch
The output end of network connects the cathode of the input terminal of first chopper, second switch network-based control end connection second
Control signal；
The input terminal of the third switching network connects the cathode of the input terminal of first chopper, the third switch
The output end of network connects the cathode of the output end of first chopper, described in the control terminal connection of the third switching network
First control signal；
The input terminal of 4th switching network connects the anode of the input terminal of first chopper, the 4th switch
The output end of network connects the cathode of the output end of first chopper, described in the control terminal connection of the 4th switching network
Second control signal；
The first control signal is first chopping signal；
The frequency of the second control signal is identical with the frequency of the first control signal, and the second control signal
Phase difference with the first control signal is (2N+1) π, and wherein N is the integer more than or equal to zero；
The internal structure of 4th chopper is identical as the internal structure of first chopper；
The control method of 4th chopper is identical as the control method of first chopper.
Preferably, second chopper, comprising: the 5th switching network, the 6th switching network, the 7th switching network and
Eight switching networks；
The input terminal of five switching network connects the anode of the input terminal of second chopper, the 5th switch net
The output end of network connects the anode of the output end of second chopper, and the control terminal of the 5th switching network connects third control
Signal processed；
The input terminal of 6th switching network connects the anode of the output end of second chopper, the 6th switch
The output end of network connects the cathode of the input terminal of second chopper, the control terminal connection the 4th of the 6th switching network
Control signal；
The input terminal of 7th switching network connects the cathode of the input terminal of second chopper, the 7th switch
The output end of network connects the cathode of the output end of second chopper, described in the control terminal connection of the 7th switching network
Third controls signal；
The input terminal of 8th switching network connects the anode of the input terminal of second chopper, the 8th switch
The output end of network connects the cathode of the output end of second chopper, described in the control terminal connection of the 8th switching network
4th control signal；
The third control signal is second chopping signal；
The frequency of the 4th control signal is identical with the frequency of third control signal, and the 4th control signal
Phase difference with third control signal is (2N+1) π, and wherein N is the integer more than or equal to zero；
The internal structure of the third chopper is identical as the internal structure of second chopper；
The control method of the third chopper is identical as the control method of second chopper.
Preferably, the first switch network, comprising: the first NMOS tube and the first PMOS tube；
The drain electrode of first NMOS tube connects the input terminal of the first switch network, the source electrode of first NMOS tube
The output end of the first switch network is connected, the grid of first NMOS tube connects the first control signal；
The source electrode of first PMOS tube connects the drain electrode of first NMOS tube, the drain electrode connection of first PMOS tube
The grid of the source electrode of first NMOS tube, first PMOS tube connects the second control signal；
The second switch network, comprising: the second NMOS tube and the second PMOS tube；
The drain electrode of second NMOS tube connects the input terminal of the second switch network, the source electrode of second NMOS tube
The output end of the second switch network is connected, the grid of second NMOS tube connects the second control signal；
The source electrode of second PMOS tube connects the drain electrode of second NMOS tube, the drain electrode connection of second PMOS tube
The grid of the source electrode of second NMOS tube, second PMOS tube connects the first control signal；
The third switching network, comprising: third NMOS tube and third PMOS tube；
The drain electrode of the third NMOS tube connects the input terminal of the third switching network, the source electrode of the third NMOS tube
The output end of the third switching network is connected, the grid of the third NMOS tube connects the first control signal；
The source electrode of the third PMOS tube connects the drain electrode of the third NMOS tube, the drain electrode connection of the third PMOS tube
The grid of the source electrode of the third NMOS tube, the third PMOS tube connects the second control signal；
4th switching network, comprising: the 4th NMOS tube and the 4th PMOS tube；
The drain electrode of 4th NMOS tube connects the input terminal of the 4th switching network, the source electrode of the 4th NMOS tube
The output end of the 4th switching network is connected, the grid of the 4th NMOS tube connects the second control signal；
The source electrode of 4th PMOS tube connects the drain electrode of the 4th NMOS tube, the drain electrode connection of the 4th PMOS tube
The grid of the source electrode of 4th NMOS tube, the 4th PMOS tube connects the first control signal.
Preferably, the 5th switching network, comprising: the 5th NMOS tube and the 5th PMOS tube；
The drain electrode of 5th NMOS tube connects the input terminal of the 5th switching network, the source electrode of the 5th NMOS tube
The output end of the 5th switching network is connected, the grid of the 5th NMOS tube connects the third and controls signal；
The source electrode of 5th PMOS tube connects the drain electrode of the 5th NMOS tube, the drain electrode connection of the 5th PMOS tube
The source electrode of 5th NMOS tube, the grid connection of the 5th PMOS tube the 4th control signal；
6th switching network, comprising: the 6th NMOS tube and the 6th PMOS tube；
The drain electrode of 6th NMOS tube connects the input terminal of the 6th switching network, the source electrode of the 6th NMOS tube
Connect the output end of the 6th switching network, the grid connection of the 6th NMOS tube the 4th control signal；
The source electrode of 6th PMOS tube connects the drain electrode of the 6th NMOS tube, the drain electrode connection of the 6th PMOS tube
The source electrode of 6th NMOS tube, the grid of the 6th PMOS tube connect the third and control signal；
7th switching network, comprising: the 7th NMOS tube and the 7th PMOS tube；
The drain electrode of 7th NMOS tube connects the input terminal of the 7th switching network, the source electrode of the 7th NMOS tube
The output end of the 7th switching network is connected, the grid of the 7th NMOS tube connects the third and controls signal；
The source electrode of 7th PMOS tube connects the drain electrode of the 7th NMOS tube, the drain electrode connection of the 7th PMOS tube
The source electrode of 7th NMOS tube, the grid connection of the 7th PMOS tube the 4th control signal；
8th switching network, comprising: the 8th NMOS tube and the 8th PMOS tube；
The drain electrode of 8th NMOS tube connects the input terminal of the 8th switching network, the source electrode of the 8th NMOS tube
Connect the output end of the 8th switching network, the grid connection of the 8th NMOS tube the 4th control signal；
The source electrode of 8th PMOS tube connects the drain electrode of the 8th NMOS tube, the drain electrode connection of the 8th PMOS tube
The source electrode of 8th NMOS tube, the grid of the 8th PMOS tube connect the third and control signal.
Preferably, the analog-digital converter, comprising: integration module, analog-to-digital conversion module, D/A converter module and compare mould
Block；
The input terminal of the integration module connects the output end of the comparison module, the output end connection of the integration module
The input terminal of the analog-to-digital conversion module；
The output end of the analog-to-digital conversion module connects the input terminal of the third chopper；
The input terminal of the D/A converter module connects the output end of the analog-to-digital conversion module, the D/A converter module
Output end connect the negative input end of the comparison module；
The positive input terminal of the comparison module connects the output end of second chopper.
Preferably, the analog-digital converter, for the first sample frequency to the output signal of second chopper into
Row sampling；
The first sample frequency fs1 >=2*fmax, fmax are the maximum frequency of the analog signal；
The signal extraction device, frequency is greater than the first predeterminated frequency in the output signal for filtering out the modulation circuit
Noise；
First predeterminated frequency is more than or equal to the maximum frequency of the analog signal；
The signal extraction device is also used to carry out down-sampled processing to the output signal of the modulation circuit, makes sampling frequency
Rate is reduced to the second sample frequency；
The second sample frequency fs2≤fs1 and fs2 >=2*fmax, fs1 are first sample frequency, and fmax is institute
State the maximum frequency of analog signal.
Preferably, further includes: third filter；
The third filter for filtering out the noise for being greater than the second predeterminated frequency in the analog signal, and will filter out
Signal afterwards is sent to the modulation circuit；
The second predeterminated frequency f2=fs1/2, fs1 are first sample frequency.
Compared with prior art, the present invention has at least the following advantages:
Analog to digital conversion circuit provided in an embodiment of the present invention, analog signal are modulated to through the first chopper and the second chopper
After high band, digital code stream is exported after analog-digital converter is by noise shaping.At this point, useful signal is in high band, and noise,
Imbalance and quantizing noise are in low-frequency range.The digital code stream is after third chopper and the modulation of the 4th chopper, at useful signal
In low-frequency range, and noise, imbalance and quantizing noise are in high band, through signal extraction device by the noise of high band, imbalance and
The disturbing factors such as quantizing noise filter out, and the low-frequency noise and offset voltage that operational amplifier generates in reduction analog-digital converter are to mould
The influence of number conversion, improves the precision of signal processing.Meanwhile because in the ideal case, the first chopper, the second chopper,
The copped wave ripple average energy that third chopper and the 4th chopper generate is zero, in the analog-digital converter as caused by copped wave ripple
The residual offset that operational amplifier is formed is removed.Analog to digital conversion circuit provided in an embodiment of the present invention can reduce modulus and turn
Influence of the low-frequency noise and offset voltage that operational amplifier generates in parallel operation to analog-to-digital conversion, improves the letter of signal after processing
It makes an uproar and compares, improve the precision of signal processing system.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, without creative efforts,
It can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is the structure chart of Sigma-Delta ADC in the prior art；
Fig. 2 is the schematic diagram of the embodiment one of analog to digital conversion circuit provided by the invention；
Fig. 3 (a) is the schematic diagram of the embodiment two of analog to digital conversion circuit provided by the invention；
Fig. 3 (b) is another schematic diagram of the embodiment two of analog to digital conversion circuit provided by the invention；
Fig. 4 (a) is the structure chart of the first chopper and the 4th chopper in analog to digital conversion circuit provided by the invention；
Fig. 4 (b) is the structure chart of the second chopper and third chopper in analog to digital conversion circuit provided by the invention；
Fig. 5 (a) is the first chopper of analog to digital conversion circuit provided by the invention and another structure of the 4th chopper
Figure；
Fig. 5 (b) is another structure of the second chopper and third chopper in analog to digital conversion circuit provided by the invention
Figure；
Fig. 6 is the schematic diagram of the embodiment three of analog to digital conversion circuit provided by the invention.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only this
Invention a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall within the protection scope of the present invention.
It is understood that analog-digital converter includes operational amplifier.Analog to digital conversion circuit provided by the invention, not only
It can be applied to the analog to digital conversion circuit being made of Sigma-Delta ADC, moreover it is possible to cross and be applied to be turned by other kinds of modulus
The analog to digital conversion circuit of parallel operation composition.
Embodiment one:
Referring to fig. 2, which is the schematic diagram of the embodiment one of analog to digital conversion circuit provided by the invention.
Analog to digital conversion circuit provided in this embodiment, comprising: modulation circuit 100；
The modulation circuit 100, comprising: the first chopper 101, the second chopper 103, third chopper the 103, the 4th are cut
Wave device 104 and analog-digital converter 105；
It is understood that analog-digital converter 105 can be any one analog-digital converter, for example, Sigma-Delta
ADC。
The input terminal of first chopper 101 connects analog signal, and the output end of first chopper 101 connects institute
The input terminal of the second chopper 102 is stated, the control terminal of first chopper 101 connects the first chopping signal
The output end of second chopper 102 connects the input terminal of the analog-digital converter 105, second chopper
102 control terminal connects the second chopping signal
First chopping signalFrequency be less than second chopping signalFrequency.
The frequency of the noise and offset voltage that are generated due to the operational amplifier in analog-digital converter 105 and analog signal is connect
Closely, it can not directly be filtered out using filter, influence the precision of analog-to-digital conversion.Therefore, before analog-digital converter 105, first is used
Analog signal is modulated to high band by chopper 501 and the second chopper 502, is allowed to the low frequency generated with analog-digital converter 105
The separation of the disturbing factors such as noise and offset voltage.At this point, the digital code stream that analog-digital converter 105 will export after noise shaping
In, useful signal is located at high band, and the disturbing factors such as noise, imbalance and quantizing noise are located at low-frequency range.
The output end of the analog-digital converter 105 connects the input terminal of the third chopper 103；
The output end of the third chopper 103 connects the input terminal of the 4th chopper 104, the third chopper
103 control terminal connects second chopping signal
The input terminal of the output end connection signal withdrawal device 200 of 4th chopper 104, the 4th chopper 104
Control terminal connect first chopping signal
It should be noted that after analog-digital converter 105 carries out the processing such as noise shaping to signal, third chopper 103
While the useful signal for being modulated to high band is restored to low-frequency range with the 4th chopper 104, by the noise of low-frequency range, imbalance
And quantizing noise is modulated to high band.The signal of 4th chopper 104 output making an uproar high band through signal extraction device 200
The disturbing factors such as sound, imbalance and quantizing noise filter out.
Further, since the Charge injection effect of the first chopper 101 and the second chopper 102 can be such that the signal after copped wave goes out
Existing copped wave ripple.And copped wave ripple can make the operational amplifier in analog-digital converter 105 export bigger residual offset.And it should
Residual offset is close with the signal frequency after copped wave, and signal extraction device 200 can not filter out.Therefore, connect after analog-digital converter 105
It connects third chopper 103 and the 4th chopper 104 is also used to remove and be generated by the first chopper 101 and the second chopper 102
Copped wave ripple.
It should be noted that guarantee the average energy of copped wave ripple close to zero, second chopping signalFrequencyWith the first chopping signalFrequencyBetween relationship beWherein k is the integer greater than 1.
Due to controlling the first chopping signal of the first chopper 101Frequency be less than second chopper 102 of control
Second chopping signalFrequency, the first chopper 101 generate copped wave ripple far below the second chopper 102 generate cutting
Wave ripple, the copped wave ripple that the first chopper 101 generates can be ignored.The copped wave ripple that second chopper 102 generates is through third
After chopper 103 and the modulation of the 4th chopper 104, the average energy of copped wave ripple is zero, and the remnants as caused by copped wave ripple lose
It sets to zero.At this point, the residual offset as caused by 102 copped wave of the first chopper 101 and the second chopper is by 103 He of third chopper
4th chopper 104 is removed, to effectively inhibit residual offset.
Analog to digital conversion circuit provided in this embodiment, analog signal are modulated to high frequency through the first chopper and the second chopper
Duan Hou exports digital code stream after analog-digital converter is by noise shaping.At this point, useful signal is in high band, and noise, imbalance
Low-frequency range is in quantizing noise.For the digital code stream after third chopper and the modulation of the 4th chopper, useful signal is in low
Frequency range, and noise, imbalance and quantizing noise are in high band, through signal extraction device by the noise of high band, imbalance and quantization
The disturbing factors such as noise filter out, and reduce the low-frequency noise of operational amplifier generation and offset voltage in analog-digital converter and turn to modulus
The influence changed improves the precision of signal processing.Meanwhile because in the ideal case, the first chopper, the second chopper, third
The copped wave ripple average energy that chopper and the 4th chopper generate is zero, operation in the analog-digital converter as caused by copped wave ripple
The residual offset that amplifier is formed is removed.Analog to digital conversion circuit provided in this embodiment can reduce in analog-digital converter and transport
The influence of the low-frequency noise and offset voltage of amplifier generation to analog-to-digital conversion is calculated, the signal-to-noise ratio of signal after processing is improved, mentions
The precision of signal processing system is risen.
Embodiment two:
Referring to Fig. 3 (a), which is the schematic diagram of the embodiment two of analog to digital conversion circuit provided by the invention.Compared to figure
2, present embodiments provide a kind of realization structure of more specifical analog to digital conversion circuit.
For the significantly more efficient requirement for filtering out noise and imbalance in digital signal, reducing to signal extraction device performance, originally
The modulation circuit 100 that embodiment provides, further includes: first filter 106；
The input terminal of the first filter 106 connects the output end of the third chopper 103, the first filter
106 second end connects the input terminal of the 4th chopper 104.
It should be noted that useful signal is located at high band, and quantization is made an uproar in the digital code stream that analog-digital converter 105 exports
The low-frequency noise that sound and operational amplifier generate and the disturbing factors such as imbalance are located at low-frequency range.At this point, third chopper 103 will
Useful signal is modulated to the odd harmonic of the first chopping signal, and the noise and imbalance at low frequency are modulated onto high band.Through
One filter 106 can filter out the disturbing factors such as the noise of high band and imbalance.Digital code stream warp after filtering out noise and imbalance
The modulation of 4th chopper 104, can restore useful signal to original frequency section.
Remaining noise can be filtered out further through signal extraction device 200 after the modulation of 4th chopper 104.
Referring to Fig. 3 (b), which is another schematic diagram of the embodiment two of analog to digital conversion circuit provided by the invention.
The modulation circuit 100, further includes: second filter 107
The input terminal of the second filter 107 connects the output end of the 4th chopper 104, second filtering
102 output end connects the input terminal of the signal extraction device 200.
It is understood that second filter 107 can filter out the noise of high band and imbalance.The signal that it is counted is through believing
Number withdrawal device 200 carries out after filtering out noise and sampling processing, and the precision of signal processing can be improved.
It is understood that first filter 106 is identical with the effect of second filter 107, only in analog-to-digital conversion electricity
Position in road is different.First filter 106 and second filter 107 may each be wave digital lowpass filter.First filter
106 cutoff frequency and the cutoff frequency of second filter 107 can be chosen according to the actual situation.
It is low to add a number between third chopper and signal extraction device for analog to digital conversion circuit provided in this embodiment
The signal-to-noise ratio of signal after processing, the precision of promotion signal processing system can be improved in bandpass filter.Also, the digital low-pass filtering
Device can reduce the requirement in analog to digital conversion circuit to signal extraction device performance, reduce the cost of manufacture of circuit.
Chopper internal structure:
Referring to fig. 4 (a), which is the knot of the first chopper and the 4th chopper in analog to digital conversion circuit provided by the invention
Composition.
First chopper, comprising: first switch network 101a, second switch network 101b, third switching network
101c and the 4th switching network 101d；
The input terminal of the first switch network 101a connects the anode of the input terminal of first chopper, and described first
The output end of switching network 101a connects the anode of the output end of first chopper, the control of the first switch network 101a
End processed connects first control signal
The input terminal of the second switch network 101b connects the anode of the output end of first chopper, and described second
The output end of switching network 101b connects the cathode of the input terminal of first chopper, the control of the second switch network 101b
End processed connects second control signal
The input terminal of the third switching network 101c connects the cathode of the input terminal of first chopper, the third
The output end of switching network 101c connects the cathode of the output end of first chopper, the control of the third switching network 101c
End processed connects the first control signal
The input terminal of the 4th switching network 101d connects the anode of the input terminal of first chopper, and the described 4th
The output end of switching network 101d connects the cathode of the output end of first chopper, the control of the 4th switching network 101d
End processed connects the second control signal
The first control signalFor first chopping signal
The second control signalFrequency and the first control signalFrequency it is identical, and it is described second control
Signal processedWith the first control signalPhase difference be (2N+1) π, wherein N is integer more than or equal to zero；
It is understood that first control signalWith second control signalFor complementary signal.
The internal structure of 4th chopper is identical as the internal structure of first chopper；
The control method of 4th chopper is identical as the control method of first chopper.
The off state of chopper internal switch pipe are as follows: first switch network 101a and third switching network 101c conducting,
Second switch network 101b and the 4th switching network 101d shutdown, or, first switch network 101a and third switching network 101c
Shutdown, second switch network 101b and the 4th switching network 101d conducting.
It is understood that first switch network 101a, second switch network 101b, third switching network 101c and the 4th
Switching network 101d can be NMOS tube or PMOS tube.
Referring to fig. 4 (b), which is the knot of the second chopper and third chopper in analog to digital conversion circuit provided by the invention
Composition.
It is understood that the internal structure of the second chopper is identical with the internal structure of the first chopper, but second cuts
The control signal of wave device and the control signal of the first chopper are different.
Second chopper, comprising: the 5th switching network 102a, the 6th switching network 102b, the 7th switching network
102c and the 8th switching network 102d；
The input terminal of the five switching networks 102a connects the anode of the input terminal of second chopper, and the described 5th opens
The output end of pass network 102a connects the anode of the output end of second chopper, the control of the 5th switching network 102a
End connection third controls signal
The input terminal of the 6th switching network 102b connects the anode of the output end of second chopper, and the described 6th
The output end of switching network 102b connects the cathode of the input terminal of second chopper, the control of the 6th switching network 102b
Connection the 4th control signal in end processed
The input terminal of the 7th switching network 102c connects the cathode of the input terminal of second chopper, and the described 7th
The output end of switching network 102c connects the cathode of the output end of second chopper, the control of the 7th switching network 102c
End processed connects the third and controls signal
The input terminal of the 8th switching network 102d connects the anode of the input terminal of second chopper, and the described 8th
The output end of switching network 102d connects the cathode of the output end of second chopper, the control of the 8th switching network 102d
Connection the 4th control signal in end processed
The third controls signalFor second chopping signal
The 4th control signalFrequency and the third control signalFrequency it is identical, and it is described 4th control
Signal processedSignal is controlled with the thirdPhase difference be (2N+1) π, wherein N is integer more than or equal to zero；
It is understood that third controls signalWith the 4th control signalFor complementary signal.
The internal structure of the third chopper is identical as the internal structure of second chopper；
The control method of the third chopper is identical as the control method of second chopper.
The off state of chopper internal switch pipe are as follows: the 5th switching network 102a and the 7th switching network 102c conducting,
6th switching network 102b and the 8th switching network 102d shutdown, or, the 5th switching network 102a and the 7th switching network 102c
Shutdown, the 6th switching network 102b and the 8th switching network 102d conducting.
It is understood that the 5th switching network 102a, the 6th switching network 102b, the 7th switching network 102c and the 8th
Switching network 102d can be NMOS tube or PMOS tube.
The internal structure and control method of first chopper and the 4th chopper are all the same, and the second chopper and third
The internal structure and control method of chopper are all the same.
Referring to Fig. 5 (a), the figure be analog to digital conversion circuit provided by the invention the first chopper and the 4th chopper it is another
A kind of structure chart.
For further decrease switching device in chopper charge injection effect etc. non-ideal effects it is defeated to analog to digital conversion circuit
The influence of the signal-to-noise ratio of signal and precision out, the first switch network 101a, comprising: the first NMOS tube NM1 and the first PMOS
Pipe PM1；
The drain electrode of the first NMOS tube NM1 connects the input terminal of the first switch network 101a, the first NMOS
The source electrode of pipe NM1 connects the output end of the first switch network 101a, the grid connection of the first NMOS tube NM1 described the
One control signal
The source electrode of the first PMOS tube PM1 connects the drain electrode of the first NMOS tube NM1, the first PMOS tube PM1
Drain electrode connect the source electrode of the first NMOS tube NM1, the grid of the first PMOS tube PM1 connects the second control signal
It is understood that the first NMOS tube NM1 and the first PMOS tube PM1 constitutes CMOS complementary switch.CMOS complementation is opened
Resistance is smaller when closing conducting, can reduce influence of the non-ideal effects such as the Charge injection effect of switch to analog to digital conversion circuit.
Second NMOS tube NM2 and the second PMOS tube PM2, third NMOS tube NM3 and third PMOS tube PM3 and the 4th NMOS tube NM4 and
The connection relationship of 4th PMOS tube PM4 is similar to the connection relationship of the first NMOS tube NM1 and the first PMOS tube PM1, constitutes
CMOS complementary switch.
The second switch network 101b, comprising: the second NMOS tube NM2 and the second PMOS tube PM2；
The drain electrode of the second NMOS tube NM2 connects the input terminal of the second switch network 101b, the 2nd NMOS
The source electrode of pipe NM2 connects the output end of the second switch network 101b, the grid connection of the second NMOS tube NM2 described the
Two control signals
The source electrode of the second PMOS tube PM2 connects the drain electrode of the second NMOS tube NM2, the second PMOS tube PM2
Drain electrode connect the source electrode of the second NMOS tube NM2, the grid of the second PMOS tube PM2 connects the first control signal
The third switching network 101c, comprising: third NMOS tube NM3 and third PMOS tube PM3；
The drain electrode of the third NMOS tube NM3 connects the input terminal of the third switching network 101c, the 3rd NMOS
The source electrode of pipe NM3 connects the output end of the third switching network 101c, the grid connection of the third NMOS tube NM3 described the
One control signal
The source electrode of the third PMOS tube PM3 connects the drain electrode of the third NMOS tube NM3, the third PMOS tube PM3
Drain electrode connect the source electrode of the third NMOS tube NM3, the grid of the third PMOS tube PM3 connects the second control signal
The 4th switching network 101d, comprising: the 4th NMOS tube NM4 and the 4th PMOS tube PM4；
The drain electrode of the 4th NMOS tube NM4 connects the input terminal of the 4th switching network 101d, the 4th NMOS
The source electrode of pipe NM4 connects the output end of the 4th switching network 101d, the grid connection of the 4th NMOS tube NM4 described the
Two control signals
The source electrode of the 4th PMOS tube PM4 connects the drain electrode of the 4th NMOS tube NM4, the 4th PMOS tube PM4
Drain electrode connect the source electrode of the 4th NMOS tube NM4, the grid of the 4th PMOS tube PM4 connects the first control signal
Referring to Fig. 5 (b), which is the another of the second chopper and third chopper in analog to digital conversion circuit provided by the invention
A kind of structure chart.
The 5th switching network 101a, comprising: the 5th NMOS tube NM5 and the 5th PMOS tube PM5；
The drain electrode of the 5th NMOS tube NM5 connects the input terminal of the 5th switching network 101a, the 5th NMOS
The source electrode of pipe NM5 connects the output end of the 5th switching network 101a, the grid connection of the 5th NMOS tube NM5 described the
Three control signals
The source electrode of the 5th PMOS tube PM5 connects the drain electrode of the 5th NMOS tube NM5, the 5th PMOS tube PM5
Drain electrode connect the source electrode of the 5th NMOS tube NM5, the grid connection of the 5th PMOS tube PM5 the 4th control signal
The 6th switching network 102b, comprising: the 6th NMOS tube NM6 and the 6th PMOS tube PM6；
The drain electrode of the 6th NMOS tube NM6 connects the input terminal of the 6th switching network 101b, the 6th NMOS
The source electrode of pipe NM6 connects the output end of the 6th switching network 101b, the grid connection of the 6th NMOS tube NM6 described the
Four control signals
The source electrode of the 6th PMOS tube PM6 connects the drain electrode of the 6th NMOS tube NM6, the 6th PMOS tube PM6
Drain electrode connect the source electrode of the 6th NMOS tube NM6, the grid of the 6th PMOS tube PM6 connects the third and controls signal
The 7th switching network 102c, comprising: the 7th NMOS tube NM7 and the 7th PMOS tube PM7；
The drain electrode of the 7th NMOS tube NM7 connects the input terminal of the 7th switching network 101c, the 7th NMOS
The source electrode of pipe NM7 connects the output end of the 7th switching network 101c, the grid connection of the 7th NMOS tube NM7 described the
Three control signals
The source electrode of the 7th PMOS tube PM7 connects the drain electrode of the 7th NMOS tube NM7, the 7th PMOS tube PM7
Drain electrode connect the source electrode of the 7th NMOS tube NM7, the grid connection of the 7th PMOS tube PM7 the 4th control signal
The 8th switching network 102d, comprising: the 8th NMOS tube NM8 and the 8th PMOS tube PM8；
The drain electrode of the 8th NMOS tube NM8 connects the input terminal of the 8th switching network 101d, the 8th NMOS
The source electrode of pipe NM8 connects the output end of the 8th switching network 101d, the grid connection of the 8th NMOS tube NM8 described the
Four control signals
The source electrode of the 8th PMOS tube PM8 connects the drain electrode of the 8th NMOS tube NM8, the 8th PMOS tube PM8
Drain electrode connect the source electrode of the 8th NMOS tube NM8, the grid of the 8th PMOS tube PM8 connects the third and controls signal
Analog to digital conversion circuit provided in this embodiment, chopper are made of CMOS technology, be can be effectively reduced modulus and are turned
The influence of the noise of operational amplifier and offset voltage to A/D conversion accuracy in parallel operation, the noise of signal after raising processing
Than the precision of promotion signal processing system.
Embodiment three:
Referring to Fig. 6, which is the schematic diagram of the embodiment three of analog to digital conversion circuit provided by the invention.Compared to Fig. 2, originally
Embodiment provides a kind of realization structure of more specifical analog to digital conversion circuit.
In analog to digital conversion circuit provided in this embodiment, the analog-digital converter 105, for the first sample frequency fs1
The output signal of second chopper 102 is sampled；
The first sample frequency fs1 >=2*fmax, fmax are the maximum frequency of the analog signal.
It is understood that analog-digital converter 105 is generally using the frequency much larger than Nyquist sampling frequency to simulation
Signal is sampled, i.e. over-sampling, to improve the signal-to-noise ratio of the digital signal of output.First sample frequency fs1=M*2fmax, M
Value generally between 8-256, can choose according to the actual situation.
The analog-digital converter 105, comprising: integration module 105a, analog-to-digital conversion module 105b, D/A converter module 105c
With comparison module 105d；
The input terminal of the integration module 105a connects the output end of the comparison module 105d, the integration module 105a
Output end connect the input terminal of the analog-to-digital conversion module 105b；
The output end of the analog-to-digital conversion module 105b connects the input terminal of the third chopper 103；
The input terminal of the D/A converter module 105c connects the output end of the analog-to-digital conversion module 105b, the digital-to-analogue
The output end of conversion module 105c connects the negative input end of the comparison module 105d；
The positive input terminal of the comparison module 105d connects the output end of second chopper 102.
After the integrated module 105a noise shaping of signal of second chopper output, quantify through analog-to-digital conversion module 105b defeated
Out.Output signal makes the difference after D/A converter module 105c processing by comparing module 105d and the output signal of the second chopper
Compare, gradually reduce difference, so that the output signal of analog-digital converter 105 is close to input signal.
It should be noted that integration module 105a can be feedforward loop circuit filter, i.e., a kind of discrete-time integrator.Mould
Number converter 105 can be monocycle Sigma-Delta modulator or cascade connection type Sigma-Delta modulator.Integration module 105a
Including discrete-time integrator number it is more, just closer to output, the precision of analog-to-digital conversion is higher for output.
The signal extraction device 200 is greater than the first default frequency for filtering out frequency in 100 output signal of modulation circuit
The noise of rate；
First predeterminated frequency is more than or equal to the maximum frequency of the analog signal；
The signal extraction device 200 is also used to carry out down-sampled processing to the output signal of the modulation circuit, makes to sample
Frequency will be the second sample frequency；
The second sample frequency fs2≤fs1 and fs2 >=2*fmax, fs1 are the first sample frequency, and fmax is the mould
The maximum frequency of quasi- signal.
On the one hand signal extraction device 200 filters out the noise other than signal bandwidth；On the other hand to the digital signal of output into
Row double sampling reduces the sample frequency of digital signal, facilitates the transmission and storage of digital signal, reduces power wastage.
It is understood that the noise-filtering part of signal extraction device 200 can by cascade comb filter and several half
Band filter cascade composition.The double sampling of signal extraction device 200 can be used a certain intermediate samples frequency and carry out repeatedly to signal
Sampling, finally makes sample frequency be reduced to the second sample frequency fs2.Second sample frequency fs2 can according to actual needs according to how
Qwest's sampling thheorem is chosen.
D/A converting circuit provided in this embodiment, further includes: third filter 300；
The third filter 300, for filtering out the noise for being greater than the second predeterminated frequency in the analog signal, and will filter
Signal after removing is sent to the modulation circuit 100；
The second predeterminated frequency f2=fs1/2, fs1 are first sample frequency.
According to nyquist sampling theorem, sample frequency need to be greater than twice of frequency input signal, otherwise will cause aliasing.
Third filter 300 will be higher than the signal on the frequency spectrum of 1/2 sample frequency in analog signal, reduce to analog to digital conversion circuit performance
Requirement, avoid aliasing.
It is understood that over-sampling reduces the requirement to 300 performance of third filter, analog to digital conversion circuit is reduced
Cost of manufacture.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Though
So the present invention has been disclosed as a preferred embodiment, and however, it is not intended to limit the invention.It is any to be familiar with those skilled in the art
Member, without departing from the scope of the technical proposal of the invention, all using the methods and technical content of the disclosure above to the present invention
Technical solution makes many possible changes and modifications or equivalent example modified to equivalent change.Therefore, it is all without departing from
The content of technical solution of the present invention, according to the technical essence of the invention any simple modification made to the above embodiment, equivalent
Variation and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (8)
1. a kind of analog to digital conversion circuit characterized by comprising modulation circuit；
The modulation circuit, comprising: the first chopper, the second chopper, third chopper, the 4th chopper and analog-to-digital conversion
Device；
The input terminal of first chopper connects analog signal, and the output end of first chopper connects second copped wave
The control terminal of the input terminal of device, first chopper connects the first chopping signal；
The output end of second chopper connects the input terminal of the analog-digital converter, and the control terminal of second chopper connects
Connect the second chopping signal；
The output end of the analog-digital converter connects the input terminal of the third chopper；
The output end of the third chopper connects the input terminal of the 4th chopper, and the control terminal of the third chopper connects
Connect second chopping signal；
The control terminal of the input terminal of the output end connection signal withdrawal device of 4th chopper, the 4th chopper connects institute
State the first chopping signal；
The third chopper and the 4th chopper are also used to remove by first chopper and second chopper
The copped wave ripple of generation；The frequency of first chopping signal is less than the frequency of second chopping signal, and described second cuts
The frequency of wave signal is k times of the frequency of first chopping signal, and k is the integer greater than 1；
First chopper, comprising: first switch network, second switch network, third switching network and the 4th switching network；
The input terminal of the first switch network connects the anode of the input terminal of first chopper, the first switch network
Output end connect first chopper output end anode, the first switch network-based control end connection first control
Signal；
The input terminal of the second switch network connects the anode of the output end of first chopper, the second switch network
Output end connect first chopper input terminal cathode, the second switch network-based control end connection second control
Signal；
The input terminal of the third switching network connects the cathode of the input terminal of first chopper, the third switching network
Output end connect first chopper output end cathode, the third switching network control terminal connection described first
Control signal；
The input terminal of 4th switching network connects the anode of the input terminal of first chopper, the 4th switching network
Output end connect first chopper output end cathode, the 4th switching network control terminal connection described second
Control signal；
The first control signal is first chopping signal；
The frequency of the second control signal is identical with the frequency of the first control signal, and the second control signal and institute
The phase difference for stating first control signal is (2N+1) π, and wherein N is the integer more than or equal to zero；
The internal structure of 4th chopper is identical as the internal structure of first chopper；
The control method of 4th chopper is identical as the control method of first chopper；
Second chopper, comprising: the 5th switching network, the 6th switching network, the 7th switching network and the 8th switching network；
The input terminal of five switching network connects the anode of the input terminal of second chopper, the 5th switching network
Output end connects the anode of the output end of second chopper, the control terminal connection third control letter of the 5th switching network
Number；
The input terminal of 6th switching network connects the anode of the output end of second chopper, the 6th switching network
Output end connect second chopper input terminal cathode, the 6th switching network control terminal connection the 4th control
Signal；
The input terminal of 7th switching network connects the cathode of the input terminal of second chopper, the 7th switching network
Output end connect second chopper output end cathode, the control terminal of the 7th switching network connects the third
Control signal；
The input terminal of 8th switching network connects the anode of the input terminal of second chopper, the 8th switching network
Output end connect second chopper output end cathode, the 8th switching network control terminal connection the described 4th
Control signal；
The third control signal is second chopping signal；
The frequency of the 4th control signal is identical with the frequency of third control signal, and the 4th control signal and institute
The phase difference for stating third control signal is (2N+1) π, and wherein N is the integer more than or equal to zero；
The internal structure of the third chopper is identical as the internal structure of second chopper；
The control method of the third chopper is identical as the control method of second chopper.
2. analog to digital conversion circuit according to claim 1, which is characterized in that the modulation circuit, further includes: the first filtering
Device；
The input terminal of the first filter connects the output end of the third chopper, and the second end of the first filter connects
Connect the input terminal of the 4th chopper.
3. analog to digital conversion circuit according to claim 1, which is characterized in that the modulation circuit, further includes: the second filtering
Device
The input terminal of the second filter connects the output end of the 4th chopper, the output end connection of second filtering
The input terminal of the signal extraction device.
4. analog to digital conversion circuit according to claim 1, which is characterized in that
The first switch network, comprising: the first NMOS tube and the first PMOS tube；
The drain electrode of first NMOS tube connects the input terminal of the first switch network, the source electrode connection of first NMOS tube
The grid of the output end of the first switch network, first NMOS tube connects the first control signal；
The source electrode of first PMOS tube connects the drain electrode of first NMOS tube, described in the drain electrode connection of first PMOS tube
The grid of the source electrode of first NMOS tube, first PMOS tube connects the second control signal；
The second switch network, comprising: the second NMOS tube and the second PMOS tube；
The drain electrode of second NMOS tube connects the input terminal of the second switch network, the source electrode connection of second NMOS tube
The grid of the output end of the second switch network, second NMOS tube connects the second control signal；
The source electrode of second PMOS tube connects the drain electrode of second NMOS tube, described in the drain electrode connection of second PMOS tube
The grid of the source electrode of second NMOS tube, second PMOS tube connects the first control signal；
The third switching network, comprising: third NMOS tube and third PMOS tube；
The drain electrode of the third NMOS tube connects the input terminal of the third switching network, the source electrode connection of the third NMOS tube
The grid of the output end of the third switching network, the third NMOS tube connects the first control signal；
The source electrode of the third PMOS tube connects the drain electrode of the third NMOS tube, described in the drain electrode connection of the third PMOS tube
The grid of the source electrode of third NMOS tube, the third PMOS tube connects the second control signal；
4th switching network, comprising: the 4th NMOS tube and the 4th PMOS tube；
The drain electrode of 4th NMOS tube connects the input terminal of the 4th switching network, the source electrode connection of the 4th NMOS tube
The grid of the output end of 4th switching network, the 4th NMOS tube connects the second control signal；
The source electrode of 4th PMOS tube connects the drain electrode of the 4th NMOS tube, described in the drain electrode connection of the 4th PMOS tube
The grid of the source electrode of 4th NMOS tube, the 4th PMOS tube connects the first control signal.
5. analog to digital conversion circuit according to claim 1, which is characterized in that
5th switching network, comprising: the 5th NMOS tube and the 5th PMOS tube；
The drain electrode of 5th NMOS tube connects the input terminal of the 5th switching network, the source electrode connection of the 5th NMOS tube
The output end of 5th switching network, the grid of the 5th NMOS tube connect the third and control signal；
The source electrode of 5th PMOS tube connects the drain electrode of the 5th NMOS tube, described in the drain electrode connection of the 5th PMOS tube
The source electrode of 5th NMOS tube, the grid connection of the 5th PMOS tube the 4th control signal；
6th switching network, comprising: the 6th NMOS tube and the 6th PMOS tube；
The drain electrode of 6th NMOS tube connects the input terminal of the 6th switching network, the source electrode connection of the 6th NMOS tube
The output end of 6th switching network, the grid connection of the 6th NMOS tube the 4th control signal；
The source electrode of 6th PMOS tube connects the drain electrode of the 6th NMOS tube, described in the drain electrode connection of the 6th PMOS tube
The source electrode of 6th NMOS tube, the grid of the 6th PMOS tube connect the third and control signal；
7th switching network, comprising: the 7th NMOS tube and the 7th PMOS tube；
The drain electrode of 7th NMOS tube connects the input terminal of the 7th switching network, the source electrode connection of the 7th NMOS tube
The output end of 7th switching network, the grid of the 7th NMOS tube connect the third and control signal；
The source electrode of 7th PMOS tube connects the drain electrode of the 7th NMOS tube, described in the drain electrode connection of the 7th PMOS tube
The source electrode of 7th NMOS tube, the grid connection of the 7th PMOS tube the 4th control signal；
8th switching network, comprising: the 8th NMOS tube and the 8th PMOS tube；
The drain electrode of 8th NMOS tube connects the input terminal of the 8th switching network, the source electrode connection of the 8th NMOS tube
The output end of 8th switching network, the grid connection of the 8th NMOS tube the 4th control signal；
The source electrode of 8th PMOS tube connects the drain electrode of the 8th NMOS tube, described in the drain electrode connection of the 8th PMOS tube
The source electrode of 8th NMOS tube, the grid of the 8th PMOS tube connect the third and control signal.
6. analog to digital conversion circuit according to claim 1, which is characterized in that the analog-digital converter, comprising: integral mould
Block, analog-to-digital conversion module, D/A converter module and comparison module；
The input terminal of the integration module connects the output end of the comparison module, described in the output end connection of the integration module
The input terminal of analog-to-digital conversion module；
The output end of the analog-to-digital conversion module connects the input terminal of the third chopper；
The input terminal of the D/A converter module connects the output end of the analog-to-digital conversion module, the D/A converter module it is defeated
Outlet connects the negative input end of the comparison module；
The positive input terminal of the comparison module connects the output end of second chopper.
7. analog to digital conversion circuit according to claim 1, which is characterized in that
The analog-digital converter, for being sampled with output signal of first sample frequency to second chopper；
Fs1 >=2*fmax, fs1 are first sample frequency, and fmax is the maximum frequency of the analog signal；
The signal extraction device, frequency is greater than making an uproar for the first predeterminated frequency in the output signal for filtering out the modulation circuit
Sound；
First predeterminated frequency is more than or equal to the maximum frequency of the analog signal；
The signal extraction device is also used to carry out down-sampled processing to the output signal of the modulation circuit, drops sample frequency
For the second sample frequency；
Fs1 >=fs2 >=2*fmax, fs2 are second sample frequency, and fs1 is first sample frequency, and fmax is the mould
The maximum frequency of quasi- signal.
8. analog to digital conversion circuit according to claim 7, which is characterized in that further include: third filter；
The third filter, for filtering out the noise for being greater than the second predeterminated frequency in the analog signal, and after filtering out
Signal is sent to the modulation circuit；
F2=fs1/2, f2 are second predeterminated frequency, and fs1 is first sample frequency.
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| CN110376520B (en) * | 2019-08-15 | 2020-06-30 | 珠海格力电器股份有限公司 | Motor parameter acquisition device, motor and motor parameter acquisition method thereof |
| CN110492887B (en) * | 2019-08-20 | 2024-07-19 | 深圳市锐能微科技有限公司 | Analog-to-digital converter circuit |
| CN116232323A (en) * | 2021-12-02 | 2023-06-06 | 华润微集成电路(无锡)有限公司 | Signal conditioning circuit and data processing method |
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