CN105843195A - Power-on control system for multiple controllers - Google Patents
Power-on control system for multiple controllers Download PDFInfo
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- CN105843195A CN105843195A CN201610348734.8A CN201610348734A CN105843195A CN 105843195 A CN105843195 A CN 105843195A CN 201610348734 A CN201610348734 A CN 201610348734A CN 105843195 A CN105843195 A CN 105843195A
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- 238000001514 detection method Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 6
- 238000004891 communication Methods 0.000 claims abstract description 4
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 5
- 238000007689 inspection Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 2
- 230000009131 signaling function Effects 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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- Engineering & Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention relates to a power-on control system for multiple controllers. In the existing multi-controller system, uncertainty of the IO control pin state of the main controller occurs frequently to cause a data conflict on a bus, so that heavy currents are generated and even an IO port is burned; and secret communication is formed between a bus driver and an IO power supply of a controller during the power on process of the driver, so that control of the power-on time sequence is affected. However, with the provided system the above-mention problems in the prior art can be solved. Power-on state control of a bus driver is carried out by means of detection; when a detection circuit can not receive a pulse or the number of pulses received continuously is less than a specified value at a designated frequency and a designated duty ratio, the bus driver is in a high impedance state; and when the number of received continuous pulses reaches the designated number and the designated frequency and duty ratio are reached, the high impedance state of the bus driver is released. With the method, reliable control of the power-on state and the power-on time sequence among multiple controllers is realized. Moreover, the circuit is realized simply and control becomes convenient.
Description
Technical field
The present invention relates to the upper electric control system of a kind of multi-controller, be specifically related to one and be applied to aerial image
The upper electric control system of multi-controller.
Background technology
For realizing complicated function, the mode of control system many employings multiple controller combination now.Control
Shared bus between device, master controller realizes data transmission and direction between different controller by bus driver and controls
System.During system electrification, easily occur that master controller IO controls the uncertainty of pin status, cause
Data collision in bus and occur that big electric current even burns I/O port, simultaneously as many number controllers IO
Port is internal exists protection diode, easily occurs that the bus driver IO with controller in power up powers
Power supply is formed latent logical, affects the control of electrifying timing sequence.
Summary of the invention
The present invention solves in existing multi controller systems, easily occur that master controller IO controls pin status not
Definitiveness, causes the data collision in bus to occur that big electric current even burns I/O port and existing bus driver
Device IO power supply with controller in power up is formed latent logical, affects the problem such as control of electrifying timing sequence,
The system electrification control system of a kind of multi-controller is provided.
The upper electric control system of multi-controller, including master controller, multiple bus control circuit, multiple bus
Driver and multiple from controller；Bus driver is controlled by described master controller by bus control circuit
System, it is achieved exchange from communication and the data of controller；Described bus control circuit include series resistance R1,
Coupling electric capacity C1, testing circuit, inverter group and low pressure biasing circuit；
The square-wave signal of master controller input is concatenated resistance R1 and coupling electric capacity C1 and sends into detecting circuit,
Low pressure biasing circuit provides bias level for detecting circuit；
When detecting circuit do not receive pulse signal or the pulse frequency that continuously receives be f (1/T), dutycycle be
When τ and pulse number are less than setting m；The signal inverted device group of detecting circuit output negates and drives
After Dong, output makes bus driver be in the level value of high resistant；
The continuous impulse frequency received when described detecting circuit is f (1/T), dutycycle is τ and pulse number reaches
During to setting m, bus driver releases high-impedance state；Described m > 1.
Beneficial effects of the present invention: the upper electric control system of multi-controller of the present invention, can realize controlling more
Make bus-structured system electrification state and reliably control the guarantee with electrifying timing sequence.The present invention uses the side of detection
Method carries out the power-up state of bus driver and controls, when detecting circuit does not receives pulse or in the frequency specified
With the pulse number continuously received in the case of dutycycle less than setting, bus driver is all made to be in high resistant
State；When the continuous impulse received reaches frequency, dutycycle and the number of regulation, bus driver side
Release high-impedance state.Use the method can realize the power-up state between multi-controller and electrifying timing sequence reliably control,
And circuit realiration is simple, easy to control.
Accompanying drawing explanation
Fig. 1 is the structure chart of the system electrification control method of multi-controller of the present invention；
Fig. 2 be multi-controller of the present invention system electrification control method in the structure of bus control circuit
Schematic diagram.
Detailed description of the invention
Detailed description of the invention one, combine Fig. 1 and Fig. 2 present embodiment is described, the upper electric control of multi-controller
System, including master controller, multiple bus control circuit, multiple bus driver and multiple from controller；
Bus driver is controlled by described master controller by bus control circuit, it is achieved lead to from controller
News and data exchange；Described bus control circuit include series resistance R1, coupling electric capacity C1, testing circuit,
Inverter group and low pressure biasing circuit.
In conjunction with Fig. 2, the square-wave signal of master controller input is concatenated resistance R1 and coupling electric capacity C1 and sends into
Detecting circuit, low pressure biasing circuit provides bias level for detecting circuit；When detecting circuit does not receives pulse
When signal or the pulse frequency continuously received are f (1/T), dutycycle is τ and pulse number is less than setting m；
After the signal inverted device group of detecting circuit output negates and drives, output makes bus driver be in high resistant
Level value；The continuous impulse frequency received when described detecting circuit is f (1/T), dutycycle is τ and pulse
When number reaches setting m, bus driver releases high-impedance state；Described m > 1.
In present embodiment, set detecting circuit and receive moment corresponding to first pulse as t, reception continuous
Pulse number is m, frequency is f (1/T), the pulse period is T and dutycycle is τ, and low pressure biasing circuit is defeated
Going out voltage is VBIAS, the amplitude of low pressure biasing circuit input pulse signal is VmTime, then meet following relational expression:
Vdiode-0.1 ＜ Vm-VBIAS＜ Vdiode；Described VdiodeFor detecting circuit internal equivalent diode time in the conduction state
Pressure drop；The voltage V of described detecting circuit outputCT=VBIAS, the then voltage V of detecting circuit outputCTAccording toRule decline；R in formulaDFor detecting circuit equivalent resistance time in the conduction state, C
For the capacitance of high-frequency filter capacitor in detecting circuit；
In the t+T-τ moment, the voltage V of described detecting circuit outputCT(t+T-τ)＞ VTH, then detecting circuit output
Voltage VCTAccording toRule rises, R3 be detecting circuit when being in cut-off state etc.
Effect resistance；
In the t+T moment, the voltage V of detecting circuit outputCT(t+T)＜ VBIAS, the then voltage V of detecting circuit outputCT
According toRule decline；
Voltage V in the output of t+2T-τ moment detecting circuitCT(t+2T-τ)＞ VTH；
Voltage V in the output of t+2T moment detecting circuitCT(t+2T)＜ VCT(t+T), by above-mentioned moment iterative cycles,
The voltage of each cycle detecting circuit output presents progressively downward trend；
Until t+ (m-1) T moment, the voltage V of described detecting circuit outputCT(t+(m-1)T)＞ VTH, then detection electricity
The voltage V of road outputCTAccording toRule decline；
In the t+mT-τ moment, the voltage V of detecting circuit outputCT(t+mT-τ)＜ VTHAnd in the t+mT moment, described inspection
The voltage V of wave circuit outputCT(t+mT)＜ VTH, described VTHInput threshold level for inverter group.
In present embodiment, when detecting circuit does not receives pulse signal or in frequency f specified and dutycycle τ
In the case of the pulse number that continuously receives less than setting m (m > 1), after inverted device negates and drives
Output makes bus driver be in the level value of high resistant；Namely series resistance R1 and detecting circuit are on
Equivalent resistance R during stateDAnd with the capacitance-resistance charge-discharge circuit coupling electric capacity C1 composition m frequency be
F dutycycle is under the signal function of τ, the level V of detecting circuit outputCTStill it is not below the thresholding electricity of phase inverter
Flat VTH。
Present embodiment requires when the internal resistance R2 of low pressure biasing circuit is in cut-off state less than detecting circuit
The 1/100 of equivalent resistance R3, equivalent resistance R when described detecting circuit is in the conduction stateDLess than detection electricity
1/100 of equivalent resistance R3 when road is in cut-off state.
The described storage capacitor C3 in low pressure biasing circuit is more than the discharge and recharge equivalent capacity in detecting circuit
10 times of C2, the voltage of output is VCT；It is output as high level, and V not receiving detection pulsedCT＞ VTH；
Under bus driver is at high level state, it is in high resistant, then requires the number of phase inverter in inverter group
For even number；Under bus driver is at low level state, it is in high resistant, then requires phase inverter in inverter group
Number is odd number；V in formulaTHInput threshold level for phase inverter.
Capacitance C1 of the coupling electric capacity described in present embodiment meets more than the discharge and recharge equivalent electric in detecting circuit
Hold C2 2 times.The voltage of low pressure biasing circuit output is VBIAS, do not receive detection pulse at detecting circuit
Time be output as high level, and VBIAS＞ VTH。
Described in present embodiment in the upper electric control system of multi-controller, master controller can be by total line traffic control
The circuit processed control to bus driver, it is achieved multiple communications from controller and data are exchanged.Powering on
During, bus driver output keeps high-impedance state, on the one hand avoids output type end in power up
Mouth is connected, with output type port, the risk causing Short-Circuit High Current even to burn port；On the other hand, due to
It is output as high resistant, it is to avoid the protection diode of director port forms latent logical loop, shadow in power up
Ring the control of electrifying timing sequence.
Series resistance described in present embodiment uses commercially available conventional, electric-resistance, and series capacitance uses commercially available general
Energising is held；Described detecting circuit uses diode negative sense detecting circuit；Inverter group uses audion composition
Negative circuit；Described low pressure biasing circuit uses electric resistance partial pressure to amplify the circuit of capacitor filtering.
Claims (8)
1. the upper electric control system of multi-controller, including master controller, multiple bus control circuit, Duo Gezong
Line drive and multiple from controller；Bus driver is carried out by described master controller by bus control circuit
Control, it is achieved exchange from communication and the data of controller；It is characterized in that, described bus control circuit includes
Series resistance R1, coupling electric capacity C1, detecting circuit, inverter group and low pressure biasing circuit；
The square-wave signal of master controller input is concatenated resistance R1 and coupling electric capacity C1 and is sent to detecting circuit,
Low pressure biasing circuit provides bias level for detecting circuit；
When detecting circuit do not receive pulse signal or the pulse frequency that continuously receives be f (1/T), dutycycle be
When τ and pulse number are less than setting m；The signal inverted device group of detecting circuit output negates and drives
After Dong, output makes bus driver be in the level value of high resistant；
The continuous impulse frequency received when described detecting circuit is f (1/T), dutycycle is τ and pulse number reaches
During to setting m, bus driver releases high-impedance state；Described m > 1.
The upper electric control system of multi-controller the most according to claim 1, it is characterised in that described inspection
The work process of wave circuit is:
Setting described detecting circuit and receive moment corresponding to first pulse as t, the continuous impulse number of reception is
M, frequency are f (1/T), the pulse period is T and dutycycle is τ, and low pressure bias circuit output voltage is VBIAS,
The amplitude of low pressure biasing circuit input pulse signal is VmTime, then meet following relational expression:
Vdiode-0.1 ＜ Vm-VBIAS＜ Vdiode；Described VdiodeFor detecting circuit internal equivalent diode time in the conduction state
Pressure drop；
The voltage V of described detecting circuit outputCT=VBIAS, the then voltage V of detecting circuit outputCTAccording toRule decline；R in formulaDFor detecting circuit equivalent resistance time in the conduction state, C
For the capacitance of high-frequency filter capacitor in detecting circuit；
In the t+T-τ moment, the voltage V of described detecting circuit outputCT(t+T-τ)＞ VTH, then detecting circuit output
Voltage VCTAccording toRule rises, R3 be detecting circuit when being in cut-off state etc.
Effect resistance, described VTHInput threshold level for inverter group；
In the t+T moment, the voltage V of detecting circuit outputCT(t+T)＜ VBIAS, the then voltage V of detecting circuit outputCT
According toRule decline；
Voltage V in the output of t+2T-τ moment detecting circuitCT(t+2T-τ)＞ VTH, defeated at t+2T moment detecting circuit
The voltage V gone outCT(t+2T)＜ VCT(t+T), by above-mentioned moment iterative cycles, at the electricity of each cycle detecting circuit output
Pressure presents progressively downward trend；
Until t+ (m-1) T moment, the voltage V of described detecting circuit outputCT(t+(m-1)T)＞ VTH, then detection electricity
The voltage V of road outputCTAccording toRule decline；
In the t+mT-τ moment, the voltage V of detecting circuit outputCT(t+mT-τ)＜ VTHAnd in the t+mT moment, described inspection
The voltage V of wave circuit outputCT(t+mT)＜ VTH。
The upper electric control system of multi-controller the most according to claim 1 and 2, it is characterised in that institute
State detecting circuit in the conduction state time equivalent resistance RDIt is in equivalence during cut-off state less than detecting circuit
The 1/100 of resistance R3.
The upper electric control system of multi-controller the most according to claim 3, it is characterised in that low pressure is inclined
Storage capacitor C3 in circuits is more than 10 times of discharge and recharge equivalent capacity C2 in detecting circuit, in detection
Circuit is output as high level, and V when not receiving detection pulseBIAS＞ VTH。
The upper electric control system of multi-controller the most according to claim 4, it is characterised in that described low
1/100 of equivalent resistance R3 when the internal resistance R2 of pressure biasing circuit is in cut-off state less than detecting circuit.
The upper electric control system of multi-controller the most according to claim 5, it is characterised in that work as detection
When circuit does not receives pulse signal or the pulse number that receives less than setting m, detecting circuit output
After signal inverted device group negates and drives, output makes bus driver be in the level value of high resistant；That is:
Equivalent resistance R when series resistance R1 and detecting circuit are in the conduction stateDAnd form with coupling electric capacity C1
Capacitance-resistance charge-discharge circuit, be m in pulse protocol value, frequency is under the signal function that f dutycycle is τ, inspection
Wave circuit output voltage VCTThreshold level V more than inverter groupTH。
The upper electric control system of multi-controller the most according to claim 1, it is characterised in that work as bus
Driver is in high-impedance state under high level state, it is desirable in inverter group, the number of phase inverter is even number；
Under bus driver is at low level state, it is in high-impedance state, then requires the number of phase inverter in inverter group
For odd number.
The upper electric control system of multi-controller the most according to claim 1, it is characterised in that described coupling
Close the electric capacity C1 twice more than discharge and recharge equivalent capacity C2 in detecting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610348734.8A CN105843195B (en) | 2016-05-24 | 2016-05-24 | The upper electric control system of multi-controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610348734.8A CN105843195B (en) | 2016-05-24 | 2016-05-24 | The upper electric control system of multi-controller |
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| Publication Number | Publication Date |
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| CN105843195A true CN105843195A (en) | 2016-08-10 |
| CN105843195B CN105843195B (en) | 2019-02-01 |
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| CN201610348734.8A Expired - Fee Related CN105843195B (en) | 2016-05-24 | 2016-05-24 | The upper electric control system of multi-controller |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104811A (en) * | 2020-09-21 | 2020-12-18 | 中国科学院长春光学精密机械与物理研究所 | Low-latency multi-group imaging control system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4985903A (en) * | 1988-10-18 | 1991-01-15 | Ant Nachrichtentechnik Gmbh | Bus coupling circuit |
| CN1808284A (en) * | 2006-01-26 | 2006-07-26 | 上海微电子装备有限公司 | Serial data transmission system with multiple acquisition channels and control method thereof |
| CN102724092A (en) * | 2012-06-25 | 2012-10-10 | 西安热工研究院有限公司 | Profibus-DP communication protocol redundancy master station |
| CN105334178A (en) * | 2015-11-26 | 2016-02-17 | 无锡拓能自动化科技有限公司 | Harmful gas monitoring system based on detection rectifying circuit |
-
2016
- 2016-05-24 CN CN201610348734.8A patent/CN105843195B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4985903A (en) * | 1988-10-18 | 1991-01-15 | Ant Nachrichtentechnik Gmbh | Bus coupling circuit |
| CN1808284A (en) * | 2006-01-26 | 2006-07-26 | 上海微电子装备有限公司 | Serial data transmission system with multiple acquisition channels and control method thereof |
| CN102724092A (en) * | 2012-06-25 | 2012-10-10 | 西安热工研究院有限公司 | Profibus-DP communication protocol redundancy master station |
| CN105334178A (en) * | 2015-11-26 | 2016-02-17 | 无锡拓能自动化科技有限公司 | Harmful gas monitoring system based on detection rectifying circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104811A (en) * | 2020-09-21 | 2020-12-18 | 中国科学院长春光学精密机械与物理研究所 | Low-latency multi-group imaging control system |
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| CN105843195B (en) | 2019-02-01 |
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