CN105845663B - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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- CN105845663B CN105845663B CN201510014320.7A CN201510014320A CN105845663B CN 105845663 B CN105845663 B CN 105845663B CN 201510014320 A CN201510014320 A CN 201510014320A CN 105845663 B CN105845663 B CN 105845663B
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- 239000002184 metal Substances 0.000 claims abstract description 192
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- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor devices of present invention offer and preparation method thereof and electronic device, the semiconductor devices include:First substrate, the first substrate include the first metal interconnection structure and the first bonded layer;Second substrate; the second substrate includes the second metal interconnection structure, protective layer; and the silicon hole positioned at the second metal interconnection structure side; further include insulating layer, the diffusion impervious layer on the insulating layer, the metal interconnecting layer positioned at the diffusion barrier layer surface and the second bonded layer on the positive protective layer of the second substrate positioned at the through-silicon via sidewall and bottom; wherein, the insulating layer, diffusion impervious layer, metal interconnecting layer overall thickness be less than the silicon hole radius;The positive second bonding layer surface of second substrate is bonded layer surface with the first of the first substrate and is mutually bonded, and is formed with gap in the silicon hole.The semiconductor devices of the present invention, perfect heat-dissipating, and ensure that the electric conductivity of silicon hole.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics
Device.
Background technology
To adapt to the requirement of integrated circuit high density, compact, chip Stack Technology has become becoming for integrated circuit development
Gesture.The component manufactured with 3D encapsulation technologies, high packing density, will necessarily while the power density for making device improves
Cause to encapsulate the heat increase that unit volume accommodates.Under normal circumstances, the high temperature caused by Joule heat often substantially reduces collection
At performance/reliability of circuit devcie.The operating temperature of device increases, and crash rate can also increase.Unreasonable thermal design will
A series of integrity problem is induced, hot-spot, temperature distributing disproportionation etc. such as occurs.Therefore, it is manufactured using 3D encapsulation technologies
Component must just think better of the heat dissipation problem of packaging body.
Prior art discloses a kind of air duct interconnection structures for 3-D encapsulation, it is proposed that a kind of to be stacked in chip
The method for increasing air duct interconnection structure in structure removes the heat in packaging body from chip interior.However this side
Method has the drawback that air duct is non-conductive, can significantly reduce the RC retardation ratio performance of interconnection structure.
Therefore, it is necessary to propose a kind of new structure and production method, so as to solve the deficiencies in the prior art.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are provide a kind of semiconductor devices, feature exists in one embodiment of the invention
In, including:
First substrate is located at first metal interconnection structure on the first substrate surface, is located at the first substrate surface
The first bonded layer, and first bonded layer exposes part first metal interconnection structure;
Second substrate, the second substrate include positive second metal interconnection structure positioned at the second substrate, position
In the positive protective layer of the second substrate, and the second metal interconnection structure described in the protective layer expose portion, it is located at described
Second substrate front, and further include being located at the through-silicon via sidewall and bottom positioned at the silicon hole of the second metal interconnection structure side
The insulating layer in portion, and
Positioned at second metal interconnection structure exposed, the part second substrate positive and described insulating layer on
Diffusion impervious layer, be located at the diffusion barrier layer surface metal interconnecting layer, and be located at the positive guarantor of the second substrate
The second bonded layer on sheath, the second bonded layer exposure are located at the metal interconnecting layer on the second substrate surface, wherein
The insulating layer, diffusion impervious layer, metal interconnecting layer overall thickness be less than the silicon hole radius;
The positive second bonding layer surface of second substrate is bonded layer surface with the first of the first substrate and is mutually bonded,
The silicon hole is corresponding with first metal interconnection structure exposed, the metal interconnecting layer respectively with first gold medal
Belong to interconnection structure and the second metal interconnection structure is electrically connected, and gap is formed in the silicon hole.
Further, the material of the metal interconnecting layer is tungsten or aluminium or copper.
Further, it is formed with the first semiconductor devices in the first substrate, first semiconductor devices and described the
One metal interconnection structure is electrically connected.
Further, it is formed with the second semiconductor devices in the second substrate, second semiconductor devices and described the
Two metal interconnection structures are electrically connected.
Further, second bonded layer also covers the metal interconnecting layer in the silicon hole.
Further, the second bonded layer in the insulating layer, diffusion impervious layer, metal interconnecting layer and the silicon hole is total
Thickness is less than the radius of the silicon hole.
Further, the overall thickness of the second bonded layer in the silicon hole, metal interconnecting layer, diffusion impervious layer and insulating layer
Less than 2 μm.
Further, the diameter range of the silicon hole is 5~15 μm.
A kind of production method of semiconductor devices is provided in another embodiment of the present invention, including:
First substrate and second substrate are provided, wherein
It is formed with the first metal interconnection structure on the first substrate part surface, and is formed in the first substrate
First bonded layer on surface, and first bonded layer exposes part first metal interconnection structure, and
It is formed with the second metal interconnection structure, and covering second metal interconnection structure in the second substrate front
Protective layer;
The front of the protective layer and part second substrate is performed etching to form silicon hole;
Insulating layer is formed in the side wall of the silicon hole and bottom;
The protective layer is thinned, the second metal interconnection structure surface described in the expose portion;
In the insulating layer, the part protective layer and the second metal interconnection structure surface formation diffusion barrier exposed
Layer;
Metal interconnecting layer is formed in the diffusion barrier layer surface, wherein the insulating layer, diffusion impervious layer, metal are mutual
Even the overall thickness of layer is less than the radius of the silicon hole;
The second bonded layer, top surface and the metal interconnecting layer of second bonded layer are formed on the protective layer
Top surface flush;
The second bonded layer on the second substrate is bonded with the first bonded layer of the first substrate, and makes institute
The surface for stating exposed metal interconnecting layer is corresponding with first metal interconnection structure, and gap is formed in the silicon hole.
Further, second bonded layer also covers the metal interconnecting layer in the silicon hole, wherein the insulating layer,
The overall thickness of the second bonded layer in diffusion impervious layer, metal interconnecting layer and the silicon hole is less than the radius of the silicon hole.
Further, the silicon hole is formed using deep reaction ion etching technique or Bosch technique.
Further, the method for forming second bonded layer includes the following steps:
Deposition forms the second bonding material layer on the surface of the metal interconnecting layer and the protective layer of the exposure;
Chemical mechanical grinding step is executed, the surface of the metal interconnecting layer described in the expose portion.
Further, the material of first bonded layer and second bonded layer is silica.
Further, the bonding technology is silica melting bonding.
Further, the formation process of the metal interconnecting layer includes sputtering, plasma physical vapor deposition, high density etc.
Ion body chemical vapor phase growing, low-pressure chemical vapor deposition or atomic layer deposition.
Further, it is formed with the first semiconductor devices in the first substrate, first semiconductor devices and described the
One metal interconnection structure is electrically connected;The second semiconductor devices, second semiconductor devices are formed in the second substrate
It is electrically connected with second metal interconnection structure.
Further, the method that the protective layer is thinned is chemical mechanical grinding or lithographic method.
The embodiment of the present invention three provides a kind of electronic device, including semiconductor devices above-mentioned.
In conclusion production method according to the present invention, forms the silicon with gap between the substrate of bonding at two and leads to
Hole, the gap can be gone out the heat transfer generated in semiconductor substrate in device using air, and the heat dissipation of device is improved
Performance, while the metal interconnection structure of the substrate of bonding can be also electrically connected by silicon hole, ensure its electric conductivity.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
The production method that Figure 1A-Fig. 1 I show semiconductor device according to the invention implements cuing open for obtained device successively
Face schematic diagram;
Fig. 2 shows the process flow charts that the production method of semiconductor device according to the invention is implemented successively.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device in attached drawing is overturn, then, it is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
The production method of the semiconductor devices of the present invention is described in detail next, with reference to Figure 1A-Fig. 1 I and Fig. 2.
First, with reference to figure 1H, first substrate 10 is provided, there is the first semiconductor devices 101 in the first substrate 10,
It is formed with the first metal interconnection structure 103 on 10 part surface of the first substrate, and is formed in 10 table of the first substrate
First bonded layer 104 in face, and first bonded layer 104 exposes part first metal interconnection structure 103.
The first substrate 10 includes the first semiconductor substrate 100, and the first half in the first semiconductor substrate 100 lead
Body device 101 covers first semiconductor devices 101, the interlayer dielectric layer on 100 surface of the first semiconductor substrate (does not show
Go out), the interconnection structure 102 being located in the interlayer dielectric layer.
Illustratively, first semiconductor substrate 100 can be silicon substrate, germanium substrate, silicon-on-insulator substrate, glass
One kind in substrate, in the present embodiment, first semiconductor substrate 100 is silicon substrate.First semiconductor devices 101 can
Think one or more of MOS transistor, diode, memory, capacitance, resistance, inductance.In the present embodiment, with a MOS
Transistor illustrates the present invention as the first semiconductor devices 101.
The interlayer dielectric layer includes one or more layers dielectric layer, has interconnection structure in one or more layers described dielectric layer
102, the interconnection structure 102 includes metal layer and the conductive plunger between adjacent metal, utilizes the interconnection structure
102 are electrically connected first semiconductor devices 101 and the first metal interconnection structure 103.
First metal interconnection structure 103 can only include metal interconnecting layer, or metal interconnecting layer and conduction
The combination of plug.The material of first metal interconnection structure 103 can be well known to those skilled in the art any applicable
Metal material, such as copper, aluminium, tungsten etc..In the present embodiment, first metal interconnection structure 103 only includes that one layer of metal interconnects
Layer, first metal interconnection structure 103 are electrically connected with interconnection structure 102.
The material of first bonded layer 104 is silica, silicon nitride or silicon oxynitride etc., first bonded layer 104
It is interfered by outside for protecting the first metal interconnection structure 103 to exempt from.In the present embodiment, the material of first bonded layer 104
Material is silica.For subsequently needing to be bonded with second substrate on 104 surface of the first bonded layer, when using Direct Bonding work
When first bonded layer, 104 surface is bonded by skill with second substrate, since the material of the bonding face of second substrate is mostly
Silica, therefore, it can be achieved that silica-oxidation silicon bonding, technical maturity can reduce cost.
With reference to figure 1A, second substrate 20 is provided, the second semiconductor devices 201 is formed in the second substrate 20, in institute
It states 20 front of second substrate and is formed with the second metal interconnection structure 203, second metal interconnection structure 203 and described the second half
Conductor device 201 is electrically connected, and the protection for covering second metal interconnection structure 203 is formed in 20 front of second substrate
Layer.
Further, the second substrate 20 further includes the second semiconductor substrate 200, is located at the second semiconductor substrate 200
Second semiconductor devices 201 on surface, cover second semiconductor devices 201,200 surface of the second semiconductor substrate interlayer
Dielectric layer 202, the second metal interconnection structure of part 203 being located in the interlayer dielectric layer 202.
Illustratively, second semiconductor substrate 200 can be silicon substrate, germanium substrate, silicon-on-insulator substrate, glass
One kind in substrate, in the present embodiment, second semiconductor substrate 200 is silicon substrate.Second semiconductor devices 201 can
Think one or more of MOS transistor, diode, memory, capacitance, resistance, inductance.In the present embodiment, with a MOS
Transistor illustrates the present invention as the second semiconductor devices 201.
The interlayer dielectric layer 202 includes one or more layers dielectric layer, has part in one or more layers described dielectric layer
Second metal interconnection structure 203, second metal interconnection structure 203 include metal layer and leading between adjacent metal
Electric plug, it is using the second metal interconnection structure 203 that second semiconductor devices 201 is mutual with the metal in silicon hole later
Even layer is electrically connected.
Illustratively, metal can be only included positioned at positive the second metal interconnection structure of part of the second substrate 203
Interconnection layer, or the combination of metal interconnecting layer and conductive plunger.The material of second metal interconnection structure 203 can be
Any applicable metal material, such as copper, aluminium, tungsten well known to those skilled in the art etc..In the present embodiment, the interconnection of the second metal
Structure 203 is electrically connected with the metal interconnecting layer formed in silicon hole later.
The material of the protective layer 204 is silica, silicon nitride or silicon oxynitride etc., and the protective layer 204 is for protecting
Second metal interconnection structure 203 is exempted from interfered by outside.In the present embodiment, the material of the protective layer 204 is silica.
With reference to figure 1B, the front of the protective layer 204 and part second substrate 20 is performed etching to form silicon hole 205.
In the present embodiment, using deep reaction ion etching (DRIE) technique to the second base of the protective layer 204 and part
Plate 20 performs etching, and forms silicon hole 205, the diameter range of the silicon hole 205 is 5 μm~15 μm.The etching stopping in
In the second substrate 20, do not run through entire second substrate 20.
In other examples, the technique for forming the silicon hole can also be other any suitable techniques, such as Bosch
(Bosch) technique etc..
With reference to figure 1C, insulating layer 206 is formed in the side wall of the silicon hole 205 and bottom and 204 surface of protective layer.
Illustratively, the material of the insulating layer 206 is silica, and the method for forming the insulating layer 206 can be etc.
Gas ions enhance chemical vapor deposition, low-pressure chemical vapor deposition process, high density plasma CVD technique etc.,
Since above-mentioned depositing operation has preferable Step Coverage ability, insulating layer can be formed in the silicon hole of larger depth-to-width ratio.
With reference to figure 1D, the protective layer 204 is thinned, 203 surface of the second metal interconnection structure described in the expose portion;
Preferably, the method that the protective layer is thinned can be chemical mechanical grinding or lithographic method.In one example,
By etching technics, first the insulating layer 206 on 204 surface of protective layer is performed etching, is etching the protective layer 204,
The surface of the second metal interconnection structure 203 described in the expose portion.
In other examples, the method that chemical mechanical grinding can also be used realizes the insulation that removal is located on protective layer 204
Layer 206, and is thinned protective layer 204, the surface of the second metal interconnection structure 203 described in the expose portion.
By above-mentioned steps, also so that being only formed with insulating layer 206 in the side wall of silicon hole 205 and bottom.
With reference to figure 1E, in the insulating layer 206, the protective layer 204 and 204 table of the second metal interconnection structure exposed
Face forms diffusion impervious layer 207, metal interconnecting layer 208 is formed on 207 surface of the diffusion impervious layer, wherein the insulating layer
206, diffusion impervious layer 207, metal interconnecting layer 208 overall thickness be less than the silicon hole 205 radius.
Diffusion impervious layer 207 may be a silicon-containing layer, an one carbon-containing bed, nitrogenous layer, a hydrogeneous layer or a metal or metal
Compound layer.The material of metal or metal compound layer for example tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten,
Tungsten nitride, its alloy or its constituent.Diffusion impervious layer 207 is by such as physical vapour deposition (PVD), atomic layer deposition, rotary coating
(spin-on) processing procedure of deposition or other proper methods is formed.Diffusion impervious layer 207 can be in the temperature between -40~400 DEG C
With about formed under the pressure of 0.1~100 millitorr (mTorr).In addition, diffusion impervious layer 207 also may include multiple film layers.
The metal in metal interconnecting layer after the diffusion impervious layer 207 is used to prevent in silicon hole is diffused into second substrate 20.
The material of metal interconnecting layer 208 can be tungsten or the metal materials such as aluminium or copper, can pass through low-pressure chemical vapor deposition
(LPCVD), plasma auxiliary chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition
Product (ALD) or other advanced deposition techniques are formed.Preferably, the material of metal interconnecting layer 208 is tungsten material.
In the present embodiment, metal interconnecting layer 208 is partially filled with the silicon hole 205, so that the insulating layer 206, expansion
Dissipate barrier layer 207, metal interconnecting layer 208 overall thickness be less than the silicon hole 205 radius, there are gaps in silicon hole.
With reference to figure 1E, part diffusion impervious layer 207 and metal interconnecting layer 208 are removed, protective layer 204 described in expose portion
Surface.Any method well known to those skilled in the art can be used and carry out the removal technique, such as dry etching or wet method are carved
Erosion etc..
With reference to figure 1F, the second bonded layer 209 is formed on the surface of the protective layer and the metal interconnecting layer 208.
The material of second bonded layer 209 is silica, silicon nitride or silicon oxynitride etc., described the be located in through-hole
Two bonded layers 209 are for protect metal interconnecting layer 208 to exempt from interfered by outside, while the bonding after can be additionally used in.In this reality
It applies in example, the material of second bonded layer 209 is silica.
Later, with reference to figure 1G, chemical mechanical grinding is carried out, until the surface of the exposure metal interconnecting layer 208, to be formed
The second smooth bonded layer 209, exposed metal interconnecting layer 208 with the first metal interconnection structure 103 after being bonded for realizing electricity
Learn connection.
Control the second bonded layer 209, metal interconnecting layer 208, diffusion impervious layer 207 and the insulation in the silicon hole 205
The overall thickness of layer 206 is less than the radius of silicon hole 205, so that remaining with gap always in through-hole 205.Preferably, control
The overall thickness of the second bonded layer, metal interconnecting layer, diffusion impervious layer and insulating layer in the silicon hole is less than 2 μm.
With reference to figure 1I, the second bonded layer 209 on the second substrate 20 is bonded with the first of the first substrate 10
Layer 104 is bonded, and keeps the surface of the metal interconnecting layer 208 of the exposure corresponding with first metal interconnection structure 103,
Gap is formed in the silicon hole.
In the present embodiment, using the material of first bonded layer 104 as silica, the material of second bonded layer 209
For silica, it is bonded.Optionally, the bonding technology is silica melting bonding.The above method is only illustratively, also
The material of the first bonded layer and the second bonded layer can be reasonably selected according to bonding pattern.
After above-mentioned bonding steps, gap is formd in the silicon hole between first substrate 10 and second substrate 20, the sky
Gap can be gone out the heat transfer generated in semiconductor substrate in device using air, while for the metal on silicon hole surface
Interconnection layer 208 is electrically connected with the first metal interconnection structure and the second metal interconnection structure, therefore can also ensure silicon well
The electric conductivity of through-hole.
Also the back side of the second substrate is thinned using backgrind technique later, until exposing metal interconnects
The bottom surface of layer.
The production method proposed through the invention again can also be bonded multiple bases for including silicon hole proposed by the present invention successively
Plate, to realize the encapsulation to multiple substrates.While heat dissipation to semiconductor substrate using multiple silicon hole realizations with gap,
The electric conductivity of silicon hole can also be taken into account.
In conclusion production method according to the present invention, forms the silicon with gap between the substrate of bonding at two and leads to
Hole, the gap can be gone out the heat transfer generated in semiconductor substrate in device using air, and the heat dissipation of device is improved
Performance, while the metal interconnection structure of the substrate of bonding can be also electrically connected by silicon hole, ensure its electric conductivity.
With reference to Fig. 2, the process flow chart for a step of specific implementation mode of the invention is implemented successively is shown, for letter
The flow of entire manufacturing process is shown.
In step 201, first substrate and second substrate are provided, first is formed on the first substrate part surface
Metal interconnection structure, and it is formed in first bonded layer on the first substrate surface, and in second substrate front shape
At there is the second metal interconnection structure, the protective layer of second metal interconnection structure is covered;
In step 202, the front of the protective layer and part second substrate is performed etching to form silicon hole;
In step 203, insulating layer is formed in the side wall of the silicon hole and bottom;
In step 204, the protective layer is thinned, the second metal interconnection structure surface described in the expose portion;
In step 205, on the insulating layer, the part protective layer and the second metal interconnection structure surface exposed
Form diffusion impervious layer;
In step 206, metal interconnecting layer is formed in the diffusion barrier layer surface, wherein the insulating layer, diffusion
Barrier layer, metal interconnecting layer overall thickness be less than the silicon hole radius;
In step 207, the second bonded layer, the top surface of second bonded layer and institute are formed on the protective layer
The top surface for stating metal interconnecting layer flushes;
In a step 208, by the first bonded layer of the second bonded layer and the first substrate on the second substrate into
Line unit closes, and keeps the surface of the metal interconnecting layer of the exposure corresponding with first metal interconnection structure, in the silicon hole
Interior formation gap.
Embodiment two
In the following, the structure of semiconductor devices proposed by the present invention is described in detail with reference to figure 1I.
With reference to figure 1I, the semiconductor devices includes:First substrate 10 is located at first gold medal on 10 surface of the first substrate
Belong to interconnection structure 103, is located at first bonded layer 104 on 10 surface of the first substrate, and first bonded layer 104 exposes
Part first metal interconnection structure 103.
The first substrate 10 further includes the first semiconductor substrate 100, the first half be located in the first semiconductor substrate 100
Conductor device 101 covers first semiconductor devices 101, the interlayer dielectric layer on 100 surface of the first semiconductor substrate (does not show
Go out), the interconnection structure 102 being located in the interlayer dielectric layer.
Illustratively, first semiconductor substrate 100 can be silicon substrate, germanium substrate, silicon-on-insulator substrate, glass
One kind in substrate, in the present embodiment, first semiconductor substrate 100 is silicon substrate.First semiconductor devices 101 can
Think one or more of MOS transistor, diode, memory, capacitance, resistance, inductance.In the present embodiment, with a MOS
Transistor illustrates the present invention as the first semiconductor devices 101.
The interlayer dielectric layer includes one or more layers dielectric layer, has interconnection structure in one or more layers described dielectric layer
102, the interconnection structure 102 includes metal layer and the conductive plunger between adjacent metal, utilizes the interconnection structure
102 are electrically connected first semiconductor devices 101 and the first metal interconnection structure 103.
First metal interconnection structure 103 can only include metal interconnecting layer, or metal interconnecting layer and conduction
The combination of plug.The material of first metal interconnection structure 103 can be well known to those skilled in the art any applicable
Metal material, such as copper, aluminium, tungsten etc..In the present embodiment, first metal interconnection structure 103 only includes that one layer of metal interconnects
Layer, first metal interconnection structure 103 are electrically connected with interconnection structure 102.
The material of first bonded layer 104 is silica, silicon nitride or silicon oxynitride etc., first bonded layer 104
It is interfered by outside for protecting the first metal interconnection structure 103 to exempt from.In the present embodiment, the material of first bonded layer 104
Material is silica.The medium that first bonded layer 104 is also bonded as the first substrate 10 with second substrate 20.
The semiconductor devices further includes second substrate 20, and the second substrate 20 includes being located at the second substrate 20 just
Second metal interconnection structure 203 in face is located at 20 positive protective layer 204 of the second substrate, and the protective layer 204 exposes
Part second metal interconnection structure 203 is located at 20 front of the second substrate, and is located at the second metal interconnection structure 203
The diameter range of the silicon hole 205 of side, the silicon hole is 5~15 μm.
Further, the second substrate 20 further includes the second semiconductor substrate 200, is located at the second semiconductor substrate 200
Second semiconductor devices 201 on surface, cover second semiconductor devices 201,200 surface of the second semiconductor substrate interlayer
Dielectric layer 202, the second metal interconnection structure of part 203 being located in the interlayer dielectric layer 202.
Illustratively, second semiconductor substrate 200 can be silicon substrate, germanium substrate, silicon-on-insulator substrate, glass
One kind in substrate, in the present embodiment, second semiconductor substrate 200 is silicon substrate.Second semiconductor devices 201 can
Think one or more of MOS transistor, diode, memory, capacitance, resistance, inductance.In the present embodiment, with a MOS
Transistor illustrates the present invention as the second semiconductor devices 201.
The interlayer dielectric layer 202 includes one or more layers dielectric layer, has part in one or more layers described dielectric layer
Second metal interconnection structure 203, second metal interconnection structure 203 include metal layer and leading between adjacent metal
Electric plug is interconnected the metal in second semiconductor devices 201 and silicon hole 205 using the second metal interconnection structure 203
Layer 208 is electrically connected.
Illustratively, metal can be only included positioned at positive the second metal interconnection structure of part of the second substrate 203
Interconnection layer, or the combination of metal interconnecting layer and conductive plunger.The material of second metal interconnection structure 203 can be
Any applicable metal material, such as copper, aluminium, tungsten well known to those skilled in the art etc..In the present embodiment, the interconnection of the second metal
Structure 203 is electrically connected with the metal interconnecting layer formed in silicon hole later.
Further include the insulating layer 206 positioned at 205 side wall of the silicon hole and bottom surface, positioned at second exposed
Diffusion impervious layer 207 on the positive and described insulating layer 206 of metal interconnection structure 203, the part second substrate 20;It is located at
The metal interconnecting layer 208 on 207 surface of the diffusion impervious layer, and on 20 positive protective layer 204 of the second substrate
The second bonded layer 209, second bonded layer 209 exposes the top surface of the metal interconnecting layer 208.Optionally, the insulation
Layer 206, diffusion impervious layer 207, metal interconnecting layer 208 overall thickness be less than the silicon hole 205 radius.Namely the silicon is logical
There is gap in hole 205.
The material of the insulating layer 206 is silica, and the method for forming the insulating layer 206 can be plasma enhancing
Chemical vapor deposition, low-pressure chemical vapor deposition process, high density plasma CVD technique etc..
Diffusion impervious layer 207 may be a silicon-containing layer, an one carbon-containing bed, nitrogenous layer, a hydrogeneous layer or a metal or metal
Compound layer.The material of metal or metal compound layer for example tantalum, tantalum nitride, titanium, titanium nitride, zirconium nitride, titanium nitride zirconium, tungsten,
Tungsten nitride, its alloy or its constituent.Illustratively, the material of the metal interconnecting layer is tungsten or aluminium or copper.
In one example, second bonded layer 209 also covers the metal interconnecting layer 208 in the silicon hole 205.Institute
The overall thickness for stating the second bonded layer in insulating layer, diffusion impervious layer, metal interconnecting layer and the silicon hole is logical less than the silicon
The radius in hole.Preferably, the total thickness of the second bonded layer, metal interconnecting layer, diffusion impervious layer and insulating layer in the silicon hole
Degree is less than 2 μm.
Optionally, the material of second bonded layer 209 is silica, silicon nitride or silicon oxynitride etc..
Continue to refer to figure 1 I, 20 positive second bonded layer, 209 surface of the second substrate and the first substrate 10
First bonded layer, 104 surface is mutually bonded, and the silicon hole 205 is corresponding with the first metal interconnection structure 103 exposed, in institute
State and be formed with gap in silicon hole, the metal interconnecting layer 208 respectively with first metal interconnection structure, 103 and second metal
Interconnection structure 203 is electrically connected.
The semiconductor devices of the present invention, is formed with gap in silicon hole, is conducive to the heat in semiconductor substrate from gap
Middle transmission, perfect heat-dissipating are electrically connected between the metal interconnecting layer of silicon hole and the two of bonding substrates, ensure that electric conductivity
Energy.
Embodiment three
In addition the present invention also provides a kind of electronic device comprising the semiconductor devices described in embodiment two, or including
The semiconductor devices made of method in embodiment one.
Due to including semiconductor devices have good heat dissipation effect and performance, the electronic device equally have it is above-mentioned excellent
Point.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, can also be to have
The intermediate products of above-mentioned semiconductor device, such as:Cell phone mainboard etc. with the integrated circuit.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (18)
1. a kind of semiconductor devices, which is characterized in that including:
First substrate is located at first metal interconnection structure on the first substrate surface, is located at the of the first substrate surface
One bonded layer, and first bonded layer exposes part first metal interconnection structure;
Second substrate, the second substrate include positive second metal interconnection structure positioned at the second substrate, are located at institute
The positive protective layer of second substrate, and the second metal interconnection structure described in the protective layer expose portion are stated, is located at described second
Substrate front side, and further include being located at the through-silicon via sidewall and bottom positioned at the silicon hole of the second metal interconnection structure side
Insulating layer, and
Positioned at second metal interconnection structure exposed, the part second substrate positive and described insulating layer on expansion
Barrier layer is dissipated, is located at the metal interconnecting layer of the diffusion barrier layer surface, and be located at the positive protective layer of the second substrate
On the second bonded layer, second bonded layer exposure is located at the metal interconnecting layer on the second substrate surface, wherein described
Insulating layer, diffusion impervious layer, metal interconnecting layer overall thickness be less than the silicon hole radius;
The positive second bonding layer surface of second substrate is bonded layer surface with the first of the first substrate and is mutually bonded, described
Silicon hole is corresponding with first metal interconnection structure exposed, and the metal interconnecting layer is mutual with first metal respectively
Connection structure and the second metal interconnection structure are electrically connected, and are formed with gap in the silicon hole.
2. semiconductor devices as described in claim 1, which is characterized in that the material of the metal interconnecting layer be tungsten or aluminium or
Copper.
3. semiconductor devices as described in claim 1, which is characterized in that be formed with the first semiconductor device in the first substrate
Part, first semiconductor devices are electrically connected with first metal interconnection structure.
4. semiconductor devices as described in claim 1, which is characterized in that be formed with the second semiconductor device in the second substrate
Part, second semiconductor devices are electrically connected with second metal interconnection structure.
5. semiconductor devices as described in claim 1, which is characterized in that second bonded layer also covers in the silicon hole
Metal interconnecting layer.
6. semiconductor devices as claimed in claim 5, which is characterized in that the insulating layer, diffusion impervious layer, metal interconnecting layer
It is less than the radius of the silicon hole with the overall thickness of the second bonded layer in the silicon hole.
7. semiconductor devices as claimed in claim 6, which is characterized in that the second bonded layer, the metal in the silicon hole are mutual
Even the overall thickness of layer, diffusion impervious layer and insulating layer is less than 2 μm.
8. semiconductor devices as described in claim 1, which is characterized in that the diameter range of the silicon hole is 5 μm~15 μm.
9. a kind of production method of semiconductor devices, which is characterized in that including:
First substrate and second substrate are provided, wherein
It is formed with the first metal interconnection structure on the first substrate part surface, and is formed in the first substrate surface
The first bonded layer, and first bonded layer exposes part first metal interconnection structure, and
It is formed with the second metal interconnection structure, and the guarantor of covering second metal interconnection structure in the second substrate front
Sheath;
The front of the protective layer and part second substrate is performed etching to form silicon hole;
Insulating layer is formed in the side wall of the silicon hole and bottom;
The protective layer is thinned, the second metal interconnection structure surface described in the expose portion;
In the insulating layer, the part protective layer and the second metal interconnection structure surface formation diffusion impervious layer exposed;
Metal interconnecting layer is formed in the diffusion barrier layer surface, wherein the insulating layer, diffusion impervious layer, metal interconnecting layer
Overall thickness be less than the silicon hole radius;
The second bonded layer, the top of the top surface and the metal interconnecting layer of second bonded layer are formed on the protective layer
Face flushes;
The second bonded layer on the second substrate is bonded with the first bonded layer of the first substrate, and is made described sudden and violent
The surface of the metal interconnecting layer of dew is corresponding with first metal interconnection structure, and gap is formed in the silicon hole.
10. production method as claimed in claim 9, which is characterized in that second bonded layer also covers in the silicon hole
Metal interconnecting layer, wherein the second bonded layer in the insulating layer, diffusion impervious layer, metal interconnecting layer and the silicon hole
Overall thickness be less than the silicon hole radius.
11. production method as claimed in claim 9, which is characterized in that use deep reaction ion etching technique or Bosch technique
Form the silicon hole.
12. production method as claimed in claim 10, which is characterized in that the method for forming second bonded layer includes following
Step:
Deposition forms the second bonding material layer on the surface of the metal interconnecting layer and the protective layer of the exposure;
Chemical mechanical grinding step is executed, the surface of the metal interconnecting layer described in the expose portion.
13. production method as claimed in claim 9, which is characterized in that first bonded layer and second bonded layer
Material is silica.
14. production method as claimed in claim 9, which is characterized in that the bonding technology is silica melting bonding.
15. production method as claimed in claim 9, which is characterized in that the formation process of the metal interconnecting layer include sputtering,
Plasma physical vapor deposition, high density plasma CVD, low-pressure chemical vapor deposition or atomic layer deposition.
16. production method as claimed in claim 9, which is characterized in that be formed with the first semiconductor device in the first substrate
Part, first semiconductor devices are electrically connected with first metal interconnection structure;It is formed with second in the second substrate
Semiconductor devices, second semiconductor devices are electrically connected with second metal interconnection structure.
17. production method as claimed in claim 9, which is characterized in that the method that the protective layer is thinned is ground for chemical machinery
Mill or lithographic method.
18. a kind of electronic device, which is characterized in that include the semiconductor devices as described in any one of claim 1-8.
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