CN105827237B - delay circuit and voltage controlled oscillator - Google Patents
delay circuit and voltage controlled oscillator Download PDFInfo
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- CN105827237B CN105827237B CN201510006052.4A CN201510006052A CN105827237B CN 105827237 B CN105827237 B CN 105827237B CN 201510006052 A CN201510006052 A CN 201510006052A CN 105827237 B CN105827237 B CN 105827237B
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Abstract
A kind of delay circuit and voltage controlled oscillator, wherein the delay circuit includes amplifying unit, adjusts unit and load unit；The amplifying unit is coupled to the input terminal and output end of the delay circuit, the output end, supply voltage and control voltage, the load unit that the adjusting unit is respectively coupled to the delay circuit are respectively coupled to the output end and supply voltage of the delay circuit；Unit is adjusted, is suitable for adjusting the charging and discharging currents of the delay circuit；Amplifying unit is suitable for amplifying the output voltage of the delay circuit；Load unit is suitable for the adjusting unit and provides negative impedance.By the delay circuit and the voltage controlled oscillator, the phase noise of delay circuit can be reduced and realize low voltage controlled gain.
Description
Technical field
The present invention relates to electronic circuit technology field more particularly to a kind of delay circuits and voltage controlled oscillator.
Background technology
Phaselocked loop (Phase-Locked Loop, PLL) is the core circuit in various types of communication, clock chip, output letter
Number pectrum noise, shake, the indexs such as spuious can be directly related to system performance.Voltage controlled oscillator is the important composition in PLL
Part.When control voltage changes in a certain range, the signal output within the scope of cline frequency can be obtained.Ring oscillator
It is the main realization method of one of which, feedback control loop generation oscillatory voltage signals is formed by the way that delay circuit joins end to end.Ring
Shape oscillator includes single-ended and two kinds of circuit structures of difference.
Input control voltage is converted to the adjusting unit portion of electric current in the delay circuit of existing ring oscillator design
Point, it is difficult to needed for covering when frequency range, realize smaller phase noise.
Invention content
The embodiment of the present invention solves the problems, such as it is how to reduce the phase noise of delay circuit.
To solve the above problems, the embodiment of the present invention provides a kind of delay circuit, including：Amplifying unit, adjust unit with
And load unit；The amplifying unit is coupled to the input terminal and output end of the delay circuit, and the adjusting unit distinguishes coupling
The output end, supply voltage and control voltage, the load unit for being connected to the delay circuit are respectively coupled to the delay
The output end and supply voltage of circuit；Unit is adjusted, is suitable for adjusting the charging and discharging currents of the delay circuit；Amplifying unit,
Suitable for amplifying the output voltage of the delay circuit；Load unit is suitable for the adjusting unit and provides negative impedance.
Optionally, the adjusting unit includes：First regulator unit and the second regulator unit；First regulator
Unit is coupled to the first output end of the control voltage, supply voltage and the delay circuit；The second regulator list
Member is coupled to the second output terminal of the control voltage, supply voltage and the delay circuit.
Optionally, first regulator unit includes：The first transistor and second transistor；The first transistor
Control terminal is coupled to the control voltage, and input terminal is coupled to supply voltage, and output end is coupled to the first of the delay circuit
Output end；The control terminal of the second transistor is coupled to the control voltage, and input terminal is coupled to the of the delay circuit
One output end, output end ground connection.
Optionally, second regulator unit includes：Third transistor and the 4th transistor；The third transistor
Control terminal is coupled to the control voltage, and input terminal is coupled to supply voltage, and output end is coupled to the second of the delay circuit
Output end；The control terminal of 4th transistor is coupled to the control voltage, and input terminal is coupled to the of the delay circuit
Two output ends, output end ground connection.
Optionally, the load unit includes：5th transistor and the 6th transistor；The control terminal of 5th transistor
It is coupled to the second output terminal of the delay circuit, input terminal is coupled to supply voltage, and output end is coupled to the delay circuit
The first output end；The control terminal of 6th transistor is coupled to the first output end of the delay circuit, input terminal coupling
In supply voltage, output end is coupled to the second output terminal of the delay circuit.
Optionally, the load unit further includes：7th transistor and the 8th transistor；The control of 7th transistor
End is coupled to the second output terminal of the delay circuit, input end grounding, and it is first defeated to be coupled to the delay circuit for output end
Outlet；The control terminal of 8th transistor is coupled to the first output end of the delay circuit, input end grounding, output end coupling
It is connected to the second output terminal of the delay circuit.
Optionally, the amplifying unit includes：9th transistor；The control terminal of 9th transistor is coupled to described prolong
When circuit first input end, input end grounding, output end is coupled to the first output end of the delay circuit.
Optionally, the amplifying unit further includes：Tenth transistor；The control terminal of tenth transistor is coupled to described
Second input terminal of delay circuit, input end grounding, output end are coupled to the second output terminal of the delay circuit.
In order to solve the above technical problems, the embodiment of the invention also discloses a kind of voltage controlled oscillator, including it is above-mentioned
Delay circuit；At least two delay circuit joins end to end into positive feedback.
Compared with prior art, the technical solution of the embodiment of the present invention has the following advantages：
Negative impedance is provided for the adjusting unit of the delay circuit by load unit, enhances the delay circuit defeated
The equiva lent impedance of outlet makes described to enhance gain of the delay circuit in the intermediate state that output voltage is overturn
The overturning point slope of delay circuit is precipitous, realizes quick overturning, therefore can generate lower phase noise.
Further, by adjusting the charge and discharge time of the delay circuit by two transistors in regulator unit,
Realize low voltage controlled gain.
Description of the drawings
Fig. 1 is a kind of existing delay circuit structural schematic diagram；
Fig. 2 is a kind of structural schematic diagram of delay circuit of the embodiment of the present invention；
Fig. 3 is a kind of electrical block diagram of delay circuit with differential configuration of the embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of voltage controlled oscillator of the embodiment of the present invention.
Specific implementation mode
Fig. 1 show a kind of delay circuit structure.It adjusts the RC of output node ON and OP by VVC voltage variable capacitance
Constant to realize Variable delay, and reduces delay by being connected on the resistive device that phase inverter 810 and phase inverter 820 drain
Susceptibility of the circuit to temperature and supply voltage.But the introducing of this resistive device can lead to the deterioration of oscillator phase.
Input control voltage is converted to the adjusting cell mesh of electric current in the delay circuit, it is difficult to needed for covering when frequency range,
Realize smaller phase noise.
Fig. 2 shows a kind of structural schematic diagrams of delay circuit in the embodiment of the present invention.As shown in Fig. 2, the delay
Circuit may include：Amplifying unit 101 adjusts unit 102 and load unit 103.The amplifying unit 101 is coupled to described
The input terminal IN and output end OUT of delay circuit, the output end for adjusting unit 102 and being respectively coupled to the delay circuit
OUT, supply voltage Vdd and control voltage Vc, the load unit 103 are respectively coupled to the output end of the delay circuit
OUT and supply voltage Vdd.
Amplifying unit 101 is suitable for amplifying the output voltage of the delay circuit.
Unit 102 is adjusted, is suitable for adjusting the charging and discharging currents of the delay circuit, and then correspondingly realizes and prolongs described in adjusting
When circuit RC charge constants.
Load unit 103 is suitable for the adjusting unit 102 and provides negative impedance.It is described by the load unit 103
The adjusting unit of delay circuit provides negative impedance, can enhance the delay circuit output end OUT equiva lent impedance, to increase
Strong gain of the delay circuit in the intermediate state that output voltage is overturn, makes the overturning point slope steepness of the delay circuit
It is high and steep, quick overturning is realized, therefore lower phase noise can be generated.
In specific implementation, the delay circuit can be applied in the voltage controlled oscillator of PLL.Ring oscillator is voltage-controlled
A kind of main realization method of oscillator, including single-ended and two kinds of circuit structures of difference.Since differential configuration has preferable resist
Noise immune, therefore differential configuration may be used in the delay circuit of the embodiment of the present invention, to be preferably applied for high-speed pll
In.
Fig. 3 shows a kind of structural schematic diagram of delay circuit with differential configuration in the embodiment of the present invention.Such as Fig. 3
Shown, the delay circuit may include adjusting unit, load unit 303 and amplifying unit 304.The tune of the delay circuit
Section unit may include the first regulator unit 301 and the second regulator unit 302, and first regulator unit 301 couples
In control voltage Vc, supply voltage Vdd and the first output end OUTn of the delay circuit；Second regulator unit
302 are coupled to the second output terminal OUTp of control voltage Vc, supply voltage Vdd and the delay circuit.
The output voltage of the input voltage of the first input end INp of the delay circuit and the first output end OUTn are difference
The relationship of reverse phase.Correspondingly, the output of the input voltage and second output terminal OUTp of the second input terminal INn of the delay circuit
Voltage is also the relationship of difference reverse phase.
In specific implementation, first regulator unit 301 may include：The first transistor M1 and second transistor
M2.The control terminal of the first transistor M1 is coupled to control voltage Vc, and input terminal is coupled to supply voltage Vdd, output end coupling
It is connected to the first output end OUTn of the delay circuit.The control terminal of the second transistor M2 is coupled to control voltage Vc, defeated
Enter the first output end OUTn that end is coupled to the delay circuit, output end ground connection.
In above-mentioned specific implementation, the first transistor M1 can be PMOS tube, and the second transistor M2 can be with
It is NMOS tube.
In specific implementation, corresponding with first regulator unit 301, second regulator unit 302 can
To include：Third transistor M3 and the 4th transistor M4；The control terminal of the third transistor M3 is coupled to control voltage Vc, defeated
Enter end and be coupled to supply voltage Vdd, output end is coupled to the second output terminal OUTp of the delay circuit；4th transistor
The control terminal of M4 is coupled to control voltage Vc, and input terminal is coupled to the second output terminal OUTp of the delay circuit, output termination
Ground.
In above-mentioned specific implementation, the third transistor M3 can be PMOS tube, and the 4th transistor M4 can be with
It is NMOS tube.
The control voltage Vc is a continuously varying analog signal, can pass through 301 He of the first regulator unit
Second regulator unit 302 controls the delay time of the delay circuit, i.e. charge and discharge electrical time constant RC.With the control
The change of voltage Vc voltage values processed, the first transistor M1, second transistor M2, third transistor M3 and the 4th transistor
Mutual conductance Gm, the output impedance Ro of M4 will change, to adjust the delay circuit the first output end OUTn and
The charge and discharge electrical time constant of second output terminal OUTp.
In specific implementation, the load unit 303 of the delay circuit may include：5th transistor M5 and the 6th crystal
Pipe M6；The control terminal of the 5th transistor M5 is coupled to the second output terminal OUTp of the delay circuit, and input terminal is coupled to
Supply voltage Vdd, output end are coupled to the first output end OUTn of the delay circuit；The control terminal of the 6th transistor M6
It is coupled to the first output end OUTn of the delay circuit, input terminal is coupled to supply voltage Vdd, and output end is coupled to described prolong
When circuit second output terminal OUTp.The 5th transistor M5 and the 6th transistor M6 cross-couplings, functionally etc.
It imitates in a negative resistance, as the load of the delay circuit amplifying unit 304, codetermines and adjust the delay circuit
Reversal rate.
In above-mentioned specific implementation, the 5th transistor M5 and shown 6th transistor M6 can be PMOS tube.
In specific implementation, the load unit 303 can also include：7th transistor M7 and the 8th transistor M8.Institute
The control terminal for stating the 7th transistor M7 is coupled to the second output terminal OUTp of the delay circuit, input end grounding, output end coupling
It is connected to the first output end OUTn of the delay circuit；The control terminal of the 8th transistor M8 is coupled to the delay circuit
First output end OUTn, input end grounding, output end are coupled to the second output terminal OUTp of the delay circuit.Described 7th is brilliant
Body pipe M7 and the 8th transistor M8 constitutes negative resistance to pipe, can play the high frequency overturning speed of enhancing time-delay unit circuit
Degree improves the effect of oscillator starting of oscillation ability.
In above-mentioned specific implementation, the 7th transistor M7 can be NMOS tube, and the 8th transistor M8 can be with
It is NMOS tube, forms NMOS negative resistances to pipe.
In specific implementation, the amplifying unit 304 may include：9th transistor M9；The 9th transistor M9's
Control terminal is coupled to the first input end INp of the delay circuit, input end grounding, and output end is coupled to the delay circuit
First output end OUTn.
In specific implementation, correspondingly, the amplifying unit 304 can also include：Tenth transistor M10；Described tenth
The control terminal of transistor M10 is coupled to the second input terminal INn of the delay circuit, input end grounding, and output end is coupled to institute
State the second output terminal OUTp of delay circuit.
The 9th transistor M9 and the tenth transistor M10, to pipe, amplifies the delay circuit as input mutual conductance
Output voltage.In specific implementation, the 9th transistor M9 can be NMOS tube, and the tenth transistor M10 can be
NMOS tube.
Hereafter illustrate the achieved low phase of the delay circuit by two states residing for the delay circuit
Position noise and low pressure control gain effect：
(1) when the input voltage of the first input end INp of the delay circuit, the input electricity of the second input terminal INnInn
Pressure, the output voltage of the first output end OUTn and second output terminal OUTp output voltage approximately equal, and all close to
When VDD/2, the delay circuit is in the overturning critical condition of output voltage at this time, and all transistors are all in saturation region.
To include the first transistor M1, second transistor M2, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7M7, the 8th
Transistor M8M8, the 9th transistor M9 left half of circuit for, circuit small-signal gain is Gm9*Zoutn.Wherein, Gm9 is
The mutual conductance of 9th transistor M9, Zoutn are the equiva lent impedance of the delay circuit the first output end OUTn output ends.Because at this time
The first transistor M1 and second transistor M2 have higher resistance all in saturation region.Simultaneously because two groups of negative resistances are to pipe
5th transistor M5 and the 6th transistor M6, the 7th transistor M7M7 and the 8th transistor M8M8 introduce negative impedance, thus into
One step enhances the equiva lent impedance Zoutn of the first output end OUTn of the delay circuit, so that the delay circuit exists
The intermediate state of overturning have very strong gain, this quick switching process, precipitous overturning point slope accordingly bring compared with
Low phase noise.
Wherein U is the migration rate of transistor carrier, and Cox is transistor unit area gate oxide capacitance, and W/L is crystalline substance
Body pipe breadth length ratio, Vgs-Vth are overdrive voltage.Therefore the breadth length ratio W/L of the first transistor M1 determines charging current at this time
Size namely charge constant.Similarly, discharge time constant is determined by second transistor M2 pipes.The charging and discharging
Time constant has codetermined the frequency of oscillation of oscillator.
Therefore to sum up, can be controlled by the way that the wide W and long L of the first transistor M1 and second transistor M2 is arranged
The size of the delay circuit charging current, to obtain smaller voltage controlled gain.In addition, in the delay of existing ring oscillator
In circuit, control voltage Vc only controls a transistor, such as the grid of NMOS or PMOS.The control voltage of the embodiment of the present invention
Vc controls the first transistor M1 and second transistor M2 simultaneously, therefore can adjust the W/L parameters of M1 and M2 in proportion to realize
The control voltage Vc is as good linear in having in 0~VDD in big voltage range.
It in specific implementation, can be according to the analog result of circuit simulation, to the first transistor M1 and described second
Transistor M2 wide W and long L parameters do setting and type selecting, and the delay circuit is made to have low voltage controlled gain and good linear
Degree.
The type of above-mentioned transistor is not limited to the type shown by the present embodiment, can be according to the need of practical application
Change, as long as same control logic can be realized.It is understood that transistor types shown in the present embodiment or
Other variations all belong to the scope of protection of the present invention.
The embodiment of the invention also discloses a kind of voltage controlled oscillators.The voltage controlled oscillator includes at least two above-mentioned prolonging
When circuit.At least two delay circuit joins end to end into positive feedback.As shown in figure 4, for by two 401 Hes of delay circuit
The voltage controlled oscillator of 402 compositions.
In specific implementation, corresponding setting can be done in the voltage controlled oscillator according to the needs of application.Such as it wants
When to seek the output waveform of the voltage controlled oscillator be square wave of the duty ratio close to 50%, it can pass through and level-one phase inverter is set carry out
Corresponding Shape correction.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of delay circuit, which is characterized in that including：Amplifying unit adjusts unit and load unit；
The amplifying unit is coupled to the input terminal and output end of the delay circuit, and the adjusting unit is respectively coupled to described
The output end of delay circuit, supply voltage and control voltage, the load unit are respectively coupled to the defeated of the delay circuit
Outlet and supply voltage；
Unit is adjusted, is suitable for adjusting the charging and discharging currents of the delay circuit；
Amplifying unit is suitable for amplifying the output voltage of the delay circuit；
Load unit is suitable for the adjusting unit and provides negative impedance；
The adjusting unit includes：First regulator unit and the second regulator unit；First regulator unit is coupled to
First output end of the control voltage, supply voltage and the delay circuit；Second regulator unit is coupled to institute
State the second output terminal of control voltage, supply voltage and the delay circuit；
First regulator unit includes：
The first transistor and second transistor；
The control terminal of the first transistor is coupled to the control voltage, and input terminal is coupled to supply voltage, output end coupling
In the first output end of the delay circuit；
The control terminal of the second transistor is coupled to the control voltage, and it is first defeated to be coupled to the delay circuit for input terminal
Outlet, output end ground connection.
2. delay circuit as described in claim 1, which is characterized in that second regulator unit includes：Third transistor
With the 4th transistor；
The control terminal of the third transistor is coupled to the control voltage, and input terminal is coupled to supply voltage, output end coupling
In the second output terminal of the delay circuit；
The control terminal of 4th transistor is coupled to the control voltage, and it is second defeated to be coupled to the delay circuit for input terminal
Outlet, output end ground connection.
3. delay circuit as described in claim 1, which is characterized in that the load unit includes：5th transistor and the 6th
Transistor；
The control terminal of 5th transistor is coupled to the second output terminal of the delay circuit, and input terminal is coupled to power supply electricity
Pressure, output end are coupled to the first output end of the delay circuit；
The control terminal of 6th transistor is coupled to the first output end of the delay circuit, and input terminal is coupled to power supply electricity
Pressure, output end are coupled to the second output terminal of the delay circuit.
4. delay circuit as claimed in claim 3, which is characterized in that the load unit further includes：7th transistor and
Eight transistors；
The control terminal of 7th transistor is coupled to the second output terminal of the delay circuit, input end grounding, output end coupling
It is connected to the first output end of the delay circuit；
The control terminal of 8th transistor is coupled to the first output end of the delay circuit, input end grounding, output end coupling
It is connected to the second output terminal of the delay circuit.
5. delay circuit as described in claim 1, which is characterized in that the amplifying unit includes：9th transistor；
The control terminal of 9th transistor is coupled to the first input end of the delay circuit, input end grounding, output end coupling
It is connected to the first output end of the delay circuit.
6. delay circuit as claimed in claim 5, which is characterized in that the amplifying unit further includes：Tenth transistor；
The control terminal of tenth transistor is coupled to the second input terminal of the delay circuit, input end grounding, output end coupling
It is connected to the second output terminal of the delay circuit.
7. a kind of voltage controlled oscillator, which is characterized in that including at least two delay electricity as claimed in any one of claims 1 to 6
Road；At least two delay circuit joins end to end into positive feedback.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510006052.4A CN105827237B (en) | 2015-01-06 | 2015-01-06 | delay circuit and voltage controlled oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510006052.4A CN105827237B (en) | 2015-01-06 | 2015-01-06 | delay circuit and voltage controlled oscillator |
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| Publication Number | Publication Date |
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| CN105827237A CN105827237A (en) | 2016-08-03 |
| CN105827237B true CN105827237B (en) | 2018-09-07 |
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| CN201510006052.4A Active CN105827237B (en) | 2015-01-06 | 2015-01-06 | delay circuit and voltage controlled oscillator |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110518884B (en) * | 2019-08-20 | 2021-03-09 | 上海交通大学 | Time-delay amplifier |
| CN116346084B (en) * | 2023-03-14 | 2023-10-20 | 瑶芯微电子科技(上海)有限公司 | High-frequency noise suppression circuit |
| CN117559915B (en) * | 2024-01-12 | 2024-03-26 | 西北工业大学 | Dual-path inductance-based dual-mode oscillator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101132167A (en) * | 2006-08-25 | 2008-02-27 | 松下电器产业株式会社 | Ring oscillator and semiconductor integrated circuit and electronic device including the same |
| CN101557213A (en) * | 2009-03-27 | 2009-10-14 | 华为技术有限公司 | Delay unit, annular oscillator and PLL circuit |
| CN101567679A (en) * | 2009-05-22 | 2009-10-28 | 清华大学 | Differential voltage-controlled adjustable time delay unit with full swing |
| CN103812503A (en) * | 2012-11-15 | 2014-05-21 | 安凯(广州)微电子技术有限公司 | Differential delay unit circuit and ring oscillator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8710930B2 (en) * | 2012-01-12 | 2014-04-29 | Mediatek Singapore Pte. Ltd. | Differential ring oscillator and method for calibrating the differential ring oscillator |
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2015
- 2015-01-06 CN CN201510006052.4A patent/CN105827237B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101132167A (en) * | 2006-08-25 | 2008-02-27 | 松下电器产业株式会社 | Ring oscillator and semiconductor integrated circuit and electronic device including the same |
| CN101557213A (en) * | 2009-03-27 | 2009-10-14 | 华为技术有限公司 | Delay unit, annular oscillator and PLL circuit |
| CN101567679A (en) * | 2009-05-22 | 2009-10-28 | 清华大学 | Differential voltage-controlled adjustable time delay unit with full swing |
| CN103812503A (en) * | 2012-11-15 | 2014-05-21 | 安凯(广州)微电子技术有限公司 | Differential delay unit circuit and ring oscillator |
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