CN105824719A - Method and system for detecting random access memory - Google Patents
Method and system for detecting random access memory Download PDFInfo
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- CN105824719A CN105824719A CN201610150312.XA CN201610150312A CN105824719A CN 105824719 A CN105824719 A CN 105824719A CN 201610150312 A CN201610150312 A CN 201610150312A CN 105824719 A CN105824719 A CN 105824719A
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention provides a method and a system for detecting a random access memory. The method comprises the following steps of monitoring connecting ports of a first processor and a primary random access memory by a second processor; if the first processor is monitored to write data in a first address of the primary random access memory, obtaining the data, reversing the data, and then writing reversed data in a second address of a standby random access memory; if the first processor is monitored to read data from the first address of the primary random access memory, obtaining the data read from the first address by the first processor, read the data from the second address, comparing the data read from the first address with the data read from the second address, and outputting a detection signal according to a comparison result. As being seen, the method and the system for detecting the random access memory can be used for detecting the data transmission of the primary random access memory in real time, moreover, the data are not needed to be written in all addresses, and thus, the time consumption is reduced. Furthermore, a common cause failure factor can be avoided quite well.
Description
Technical field
The present invention relates to industrial control field, especially relate to detection method and the system of a kind of random access memory.
Background technology
Synchronous DRAM is (English: SynchronousDynamicRandomAccessMemory, be called for short SDRAM) etc. random access memory there is the features such as price is low, data transmission rate is high, manufacturing process is simple, be widely used in digital circuitry.
But, owing to electromagnetic interference or defective workmanship etc. affect, there is the probability of certain single-bit state upset mistake in random access memory when data are transmitted, and the data transmission of mistake may result in system operation and mistake occurs, even threatens the safety of system.Due to random access memory usually not self-checking function, how the data to random access memory are transmitted and are detected, and are the key factors of safeguards system safe operation.
A kind of conventional detection mode is, before random access memory formally uses, writing data to all addresses of random access memory and read the data of write, by the data of the data of reading with write being compared, the data transmission of detection random access memory is the most normal.
But, this detection mode can only detect before random access memory formally uses, and real-time is very poor, it is impossible to the upset mistake occurred during detecting use.And need when detecting all to write data in all addresses of random access memory, detection is the longest.
Summary of the invention
Present invention solves the technical problem that the detection method and system being to provide a kind of random access memory, detect to realize in real time the data of random access memory being transmitted, and need not all write data in all addresses of random access memory, thus reduce time-consuming.
To this end, the technical scheme that the present invention solves technical problem is:
The invention provides the detection method of a kind of random access memory, described method includes:
Second processor monitors first processor and the connectivity port of primary random access memory；
If listening to the described first processor the first address write data to described primary random access memory, described second processor obtains described data, and will write the second address of standby random access memory after described data-conversion；
If listening to the described first processor the first address reading data from described primary random access memory, described second processor obtains the data that described first processor reads from described first address, and from the second address reading data of described standby random access memory；
The data that obtain, described first processor are read by described second processor from described first address, compare, according to comparative result output detections signal with the data read from described second address.
Optionally, if described comparative result represents the data read from described second address, matching after the data-conversion read from described first address, described detection signal is initial signal；
If described comparative result represents the data read from described second address, not mating after the data-conversion read from described first address, described detection signal is abnormal signal.
Optionally, described include according to comparative result output detections signal:
According to comparative result to described first processor output detections signal.
Optionally, if described detection signal is abnormal signal；Described method also includes:
Described second processor receives the clear signal that described first processor sends；
Described second processor exports initial signal to described first processor.
Optionally, described second address is determined according to described first address.
Optionally, also include:
If listen to the described first processor the 3rd address write data to described primary random access memory and receive error injection signal, described second processor obtains the data to described 3rd address write, and the 4th address of described standby random access memory of writing direct；
If listening to the described first processor the 3rd address reading data from described primary random access memory, described second processor obtains the data that described first processor reads from described 3rd address, and from the 4th address reading data of described standby random access memory；
The data that obtain, described first processor are read by described second processor from described 3rd address, compare with the data read from described 4th address, generate testing result according to comparative result.
The invention provides the detecting system of a kind of random access memory, first processor is connected with primary random access memory, and the second processor is connected with the connectivity port of first processor and primary random access memory, and is connected with standby random access memory；Described system includes: described second processor and described standby random access memory；
Described second processor is used for monitoring described connectivity port；If listening to the described first processor the first address write data to described primary random access memory, obtaining described data, and the second address of described standby random access memory being write after described data-conversion；If listening to the described first processor the first address reading data from described primary random access memory, obtain the data that described first processor reads from described first address, and from the second address reading data of described standby random access memory；
Described second processor is additionally operable to, the data that obtain, described first processor read from described first address, compares, according to comparative result output detections signal with the data read from described second address.
Optionally, if described comparative result represents the data read from described second address, matching after the data-conversion read from described first address, described detection signal is initial signal；
If described comparative result represents the data read from described second address, not mating after the data-conversion read from described first address, described detection signal is abnormal signal.
Optionally, described second processor is also connected with the first port of described first processor, and described first port is different from described connectivity port；
When according to comparative result output detections signal, described second processor specifically for according to comparative result to the described first port output detections signal of described first processor.
Optionally, described second processor is also connected with the second port of described first processor, and described second port is different from described connectivity port；
If described detection signal is abnormal signal, described second processor is additionally operable to receive the clear signal that described second port of described first processor sends, and exports initial signal to described first port of described first processor.
Optionally, described second address is determined according to described first address.
Optionally, described second processor is also connected with the 3rd port of described first processor, and described 3rd port is different from described connectivity port；
Described second processor is additionally operable to, if listen to the described first processor the 3rd address write data to described primary random access memory and receive the error injection signal of described 3rd port transmission, obtain the data to described 3rd address write, and the 4th address of described standby random access memory of writing direct；If listening to the described first processor the 3rd address reading data from described primary random access memory, obtain the data that described first processor reads from described 3rd address, and from the 4th address reading data of described standby random access memory；
Described second processor is additionally operable to, the data that obtain, described first processor read from described 3rd address, compares with the data read from described 4th address, generates testing result according to comparative result.
By technique scheme, in the embodiment of the present invention, second processor can monitor first processor and the connectivity port of primary random access memory, when listening to the described first processor the first address write data to described primary random access memory, the second address of standby random access memory can will be write after described data-conversion, when listening to the described first processor the first address reading data from described primary random access memory, described second processor can obtain the data that described first processor reads from described first address, and from the second address reading data of described standby random access memory, and the data read from described first address and described second address are compared, according to comparative result output detections signal.Visible, the data of random access memory can be transmitted by the embodiment of the present invention in real time and detect, and need not all write in all addresses data, thus reduce time-consuming.It addition, the embodiment of the present invention is when to standby random access memory storage data, store again after data can be carried out inversion operation, it is possible to avoid common cause failure factor.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in describing embodiment below, the required accompanying drawing used is briefly described, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of transmission system of the prior art；
The schematic flow sheet of a kind of embodiment of the method that Fig. 2 provides for the embodiment of the present invention；
A kind of structural representation storing system that Fig. 3 provides for the embodiment of the present invention；
The schematic flow sheet of the another kind of embodiment of the method that Fig. 4 provides for the embodiment of the present invention；
The structural representation of the another kind of storage system that Fig. 5 provides for the embodiment of the present invention；
The data flow schematic diagram of the CPLD that Fig. 6 provides for the embodiment of the present invention.
Detailed description of the invention
The transmission system of random access memory is as it is shown in figure 1, data can be write by first processor 101 to random access memory 102, it is also possible to read data from random access memory 102 by first processor 101.Due to random access memory usually not self-checking function, how the data to random access memory are transmitted and are detected, and are the key factors of safeguards system safe operation.
A kind of conventional detection mode is, before random access memory uses, writes data to all addresses of random access memory and reads the data of write, and by the data of the data of reading with write being compared, the data transmission of detection random access memory is the most normal.But, this detection mode real-time is very poor, it is impossible to the upset mistake occurred during detecting use.And detect the longest.In addition with two kinds of detection modes, a kind of is the self-inspection utilizing the address mapping function of embedded OS to realize random access memory, and another kind is to utilize the built-in error detection of embedded processor architecture and report mechanism to detect.Both modes are required for depending on embedded processing systems, and development cost is high, and broad applicability is poor.
The embodiment of the present invention provides the detection method of a kind of random access memory and system, to realize data to random access memory to transmit and detecting in real time, and need not all write in all addresses of random access memory data, thus reduces time-consuming.And, it is not necessary to by means of embedded processing systems, succeed in developing low thus broad applicability high.Additionally it uses bypass detection mode, also will not impact normal use of random access memory even if detection function is made mistakes.
For the technical scheme making those skilled in the art be more fully understood that in the present invention, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, all should belong to the scope of protection of the invention.
Refer to Fig. 2, embodiments provide a kind of embodiment of the method for the detection method of random access memory.
The present embodiment may be used in storage system as shown in Figure 3, and this system includes first processor 301, primary random access memory the 302, second processor 303 and standby random access memory 304.Wherein, first processor 301 is connected with primary random access memory 302, thus first processor 301 can carry out data transmission with primary random access memory 302, such as, first processor 301 writes data to primary random access memory 302, or first processor 301 reads data from primary random access memory 302.
The described method of the present embodiment includes:
S201: the second processor 303 monitors first processor 301 and the connectivity port of primary random access memory 302.
Wherein, the second processor 303 is connected with the connectivity port of first processor 301 and primary random access memory 302, thus monitors described connectivity port, determines whether first processor 301 carries out data transmission with primary stochastic processor 302.
S202: if listening to the first processor 301 first address write data to primary random access memory 302, second processor 303 obtains the first processor 301 data to described first address write, and will write the second address of standby random access memory 304 after this data-conversion.
In the embodiment of the present invention, if first processor 301 writes data to primary random access memory 302, second processor 303 can listen to this write operation, and get the writing address (the i.e. first address) of this write operation, and the second address of standby random access memory 304 will be write after described data-conversion.Wherein, the second address can determine according to the first address.Such as, the first address is identical with the second address, and the first address can be the 0th to the 15th, and the second address can also be the 0th to the 15th.Second processor 303 is corresponding stores described first address and described second address.
Wherein, the second processor 303 is not directly to write data into standby random access memory 304, but can store after negating data again, it is possible to avoid common cause failure factor (mistake caused due to same problem) well.Inversion operation refers to invert the low and high level in data.
S203: if listening to the first processor 301 first address reading data from primary random access memory 302, second processor 303 obtains the data that first processor 301 reads from the first address of primary random access memory 302, and from the second address reading data of standby random access memory 304.
If first processor 301 reads the data having been written into from primary random access memory 302, the second processor 303 can listen to this read operation, gets the first address of this read operation, and obtains the data that this read operation reads.Additionally, the second processor 303 also can get the second address that the first address is corresponding, and from the second address reading data of standby random access memory 304.
The data that obtain, first processor 301 are read by the S204: the second processor 303 from the first address of primary random access memory 302, the data read from the second address of standby random access memory 304 with the second processor 303 compare, according to comparative result output detections signal.
Wherein, if described comparative result represents the data read from described second address, matching after the data-conversion read from described first address, described detection signal is initial signal, i.e. represents that this transmission is normal.Match and also refer to identical or identical ratio and reach predetermined percentage etc..If described comparative result represents the data read from described second address, not mating after the data-conversion read from described first address, described detection signal is abnormal signal error_flag, i.e. represents that mistake occurs in this transmission.
By technique scheme, in the embodiment of the present invention, second processor 203 can monitor first processor 201 and the connectivity port of primary random access memory 202, when listening to the first processor 201 first address write data to primary random access memory 202, the second address of standby random access memory 204 can will be write after described data-conversion, when listening to the first processor 201 first address reading data from primary random access memory 202, second processor 203 can obtain the data that first processor 201 reads from described first address, the second address reading data from standby random access memory 204, and the data read from described first address and described second address are compared, according to comparative result output detections signal.Visible, in the embodiment of the present invention during the use of primary random access memory 202, it is possible to the data to primary random access memory 202 are transmitted and detected in real time, and need not all write data in all addresses, thus reduce time-consuming.It addition, the embodiment of the present invention is when storing data to standby random access memory 204, store again after data can be carried out inversion operation, it is possible to avoid common cause failure factor well.
Additionally, the method that the embodiment of the present invention provides need not by means of embedded processing systems, succeed in developing low thus broad applicability high.Additionally it uses bypass detection mode, also will not impact normal use of primary random access memory even if detection function is made mistakes, thus avoid the interruption of first processor read-write operation.If the second processor or standby random access memory occur abnormal, error detection error correction (ErrorCorrectingCode, ECC) module can be used to replace, thus realize detection and the recovery of wrong data.
In the present embodiment, first processor 301 can be central processing unit (CentralProcessingUnit, CPU) etc., and the second processor 304 can be field programmable gate array (Field-ProgrammableGateArray, FPGA), CPLD (ComplexProgrammableLogicDevice, CPLD) etc..In the present embodiment, primary random access memory 302 and standby random access memory 304 can be any one random access devices, such as SRAM (StaticRandomAccessMemory, SRAM), synchronous DRAM (SynchronousDynamicRandomAccessMemory, SDRAM), Double Data Rate synchronous DRAM (DoubleDataRate, DDR), DDR2, DDR3 etc..
In the embodiment of the present invention, the second processor 303 can be to first processor 301 output detections signal.Such as, if the second processor 303 exports initial signal (such as 0) to first processor 301, represent that this transmission is normal, if the second processor 303 is to first processor 302 output abnormality signal error_flag (such as 1), represent this transmission abnormality.Wherein, first processor 301 can process detection signal by the way of interruption.
If the second processor 303 is to first processor 301 output abnormality signal, then first processor 301 makes the processing mode of correspondence, such as warning etc., it is ensured that can find in time during data transmission exception after receiving abnormal signal.Wherein, first processor 301 can also send clear signal to the second processor 303, after the second processor 303 receives clear signal, exports initial signal according to this clear signal.Such as, the second processor 303 exports 1, after receiving clear signal, exports 0.
The present embodiment is also supported error injection pattern, say, that the second processor 303 writes to standby random access memory 304 and do not carries out inversion operation before data, but directly data is write.So that the detection signal one of the second processor 303 output is set to abnormal signal, the bypass detection function realized for detection the second processor 303 and standby random access memory 304 is the most normal.
Specifically, described method can also include: if listen to the first processor 301 the 3rd address write data to primary random access memory 302 and receive error injection signal, second processor 303 obtains the data to the 3rd address write, and the 4th address of standby random access memory 304 of writing direct；If listening to the first processor 301 the 3rd address reading data from primary random access memory 302, second processor 303 obtains the data that first processor 301 reads from the 3rd address of primary random access memory 302, and from the 4th address reading data of standby random access memory 304；Second processor 303, by the data that obtain, first processor 301 reads from the 3rd address, compares with the data read from the 4th address, generates testing result according to comparative result.
The present invention is illustrated by a specific embodiment below.
Refer to Fig. 4, embodiments provide the another kind of embodiment of the method for the detection method of random access memory.
The present embodiment is introduced as a example by the system shown in Fig. 5, and this system includes CPU501, SDRAM502, CPLD503 and SDRAM504.Wherein, CPLD can include parsing module, data control block and diagnostic module.Visible, the present embodiment is specially CPU with first processor, the second processor is specially CPLD, and random access memory specially SDRAM carries out exemplary introduction, and is not limited this in the embodiment of the present invention.
The described method of the present embodiment includes:
S401: parsing module monitors the connectivity port of CPU501 and SDRAM502.
S402: if parsing module listens to CPU501 and sends control signal 01 to SDRAM502, send to SDRAM504 as control signal 02 after this control signal 01 is resolved, it is ensured that the action that SDRAM504 with SDRAM502 execution is identical.
Such as shown in Fig. 6, control signal 01 includes address signal addr_bi [12:0], row gating signal cas_i, column selection messenger res_i and write enable signal we_i.Control signal 02 includes: address signal backup_addr_bo [12:0], row gating signal cas_o, column selection messenger res_o and write enable signal we_o.Wherein, write enable signal we_i and we_o is used for enabling write operation, address signal addr_bi [12:0] writes data into the first address for expression, such as the 0th to the 15th, address signal backup_addr_bo [12:0] writes data into the second address for expression, such as the 0th to the 15th.Row gating signal and column selection messenger are used for enabling row address strobe and column address strobe.
S403: parsing module listens to CPU501 when SDRAM502 sends control signal 01, data control block obtains data dq [15:0] that CPU501 sends to SDRAM502, and after these data dq [15:0] being negated, obtain backup_dq [15:0], data backup_dq [15:0] are sent to SDRAM504.The data received can be write the first address according to control signal 01 by SDRAM502.The data received can be write the second address according to control signal 02 by SDRAM504.
In the present embodiment, CPU501 can carry out 8 bits, 16 bits, 24 bits or the read-write operation of burst mode to SDRAM502, and CPLD503 carries out the read-write operation of model identical to SDRAM504.
S404: if parsing module listens to CPU501 and sends control signal 03 to SDRAM502, send to SDRAM504 as control signal 04 after this control signal 03 is resolved.
Control signal 03 includes address signal addr_bi [12:0], row gating signal cas_i, column selection messenger res_i and reads to enable signal rd_i.Control signal 04 includes: address signal backup_addr_bo [12:0], row gating signal cas_o, column selection messenger res_o and reading enable signal rd_o.Wherein, reading to enable signal rd_i and rd_o and be used for enabling read operation, address signal addr_bi [12:0] is for representing that address signal backup_addr_bo [12:0] is for representing from the second address reading data from the first address reading data.Row gating signal and column selection messenger are used for representing enable row address strobe and column address strobe.
S405: parsing module listens to CPU501 when SDRAM502 sends control signal 03, and data control block obtains the data that read from SDRAM502 of CPU501, and data control block reads data from SDRAM504.Owing to SDRAM502 and SDRAM504 is respectively received control signal 03 and control signal 04, what now data control block got is the data of the second address reading of the first address from SDRAM502 and SDRAM504 respectively, and the data read from the two address are sent to diagnostic module.
The data read from the first address and the second address respectively are compared by S406: diagnostic module, if comparative result represents that the data low and high level read from the two address is contrary, then represent that this transmission is normal, initial signal is exported to CPU501, otherwise represent this transmission abnormality, to CPU501 output abnormality signal.Such as shown in Fig. 6, diagnostic module output abnormality signal error_flag.After diagnostic module receives the clear signal of CPU501, the diagnostic module initial signal of output, and no longer output abnormality signal error_flag.
Wherein, parsing module may also listen for other signals in addition to control signals that CPU501 sends, such as configuration signal (including initial configuration), self refresh signal to SDRAM502.Now parsing module can send to SDRAM504 after configuration signal, self refresh signal etc. being resolved.
The present embodiment also supports error injection pattern.If CPU501 is when CPLD503 sends error injection signal, the data of reading can be write direct SDRAM504 by data control block, does not carry out inversion operation.
Corresponding said method embodiment, present invention also offers a kind of embodiment of the method for the detecting system of random access memory.
As it is shown on figure 3, first processor 301 is connected with primary random access memory 302 in the present embodiment, the second processor 303 is connected with the connectivity port of first processor 301 and primary random access memory 302, and the second processor 303 is connected with standby random access memory 304；The described detecting system of the present embodiment includes: the second processor 303 and standby random access memory 304.
In the present embodiment, the second processor 303 is for monitoring first processor 301 and the connectivity port of primary random access memory 302.So that it is determined that whether first processor 301 carries out data transmission with primary stochastic processor 302.
Second processor 303 is additionally operable to, if listening to the first processor 301 first address write data to primary random access memory 302, the second processor 303 obtains described data, and will write the second address of standby random access memory 304 after described data-conversion.
Wherein, the second address can determine according to the first address.Such as, the first address is identical with the second address, and the first address can be the 0th to the 15th, and the second address can also be the 0th to the 15th.Second processor 303 is additionally operable to described first address of corresponding storage and described second address.
In the present embodiment, the second processor 303 is not directly to write data into standby random access memory 304, but can store after negating data again, it is possible to avoid common cause failure factor well.
Second processor 303 is additionally operable to, if listening to the first processor 301 first address reading data from primary random access memory 302, second processor 303 obtains the data that first processor 301 reads from the first address of primary random access memory 302, and from the second address reading data of standby random access memory 304.
Second processor 303 is additionally operable to, the data that obtain, first processor 301 read from the first address of primary random access memory 302, and the data read with the second address from standby random access memory 304 compare, according to comparative result output detections signal.
Wherein, if described comparative result represents the data read from described second address, matching after the data-conversion read from described first address, described detection signal is initial signal, i.e. represents that this transmission is normal.Match and also refer to identical or identical ratio and reach predetermined percentage etc..If described comparative result represents the data read from described second address, not mating after the data-conversion read from described first address, described detection signal is abnormal signal error_flag, i.e. represents that mistake occurs in this transmission.
Visible, the detecting system of the present embodiment is during the use of primary random access memory 202, it is possible to the data to primary random access memory 202 are transmitted and detected in real time, and need not all write data in all addresses, thus reduces time-consuming.It addition, the embodiment of the present invention is when storing data to standby random access memory 204, store again after data can be carried out inversion operation, it is possible to avoid common cause failure factor well.
Additionally, the detecting system that the embodiment of the present invention provides need not by means of embedded processing systems, succeed in developing low thus broad applicability high.Additionally it uses bypass testing circuit, also will not impact normal use of primary random access memory even if detection function is made mistakes, thus avoid the interruption of first processor read-write operation.If the second processor or standby random access memory occur abnormal, ECC module can be used to replace, thus realize detection and the recovery of wrong data.
In the present embodiment, first processor 301 can be CPU etc., and the second processor 304 can be FPGA, CPLD etc..In the present embodiment, primary random access memory 302 and standby random access memory 304 can be any one random access devices, such as SRAM, SDRAM, DDR, DDR2, DDR3 etc..
In the embodiment of the present invention, the second processor 303 can also be connected with the first port of first processor 301, and described first port is different from described connectivity port.Second processor 303 can be to the first port output detections signal of first processor 301.Such as, if the second processor 303 exports initial signal (such as 0) to the first port, represent that this transmission is normal, if the second processor 303 is to the first port output abnormality signal error_flag (such as 1), represent this transmission abnormality.Wherein, first processor 301 can process detection signal by the way of interruption.
If the second processor 303 is to the first port output abnormality signal of first processor 301, then first processor 301 makes the processing mode of correspondence, such as warning etc., it is ensured that can find in time during data transmission exception after receiving abnormal signal.Wherein, second processor 303 can also be connected with the second port of first processor 301, described second port is different from described connectivity port, first processor 301 can also send clear signal to the second port of the second processor 303, after second processor 303 receives clear signal, export initial signal according to this clear signal to the first port.Such as, the second processor 303 is to the first port output 1, after receiving clear signal, to the first port output 0.
The present embodiment is also supported error injection pattern, say, that the second processor 303 writes to standby random access memory 304 and do not carries out inversion operation before data, but directly data is write.So that the detection signal one of the second processor 303 output is set to abnormal signal, the most normally work for detecting the detecting system of the present embodiment.
Specifically, the second processor 303 is also connected with the 3rd port of first processor 301, and described 3rd port is different from described connectivity port.Second processor 303 is additionally operable to, if listen to the first processor 301 the 3rd address write data to primary random access memory 302 and receive the error injection signal of described 3rd port transmission, obtain the data to described 3rd address write, and the 4th address of standby random access memory 304 of writing direct；If listening to the first processor 301 the 3rd address reading data from primary random access memory 302, obtain the data that first processor 301 reads from the 3rd address of primary random access memory 302, and from the 4th address reading data of standby random access memory 304；Second processor 303 is additionally operable to, the data that will read from described 3rd address, compares with the data read from described 4th address, generates testing result according to comparative result.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, the system of foregoing description, the specific works process of device and unit, it is referred to the corresponding process in preceding method embodiment, does not repeats them here.
In several embodiments provided by the present invention, it should be understood that disclosed system, apparatus and method, can realize by another way.Such as, device embodiment described above is only schematically, such as, the division of described unit, be only a kind of logic function to divide, actual can have when realizing other dividing mode, the most multiple unit or assembly can in conjunction with or be desirably integrated into another system, or some features can ignore, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be the INDIRECT COUPLING by some interfaces, device or unit or communication connection, can be electrical, machinery or other form.
The described unit illustrated as separating component can be or may not be physically separate, and the parts shown as unit can be or may not be physical location, i.e. may be located at a place, or can also be distributed on multiple NE.Some or all of unit therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.
It addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it is also possible to be that unit is individually physically present, it is also possible to two or more unit are integrated in a unit.Above-mentioned integrated unit both can realize to use the form of hardware, it would however also be possible to employ the form of SFU software functional unit realizes.
If described integrated unit is using the form realization of SFU software functional unit and as independent production marketing or use, can be stored in a computer read/write memory medium.Based on such understanding, completely or partially can embodying with the form of software product of part that prior art is contributed by technical scheme the most in other words or this technical scheme, this computer software product is stored in a storage medium, including some instructions with so that a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (ROM, Read-OnlyMemory), the various media that can store program code such as random access memory (RAM, RandomAccessMemory), magnetic disc or CD.
The above, above example only in order to technical scheme to be described, is not intended to limit；Although the present invention being described in detail with reference to previous embodiment, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (12)
1. the detection method of a random access memory, it is characterised in that described method includes:
Second processor monitors first processor and the connectivity port of primary random access memory；
If listening to the described first processor the first address write data to described primary random access memory, described second processor obtains described data, and will write the second address of standby random access memory after described data-conversion；
If listening to the described first processor the first address reading data from described primary random access memory, described second processor obtains the data that described first processor reads from described first address, and from the second address reading data of described standby random access memory；
The data that obtain, described first processor are read by described second processor from described first address, compare, according to comparative result output detections signal with the data read from described second address.
Method the most according to claim 1, it is characterised in that if described comparative result represents the data read from described second address, matches after the data-conversion read from described first address, and described detection signal is initial signal；
If described comparative result represents the data read from described second address, not mating after the data-conversion read from described first address, described detection signal is abnormal signal.
Method the most according to claim 1, it is characterised in that described include according to comparative result output detections signal:
According to comparative result to described first processor output detections signal.
Method the most according to claim 3, it is characterised in that if described detection signal is abnormal signal；Described method also includes:
Described second processor receives the clear signal that described first processor sends；
Described second processor exports initial signal to described first processor.
Method the most according to claim 1, it is characterised in that described second address is determined according to described first address.
Method the most according to claim 1, it is characterised in that also include:
If listen to the described first processor the 3rd address write data to described primary random access memory and receive error injection signal, described second processor obtains the data to described 3rd address write, and the 4th address of described standby random access memory of writing direct；
If listening to the described first processor the 3rd address reading data from described primary random access memory, described second processor obtains the data that described first processor reads from described 3rd address, and from the 4th address reading data of described standby random access memory；
The data that obtain, described first processor are read by described second processor from described 3rd address, compare with the data read from described 4th address, generate testing result according to comparative result.
7. the detecting system of a random access memory, it is characterised in that first processor is connected with primary random access memory, the second processor is connected with the connectivity port of first processor and primary random access memory, and is connected with standby random access memory；Described system includes: described second processor and described standby random access memory；
Described second processor is used for monitoring described connectivity port；If listening to the described first processor the first address write data to described primary random access memory, obtaining described data, and the second address of described standby random access memory being write after described data-conversion；If listening to the described first processor the first address reading data from described primary random access memory, obtain the data that described first processor reads from described first address, and from the second address reading data of described standby random access memory；
Described second processor is additionally operable to, the data that obtain, described first processor read from described first address, compares, according to comparative result output detections signal with the data read from described second address.
System the most according to claim 7, it is characterised in that if described comparative result represents the data read from described second address, matches after the data-conversion read from described first address, and described detection signal is initial signal；
If described comparative result represents the data read from described second address, not mating after the data-conversion read from described first address, described detection signal is abnormal signal.
System the most according to claim 7, it is characterised in that described second processor is also connected with the first port of described first processor, described first port is different from described connectivity port；
When according to comparative result output detections signal, described second processor specifically for according to comparative result to the described first port output detections signal of described first processor.
System the most according to claim 9, it is characterised in that described second processor is also connected with the second port of described first processor, described second port is different from described connectivity port；
If described detection signal is abnormal signal, described second processor is additionally operable to receive the clear signal that described second port of described first processor sends, and exports initial signal to described first port of described first processor.
11. systems according to claim 7, it is characterised in that described second address is determined according to described first address.
12. systems according to claim 7, it is characterised in that described second processor is also connected with the 3rd port of described first processor, described 3rd port is different from described connectivity port；
Described second processor is additionally operable to, if listen to the described first processor the 3rd address write data to described primary random access memory and receive the error injection signal of described 3rd port transmission, obtain the data to described 3rd address write, and the 4th address of described standby random access memory of writing direct；If listening to the described first processor the 3rd address reading data from described primary random access memory, obtain the data that described first processor reads from described 3rd address, and from the 4th address reading data of described standby random access memory；
Described second processor is additionally operable to, the data that obtain, described first processor read from described 3rd address, compares with the data read from described 4th address, generates testing result according to comparative result.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516546A (en) * | 2017-07-07 | 2017-12-26 | 中国航空工业集团公司西安飞行自动控制研究所 | The on-line measuring device and method of a kind of random access memory |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110675911A (en) * | 2019-09-24 | 2020-01-10 | 上海闻泰电子科技有限公司 | DDR (double data Rate) repairing method, device, terminal and storage medium |
| CN111221675A (en) * | 2018-11-26 | 2020-06-02 | 奥特润株式会社 | Method and apparatus for self-diagnosis of RAM error detection logic |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315732A (en) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | Automatic test method and circuit for RAM |
| CN102486938A (en) * | 2010-12-06 | 2012-06-06 | 北大方正集团有限公司 | Method for rapid detection of memory and device |
| CN103257905A (en) * | 2013-05-02 | 2013-08-21 | 浙江中控技术股份有限公司 | Embedded computer system stored data checking circuit and method |
| CN103473160A (en) * | 2013-09-26 | 2013-12-25 | 杭州华为数字技术有限公司 | Testing device, CPU (central processing unit) chip and testing method for cache |
| US20140164834A1 (en) * | 2012-12-03 | 2014-06-12 | Kone Corporation | Apparatus and a method for memory testing by a programmable circuit in a safety critical system |
-
2016
- 2016-03-16 CN CN201610150312.XA patent/CN105824719B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315732A (en) * | 2000-03-30 | 2001-10-03 | 华为技术有限公司 | Automatic test method and circuit for RAM |
| CN102486938A (en) * | 2010-12-06 | 2012-06-06 | 北大方正集团有限公司 | Method for rapid detection of memory and device |
| US20140164834A1 (en) * | 2012-12-03 | 2014-06-12 | Kone Corporation | Apparatus and a method for memory testing by a programmable circuit in a safety critical system |
| CN103257905A (en) * | 2013-05-02 | 2013-08-21 | 浙江中控技术股份有限公司 | Embedded computer system stored data checking circuit and method |
| CN103473160A (en) * | 2013-09-26 | 2013-12-25 | 杭州华为数字技术有限公司 | Testing device, CPU (central processing unit) chip and testing method for cache |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107516546A (en) * | 2017-07-07 | 2017-12-26 | 中国航空工业集团公司西安飞行自动控制研究所 | The on-line measuring device and method of a kind of random access memory |
| CN107516546B (en) * | 2017-07-07 | 2020-09-22 | 中国航空工业集团公司西安飞行自动控制研究所 | Online detection device and method for random access memory |
| CN111221675A (en) * | 2018-11-26 | 2020-06-02 | 奥特润株式会社 | Method and apparatus for self-diagnosis of RAM error detection logic |
| CN111221675B (en) * | 2018-11-26 | 2023-12-22 | 现代奥特奥博株式会社 | Method and apparatus for self-diagnosis of RAM error detection logic |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110675911A (en) * | 2019-09-24 | 2020-01-10 | 上海闻泰电子科技有限公司 | DDR (double data Rate) repairing method, device, terminal and storage medium |
| CN110675911B (en) * | 2019-09-24 | 2021-08-24 | 上海闻泰电子科技有限公司 | DDR (double data Rate) repairing method, device, terminal and storage medium |
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|---|---|
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