CN105810171B - Amplify negater circuit and liquid crystal display device - Google Patents
Amplify negater circuit and liquid crystal display device Download PDFInfo
- Publication number
- CN105810171B CN105810171B CN201610373889.7A CN201610373889A CN105810171B CN 105810171 B CN105810171 B CN 105810171B CN 201610373889 A CN201610373889 A CN 201610373889A CN 105810171 B CN105810171 B CN 105810171B
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- amplification
- clock signal
- switching element
- electrically connected
- negater circuit
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 23
- 230000003321 amplification Effects 0.000 claims abstract description 28
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 28
- 230000005611 electricity Effects 0.000 claims description 9
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000006641 stabilisation Effects 0.000 description 5
- 238000011105 stabilization Methods 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 238000013499 data model Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of amplification negater circuit,Including first switching element,Second switch element,First resistor,Second resistance and zener diode,First switching element includes the first path terminal,Alternate path end and the first control terminal,First control terminal receives external timing signal,First path terminal receives external reference high voltage,Alternate path end is electrically connected to first resistor to receive external reference low-voltage,Alternate path end is used to export the first clock signal,Alternate path end is electrically connected to the anode of zener diode,Second switch element includes third path end,Fourth passage end and the second control terminal,Second control terminal is electrically connected to the cathode of zener diode,Third path end receives external reference low-voltage,Fourth passage end is electrically connected to second resistance to receive external reference high voltage,Fourth passage end is used to export second clock signal.The present invention also provides a kind of liquid crystal display device.So that gate driving circuit exports stable waveform to drive display panel.
Description
Technical field
The present invention relates to field of liquid crystal display, more particularly to a kind of amplification negater circuit and liquid crystal display device.
Background technology
Since liquid crystal display device has many advantages, such as frivolous, energy saving, radiationless, TV, a is now widely used for
In the electronic equipments such as people's computer, tablet computer, personal digital assistant (PDA), mobile phone, digital camera.Liquid crystal display device is usual
Including gate driving circuit, source electrode drive circuit, multi-strip scanning line, a plurality of data lines and by the multi-strip scanning line and a plurality of number
The multiple pixel units intersected to form according to line.The multi-strip scanning line is connected to gate driving circuit, which passes through
The multi-strip scanning line provides gate drive signal for the plurality of pixel unit.The a plurality of data lines is connected to source electrode drive circuit,
The source electrode drive circuit provides display signal by a plurality of data lines for the plurality of pixel unit.
The basic functional principle of liquid crystal display device and drive circuit is：Gate driving circuit with gate line by electrically connecting
Pulling up transistor for connecing sends out gate drive signal to gate line, sequentially opens the TFT of every a line, then by source drive electricity
The pixel unit of one full line is charged to each required voltage by road at the same time, to show different grayscale.I.e. first by the first row
Gate driving circuit pulled up transistor by it and open the thin film transistor (TFT) of the first row, then by source electrode drive circuit to the
The pixel unit of a line charges.When the pixel unit of the first row is charged, gate driving circuit is just by the row film crystal
Pipe is closed, and then the gate driving circuit of the second row is pulled up transistor by it and opens the thin film transistor (TFT) of the second row, then by
Source electrode drive circuit carries out discharge and recharge to the pixel unit of the second row.So sequentially go down, when the pixel of last column of having substituted the bad for the good
Unit, just starts to charge up from the first row again.
Existing gate driving circuit has residual charge accumulation during discharge and recharge is continued for a long time, so as to have impact on
The stability of gate driving circuit, the general low reference voltage passage utilized in level translator chip circuit is to raster data model electricity
Road is discharged, but its charge accumulation can be made by carrying out electric discharge lasting for a long time due to the use of a passage, so as to influence grid
Waveform is stablized in drive circuit output, and influences liquid crystal display device image quality.
The content of the invention
In view of this, present invention aims at providing a kind of amplification negater circuit, the first clock signal and the can be passed through
Two stable units that two clock signals continue control gate drive circuit for a long time discharge gate driving circuit, so that should
Grid drives output and stablizes waveform to drive display panel.
Specifically, the embodiment of the present invention provides a kind of amplification negater circuit, the amplification negater circuit be used for according to it is exterior when
The first clock signal of clock signal output and the second clock signal anti-phase with first clock signal, the amplification negater circuit bag
Include：First switching element, second switch element, first resistor, second resistance and zener diode；
The first switching element includes the first path terminal, alternate path end and the first control terminal, which receives
The external timing signal, first path terminal receive external reference high voltage, which is electrically connected to the first resistor
One end, the other end of the first resistor receives external reference low-voltage, which is used to export first clock letter
Number, which is electrically connected to the anode of the zener diode；
The second switch element includes third path end, fourth passage end and the second control terminal, which is electrically connected
The cathode of the zener diode is connected to, which receives the external reference low-voltage, which is electrically connected to
One end of the second resistance, the other end of the second resistance receive the external reference high voltage, which is used to export
The second clock signal.
Further, which further comprises 3rd resistor and the 4th resistance；
One end of the 3rd resistor receives the external timing signal, and the other end of the 3rd resistor is electrically connected to this and first opens
First control terminal of element is closed, one end of the 4th resistance is electrically connected to the anode of the zener diode, the 4th resistance
The other end is electrically connected to the alternate path end of the first switching element.
Further, the first switching element and the second switch element are triode.
Further, which is PNP type triode, which is NPN type triode.
Further, first control terminal of the first switching element is base stage, and this of the first switching element is first logical
Terminal is emitter, and the alternate path end of the first switching element is collector.
Further, second control terminal of the second switch element is base stage, the threeway of the second switch element
Terminal is emitter, and the fourth passage end of the second switch element is collector.
The embodiment of the present invention also provides a kind of liquid crystal display device, including gate driving circuit, the liquid crystal display device bag
Include amplification negater circuit as described above.
Further, first clock signal is respectively supplied to the grid with the second clock signal in the amplification negater circuit
The stable unit of two of drive circuit.
It can be seen from the above that amplification negater circuit provided in this embodiment and liquid crystal display device, using less triode just
It can realize and produce the first clock signal and second clock signal, production cost be saved, in addition, the first clock signal and second clock
Signal drives two stable units of gate driving circuit respectively, so that mutual by two stable units of gate driving circuit
Alternately discharge gate driving circuit, can avoid well because gate driving circuit stabilization unit for a long time constantly
Failed using charge accumulation is produced, influence gate driving circuit output and stablize waveform, so that gate driving circuit exports
The display panel progress picture for stablizing drive waveform liquid crystal display device is shown, to reach the antijamming capability for improving display panel
With the effect of image quality.
Above and other objects, features and advantages to allow the present invention can become apparent, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below.
Brief description of the drawings
Fig. 1 is a kind of electrical block diagram for liquid crystal display device that one embodiment of the invention provides.
Fig. 2 is a kind of electrical block diagram for amplification negater circuit that one embodiment of the invention provides.
Fig. 3 is the waveform diagram of the part signal of the amplification negater circuit shown in Fig. 2.
Embodiment
Further to illustrate that the present invention is to realize technological means and effect that expected purpose taken, below in conjunction with attached drawing
And preferred embodiment, to according to amplification negater circuit proposed by the present invention and the embodiment of liquid crystal display device, method,
Step, structure, feature and effect, describe in detail as after.
For the present invention foregoing and other technology contents, feature and effect, in the following preferable reality coordinated with reference to schema
Applying in the detailed description of example to be clearly presented.By the explanation of embodiment, when expection can be reached to the present invention
The technological means and effect that purpose is taken be able to more deeply and it is specific understand, but institute's accompanying drawings be only to provide with reference to
Purposes of discussion, is not used for being any limitation as the present invention.
Please refer to Fig.1, Fig. 1 is a kind of circuit structure signal for liquid crystal display device 100 that one embodiment of the invention provides
Figure.As shown in Figure 1, liquid crystal display device 100 includes display panel 20 and printed circuit board (PCB) 30, printed circuit board (PCB) 30 is by soft
Circuit board (not shown) is connected with display panel 20, and amplification negater circuit 32 is provided with printed circuit board (PCB) 30 and (is not shown in Fig. 1
Go out, refer to Fig. 2) with the circuit element such as power circuit (not shown), for providing the first clock signal to display panel 20
VH1 (not shown in Fig. 1, referring to Fig. 2) and second clock signal VH2 (not shown in Fig. 1, referring to Fig. 2), power supply signal with
Signal of video signal etc..Display panel 20 includes gate driving circuit 23, source electrode drive circuit 24, multi-strip scanning line 25, more datas
Line 26 and the multiple pixel units 27 intersected to form by multi-strip scanning line 25 and a plurality of data lines 26.Multi-strip scanning line 25 connects
To gate driving circuit 23, gate driving circuit 23 provides raster data model by multi-strip scanning line 25 for multiple pixel units 27 to be believed
Number.A plurality of data lines 26 is connected to source electrode drive circuit 24, and source electrode drive circuit 24 is multiple pixels by a plurality of data lines 26
Unit 27, which provides, shows signal.
In the present embodiment, amplify negater circuit 32 to be used for respectively to two stable unit (figures of gate driving circuit 23
It is not shown) the first clock signal VH1 and second clock signal VH2 is provided, to drive two stable units to provide with alternateing
Low level is discharged to gate driving circuit 23, so as to avoid two stable units from forming electric charge because of long-term continuous firing
Accumulate and the stability of 23 output waveform of gate driving circuit is influenced after failure, and then gate driving circuit 23 is exported neutral wave
Shape is shown with driving the display panel 20 of liquid crystal display device 100 to carry out picture, to improve the antijamming capability of display panel 20
And image quality.
Please also refer to Fig. 2 and Fig. 3, Fig. 2 is a kind of circuit for amplification negater circuit 32 that one embodiment of the invention provides
Structure diagram, Fig. 3 are the waveform diagram of the part signal of the amplification negater circuit shown in Fig. 2.As shown in Figure 2 and Figure 3, put
Big negater circuit 32 includes first switching element T1, second switch element T2, zener diode DZ, first resistor R1, the second electricity
Hinder R2.
In an embodiment of the present invention, amplification negater circuit 32 is further included for the electricity of the 3rd resistor R3 of current limliting and the 4th
R4 is hindered, but the present invention is not limited thereto.
First switching element T1 includes the first path terminal, alternate path end and the first control terminal.First switching element T1's
First control terminal receives external timing signal CLK, specifically, one end reception external timing signal CLK of 3rd resistor R3, the 3rd
The other end of resistance R3 is electrically connected to the first control terminal of first switching element T1.The first path termination of first switching element T1
Receive external reference high voltage VGH.The alternate path end of first switching element T1 is electrically connected to one end of first resistor R1, the first electricity
The other end for hindering R1 receives the alternate path end of external reference low-voltage VSQ, first switching element T1 for exporting the first clock
Signal VH1.
Second switch element T2 includes third path end, fourth passage end and the second control terminal.Second switch element T2's
Second control terminal is electrically connected to the cathode of zener diode DZ, and the anode of zener diode DZ is electrically connected to the one of the 4th resistance R4
End, the other end of the 4th resistance R4 are electrically connected to the alternate path end of first switching element T1.The 3rd of second switch element T2
Path terminal receives external reference low-voltage VSQ.The fourth passage end of second switch element T2 is electrically connected to the one of second resistance R2
End, the other end of second resistance R2 receive external reference high voltage VGH, and the fourth passage end of second switch element T2 is used to export
Second clock signal VH2.Specifically, in the present embodiment, the second control terminal of second switch element T2 receives first switch member
First clock signal VH1 of the alternate path end output of part T1.First resistor R1 and second resistance R2 play blocking and current limliting
Effect, 3rd resistor R3 and the 4th resistance R4 play the role of current limliting, and zener diode DZ plays the role of voltage stabilizing.
Specifically, in the present embodiment, first switching element T1 and second switch element T2 can be triode, further
Ground first switching element T1 can be PNP type triode, and second switch element T2 can be NPN type triode, but be not limited to this.Tool
Body, in the present embodiment, the first control terminal and the second control terminal of second switch element T2 of first switching element T1 are
Base stage, the first path terminal of first switching element T1 and the third path end of second switch element T2 are emitter, and first opens
It is collector that the alternate path end of element T1, which is closed, with the fourth passage end of second switch element T2.
First switching element T1 is controlled and on or off by external timing signal CLK, and second switch element T2 is by first
First clock signal VH1 of the alternate path end output of switch element T1 is controlled and on or off.Specifically, in the present embodiment
In, the duty cycle of external timing signal CLK can be arbitrary value, it is preferable that external timing signal CLK is that duty cycle is 5 percent
Ten AC signal, but be not limited to this.External reference high voltage VGH and external reference low-voltage VSQ is direct current signal.
When at t1 moment and/or t3 moment, external timing signal CLK outputs are high level, and first switching element T1 is by outer
The high level of portion's clock signal clk output is controlled and ended, the first clock of the alternate path end output of first switching element T1
Signal VH1 is low level.At the same time the low electricity of the first clock signal VH1 of the alternate path end output of first switching element T1
The low electricity of external reference that mean longitude is received by the third path end after zener diode DZ voltage stabilizings less than second switch element T2
VSQ, the first clock signal VH1 control second switch elements T2 of the alternate path end output of first switching element T1 is pressed to end,
The second clock signal VH2 of the fourth passage end output of second switch element T2 is high level.First switching element T1 at this time
First clock signal VH1 of alternate path end output stablizes unit to the one of gate driving circuit 23 and provides low level, makes grid
Drive circuit 23 carries out electric discharge and neutralizes the stable waveform of residual charge output to drive 20 display picture of display panel.
When at t2 moment and/or t4 moment, external timing signal CLK outputs are low level, first switching element T1 by
The low level control of external timing signal CLK outputs and turn on, the output of the alternate path end of first switching element T1 first when
Clock signal VH1 is high level.The high level of first clock signal VH1 of the alternate path end output of first switching element T1 at the same time
Via the second control terminal of second switch element T2 is transmitted to after zener diode DZ voltage stabilizings, so as to control second switch element T2
Conducting, the second clock signal VH2 of the fourth passage end output of second switch element T2 is low level.Second switch element at this time
The second clock signal VH2 of the fourth passage end output of T2 provides low level to another stable unit of gate driving circuit 23,
Make gate driving circuit 23 discharged in residual charge output stablize waveform to drive 20 display picture of display panel.
Specifically, in the present embodiment, first switching element T1 alternate path end output the first clock signal VH1 with
The second clock signal VH2 inversion signals each other of second switch element T2 fourth passages end output, the first clock signal VH1 and the
Two clock signal VH2 are respectively supplied to two stabilization units of gate driving circuit 23.Specifically, when the first clock signal VH1 is
During low level, second clock signal VH2 is high level, and at this moment grid is driven by the stabilization unit for receiving the first clock signal VH1
Dynamic circuit 23 discharges, so that waveform is stablized in the output of gate driving circuit 23.When the first clock signal VH1 is high level,
Second clock signal VH2 is low level, at this moment by reception second clock signal VH2 stabilization unit to gate driving circuit 23 into
Row electric discharge, so that waveform is stablized in the output of gate driving circuit 23.
It can be seen from the above that amplification negater circuit 23 provided in this embodiment and liquid crystal display device 100, use three less poles
Pipe, which just can be realized, produces the first clock signal VH1 and second clock signal VH2, production cost is saved, in addition, the first clock signal
VH1 and second clock signal VH2 drives two stable units of gate driving circuit 23 respectively, so as to pass through gate driving circuit
Two of 23 are stable, and unit discharges gate driving circuit 23 with alternateing, and can avoid well because of raster data model electricity
The stabilization unit on road 23 is constantly failed using charge accumulation is produced for a long time, is influenced gate driving circuit 23 and is exported neutral wave
Shape, so that the display panel 20 that drive waveform liquid crystal display device 100 is stablized in the output of gate driving circuit 23 carries out picture
It has been shown that, the antijamming capability of display panel and the effect of image quality are improved to reach.
The above described is only a preferred embodiment of the present invention, not make limitation in any form to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to invent, any person skilled in the art,
Do not departing from the range of inventive technique scheme, when the technology contents using the disclosure above make a little change or are modified to equivalent
The equivalent embodiment of change, as long as being without departing from inventive technique scheme content, the technical spirit according to invention is to above example
Any simple modification, equivalent change and modification made, in the range of still falling within technical solution of the present invention.
Claims (8)
1. one kind amplification negater circuit, it is characterised in that the amplification negater circuit is used to export first according to external timing signal
Clock signal and the second clock signal anti-phase with first clock signal, the amplification negater circuit include：First switching element,
Second switch element, first resistor, second resistance and zener diode；
The first switching element includes the first path terminal, alternate path end and the first control terminal, and it is outer which receives this
Portion's clock signal, first path terminal receive external reference high voltage, which is electrically connected to the one of the first resistor
End, the other end of the first resistor receive external reference low-voltage, which is used to export first clock signal, should
Alternate path end is electrically connected to the anode of the zener diode；
The second switch element includes third path end, fourth passage end and the second control terminal, which is electrically connected to
The cathode of the zener diode, the third path end receive the external reference low-voltage, the fourth passage end be electrically connected to this
One end of two resistance, the other end of the second resistance receive the external reference high voltage, the fourth passage end be used to exporting this
Two clock signals.
2. amplification negater circuit as claimed in claim 1, it is characterised in that the amplification negater circuit further comprises the 3rd electricity
Resistance and the 4th resistance；
One end of the 3rd resistor receives the external timing signal, and the other end of the 3rd resistor is electrically connected to first switch member
First control terminal of part, one end of the 4th resistance are electrically connected to the anode of the zener diode, the 4th resistance it is another
End is electrically connected to the alternate path end of the first switching element.
3. amplification negater circuit as claimed in claim 2, it is characterised in that the first switching element and the second switch element
It is triode.
4. amplification negater circuit as claimed in claim 3, it is characterised in that the first switching element is PNP type triode, should
Second switch element is NPN type triode.
5. amplification negater circuit as claimed in claim 4, it is characterised in that first control terminal of the first switching element is
Base stage, first path terminal of the first switching element is emitter, and the alternate path end of the first switching element is current collection
Pole.
6. amplification negater circuit as claimed in claim 5, it is characterised in that second control terminal of the second switch element is
Base stage, the third path end of the second switch element is emitter, and the fourth passage end of the second switch element is current collection
Pole.
7. a kind of liquid crystal display device, including gate driving circuit, it is characterised in that the liquid crystal display device includes right such as will
Seek the amplification negater circuit any one of 1 to 6.
8. liquid crystal display device as claimed in claim 7, it is characterised in that first clock signal in the amplification negater circuit
Two stable units of the gate driving circuit are respectively supplied to the second clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610373889.7A CN105810171B (en) | 2016-05-31 | 2016-05-31 | Amplify negater circuit and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610373889.7A CN105810171B (en) | 2016-05-31 | 2016-05-31 | Amplify negater circuit and liquid crystal display device |
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| Publication Number | Publication Date |
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| CN105810171A CN105810171A (en) | 2016-07-27 |
| CN105810171B true CN105810171B (en) | 2018-04-20 |
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| CN201610373889.7A Active CN105810171B (en) | 2016-05-31 | 2016-05-31 | Amplify negater circuit and liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106409256B (en) * | 2016-11-03 | 2019-04-05 | 昆山龙腾光电有限公司 | A kind of gamma voltage generation circuit and liquid crystal display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369952A (en) * | 2001-01-31 | 2002-09-18 | 日本电气株式会社 | Power circuit without dead lock |
| CN101241766A (en) * | 2007-02-09 | 2008-08-13 | 群康科技(深圳)有限公司 | Shift register and LCD device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101931335B1 (en) * | 2012-03-23 | 2018-12-20 | 엘지디스플레이 주식회사 | Level shifter for liquid crystal display |
-
2016
- 2016-05-31 CN CN201610373889.7A patent/CN105810171B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369952A (en) * | 2001-01-31 | 2002-09-18 | 日本电气株式会社 | Power circuit without dead lock |
| CN101241766A (en) * | 2007-02-09 | 2008-08-13 | 群康科技(深圳)有限公司 | Shift register and LCD device |
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| CN105810171A (en) | 2016-07-27 |
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