CN105762182B - IGBT device with high latch-up resistance - Google Patents
IGBT device with high latch-up resistance Download PDFInfo
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- CN105762182B CN105762182B CN201610298661.6A CN201610298661A CN105762182B CN 105762182 B CN105762182 B CN 105762182B CN 201610298661 A CN201610298661 A CN 201610298661A CN 105762182 B CN105762182 B CN 105762182B
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- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 230000001413 cellular effect Effects 0.000 claims description 101
- 239000004065 semiconductor Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 230000036039 immunity Effects 0.000 claims description 18
- 238000009413 insulation Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 150000002739 metals Chemical class 0.000 description 2
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- TVEXGJYMHHTVKP-UHFFFAOYSA-N 6-oxabicyclo[3.2.1]oct-3-en-7-one Chemical compound C1C2C(=O)OC1C=CC2 TVEXGJYMHHTVKP-UHFFFAOYSA-N 0.000 description 1
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical group NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 1
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Abstract
The invention relates to an IGBT device with high latch-up resistance, wherein an active unit cell of the IGBT device comprises a second conductive type base region and a first conductive type source region; a barrier ring is arranged in the second conductive type base region; on the cross section of the IGBT device, the stop ring comprises a first conduction type buried layer and an insulating medium column, the upper end of the insulating medium column is in contact with source metal, one end of the first conduction type buried layer, which is positioned right below a first conduction type source electrode region, is in contact with the insulating medium column, the other end of the first conduction type buried layer is in contact with the side wall of the conduction channel, the length of the first conduction type buried layer, which is right below the first conduction type source electrode region, is not less than the length of the first conduction type source electrode region, which is positioned in the second conduction type base region, and the first conduction type buried layer and the source metal are insulated from each. The invention has compact structure, can effectively reduce the risk of latch-up, provides a basis for reducing the conduction voltage drop, is compatible with the prior art, and is safe and reliable.
Description
Technical field
The present invention relates to a kind of semiconductor devices, especially a kind of IGBT device with high latch-up immunity belongs to
The technical field of IGBT device.
Background technology
There is parasitic thyristor, i.e. NPNP structures in IGBT device.During proper device operation, it is undesirable to open
Lead to the thyristor of the parasitism.If the parasitic thyristor is in opening state, then the grid of IGBT device will lose to electricity
The control of stream.However, in the IGBT courses of work, if the hole current flowed through below source electrode is too big, source electrode and base area
PN junction will positively biased, i.e. source electrode starts to inject electronics to base area, and base area starts to inject hole to source electrode, brilliant lock parasitic at this time
Pipe is connected, i.e., IGBT device is in latch mode.
The current density that present IGBT is pursued is increasing, and in the case where device high current works, device has generation
The risk of latch.On the one hand it is to increase base below source electrode to reduce the risk that latch occurs during the work time for IGBT device
The doping concentration in area reduces the resistance of this subregion, but this is easy to the threshold voltage of influence device, to setting to device
Meter and manufacture increase difficulty；On the other hand it is the doping concentration for reducing device backside collector, it is hollow to reduce conducting electric current
The ingredient of cave electric current, but this can increase the conduction voltage drop of device and be led especially to the high pressure IGBT device with wide N-type base area
Logical pressure drop can be very big.And when the doping of the device back side is too low, the short-circuit robustness of device can reduce.
As shown in Figure 1, for the structure of existing groove-shaped IGBT device, by taking N-type IGBT device as an example, the IGBT device packet
N-type base area 7 is included, the top in N-type base area 7 is equipped with p-type base area 6, and cellular groove 13, cellular groove are equipped in p-type base area 6
13 slot bottom is located in N-type base area 7, N+ source areas 4 is equipped with above 13 outer wall side of cellular groove, in the side wall of cellular groove 13
And bottom wall is covered with insulation gate oxide 14, and conductive polycrystalline silicon 3 is filled in cellular groove 13.Front in N-type base area 7
Equipped with source metal 1, the source metal 1 is dielectrically separated from by the insulating medium layer 2 on N-type base area 7 with conductive polycrystalline silicon 3,
Source metal 1 and the p-type heavily doped region 5 in N+ source areas 4 and p-type base area 6, the p-type heavily doped region 5 is in p-type base area 6
The lower section of N+ source areas 4 is also extended to, but p-type heavily doped region 5 is not in contact with the outer wall of cellular groove 13.In N-type base area 7
The back side be equipped with collector structure, the collector structure include p-type collecting zone 9 and with 9 Ohmic contact of p-type collecting zone
Collector electrode metal 10.
When specific works, the region part that p-type heavily doped region 5 is located at 4 lower section of N+ source areas can form anti-bolt lock structure 11,
In order to make device have high anti-latch performance, the p-type doping concentration formed in anti-bolt lock structure 11 must be very high, while high
Doping must also be as close as the side wall of cellular groove 13, and is adulterated and directly affected due to the p-type of 13 side wall of cellular groove
The threshold voltage of IGBT device, therefore the anti-bolt lock structure 11 brings prodigious difficulty to IGBT device design and processes.
On the other hand, in order to make IGBT device that latch, the doping concentration one of p-type collecting zone 9 not occur in use
As it is relatively low, junction depth is generally also than shallower, this makes 7 injected holes of N-type base area fewer, and conductivity modulation effect is not shown
It writes, IGBT device conduction voltage drop can be caused bigger.
Invention content
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of IGBT with high latch-up immunity is provided
Device, it is compact-sized, the risk that latch occurs can be effectively reduced, basis is provided to reduce conduction voltage drop, with prior art phase
It is compatible, securely and reliably.
According to technical solution provided by the invention, the IGBT device with high latch-up immunity, including there are two tools
The semiconductor substrate of opposing main faces, two opposing main faces of semiconductor substrate include the first interarea and corresponding with the first interarea
The second interarea；It include the first conduction type base region between the first interarea and the second interarea of semiconductor substrate；In semiconductor substrate
The first conduction type base region in several regular arrays of setting and the active cellular for the distribution that is mutually parallel, the active cellular include
Positioned at the second conduction type base region of the first conduction type base region internal upper part and in second conduction type base region
First conductive type source area, second conduction type base region, the first conductive type source area and semiconductor substrate first are led
Source metal Ohmic contact on face；
Blocker ring of the setting positioned at the first conductive type source area outer ring in second conduction type base region；Described
On the section of IGBT device, the blocker ring includes the first conduction type buried layer and dielectric column, the dielectric column
Positioned at the outside of the first conductive type source area, the upper end of dielectric column is contacted with source metal, the first conduction type buried layer
One end immediately below the first conductive type source area is in contact with dielectric column, the other end of the first conduction type buried layer
It is contacted with conducting channel side wall, length of the first conduction type buried layer immediately below the first conductive type source area is not less than first
Length of the conductive type source area in the second conduction type base region, the first conduction type buried layer and source metal mutually insulated,
And first between conduction type buried layer and the first conductive type source area and the first conduction type buried layer and the first conduction type base
Pass through the second conduction type base region interval between area.
Be equipped with collector structure on the second interarea of semiconductor substrate, the collector structure include collector electrode metal with
And the collector layer with the collector electrode metal Ohmic contact, collector layer are located at the second of collector electrode metal and semiconductor substrate
Between interarea, the collector layer includes the second conduction type collecting zone.
It is additionally provided with the first conductive type buffer layer between the collector layer and the second interarea of semiconductor substrate.
The collector layer further includes several first conduction type collecting zones being located in the second conduction type collecting zone, the
One conduction type collecting zone and collector electrode metal Ohmic contact.
The active cellular is in planar or channel form.
When the active cellular uses planar structure, on the section of the IGBT device, the flat surface active cellular
Including two the second adjacent conduction type base regions and the first conduction type source electrode in second conduction type base region
Area, the second adjacent conduction type base region separately, are being spaced adjacent second conductive type base by the first conduction type base region
The surface of first conduction type base region in area is equipped with conductive polycrystalline silicon and insulating medium layer, and conductive polycrystalline silicon is situated between by insulating
The first interarea and source metal of matter layer and semiconductor substrate are dielectrically separated from, and the first of the both ends of conductive polycrystalline silicon and lower section
Conductive type source area overlaps mutually, and the first conduction type buried layer is respectively provided in each second conduction type base region and insulation is situated between
Matter column, one end immediately below the first conductive type source area are in contact with dielectric column, the first conduction type buried layer
The other end is in contact with the insulating medium layer on the first interarea of semiconductor substrate, the conductive polycrystalline silicon and gate metal ohm
Contact.
When the active cellular uses channel form structure, on the section of the IGBT device, the active cellular includes
The slot bottom of cellular groove in the second conduction type base region, the cellular groove is located at below the second conduction type base region
In first conduction type base region, the inner wall and bottom wall of cellular groove are covered with insulation gate oxide, and are being covered with insulation grid oxygen
Change and be filled with conductive polycrystalline silicon in the cellular groove of layer, the notch of cellular groove is situated between by the insulation on the first interarea of semiconductor substrate
Matter layer covers, and the conductive polycrystalline silicon in cellular groove is dielectrically separated from by insulating medium layer and source metal；First conduction type
Source area is located above cellular groove outer wall side, the first conductive type source area, the other end and the member of the first conduction type buried layer
Born of the same parents' groove outer wall is in contact, the conductive polycrystalline silicon in cellular groove and gate metal Ohmic contact.
The material of the semiconductor substrate includes silicon, and the dielectric column includes silica column, dielectric column
Height is less than the thickness of the second conduction type base region.
The shape of the active cellular is in bar shaped, rectangular or round.
The the second conduction type heavily doped region for being used to form anti-bolt lock structure is equipped in the first conduction type blocker ring,
The second conduction type heavily doped region is located at the outside and lower section of the first conductive type source area, and the second conduction type is heavily doped
Miscellaneous area is contacted with the first conductive type source area, and the second conduction type heavily doped region is below the first conductive type source area
Length is less than the length of the first conductive type source area.
In " first conduction type " and " the second conduction type " the two, for N-type IGBT device, the first conduction type
Refer to N-type, the second conduction type is p-type；For p-type IGBT device, the type of the first conduction type and the second conduction type meaning
It is exactly the opposite with N-type IGBT device.
Advantages of the present invention：
1, first conduction type buried layer is set in the second conduction type base region, the first conduction type buried layer is led positioned at first
Zone length immediately below electric type source area is more than the length of the first conductive type source area, and the one of the first conduction type buried layer
End is contacted with dielectric column, and the other end is contacted with active cellular conducting channel side wall；By the first conduction type buried layer by
Surrounded below one conductive type source area, with effectively by electronic current and hole current carry out it is discrete open, significantly subtract
It is small or even prevent hole current from flowing through the lower section of the first conductive type source area, only an electronic current is allowed to flow to first by raceway groove
Conductive type source area can improve the latch-up immunity of IGBT device, basis be provided to reduce conduction voltage drop, with prior art
It is mutually compatible, securely and reliably.
2, when the first conduction type buried layer when being formed, can be limited first by dielectric column and led by double thermal diffusions
The horizontal proliferation of electric type buried layer, to reduce the size of IGBT device cellular；When the first conduction type buried layer passes through other works
When skill formation, the concentration of the first conduction type buried layer fringe field can be prevented, improves reliability, and first can be improved and led
The doping concentration of electric type buried layer, further increases the latch-up immunity of device.
Description of the drawings
Fig. 1 is the sectional view of existing groove-shaped IGBT device.
Fig. 2 is the sectional view of groove PT type IGBT devices of the present invention.
Fig. 3 is the sectional view of plane PT type IGBT devices of the present invention.
Fig. 4 is the sectional view of groove NPT type IGBT devices of the present invention.
Fig. 5 is the sectional view of groove PT types RC IGBT devices of the present invention.
Fig. 6 is the sectional view of groove NPT types RC IGBT devices of the present invention.
Fig. 7 is the sectional view of plane NTP type IGBT devices of the present invention.
Fig. 8 is the sectional view of plane PT types RC IGBT devices of the present invention.
Fig. 9 is the sectional view of plane NPT types RC IGBT devices of the present invention.
Figure 10 is the elongated structural schematic diagram of the active cellular of the present invention.
Figure 11 is the structural schematic diagram that the active cellular of the present invention is square.
Figure 12 is the active rounded structural schematic diagram of cellular of the present invention.
Reference sign：1- source metals, 2- insulating medium layers, 3- conductive polycrystalline silicons, 4-N+ source areas, 5-P type weights
Doped region, 6-P types base area, 7-N types base area, 8-N types buffer layer, 9-P types collecting zone, 10- collector electrode metals, the anti-latch knots of 11-
Structure, 12-N types buried layer, 13- cellulars groove, 14- insulation gate oxide, 15-N types collecting zone and the active cellulars of 16- and 17- are exhausted
Edge dielectric posts.
Specific implementation mode
With reference to specific drawings and examples, the invention will be further described.
In order to effectively reduce the risk that latch occurs, basis is provided to reduce conduction voltage drop, is with N-type IGBT device
Example, the present invention include that there are two the semiconductor substrates of opposing main faces for tool, and two opposing main faces of semiconductor substrate include the first master
Face and the second interarea corresponding with the first interarea；It include N-type base area between the first interarea and the second interarea of semiconductor substrate
7；Several regular arrays of setting and the active cellular 16 for the distribution that is mutually parallel, described active in the N-type base area 7 of semiconductor substrate
Cellular 16 includes positioned at the p-type base area 6 of 7 internal upper part of N-type base area and the N+ source areas 4 in the p-type base area 6, the P
Type base area 4, N+ source areas 4 and 1 Ohmic contact of source metal on the first interarea of semiconductor substrate；
Blocker ring of the setting positioned at 4 outer ring of N+ source areas in the p-type base area 6；On the section of the IGBT device,
The blocker ring includes n type buried layer 12 and dielectric column 17, and the dielectric column 17 is located at the outside of N+ source areas 4,
The upper end of dielectric column 17 is contacted with source metal 1, and n type buried layer 12 is located at one end immediately below N+ source areas 4 and is situated between with insulation
Matter column 17 is in contact, and the other end of n type buried layer 12 is in contact with the side wall of 16 conducting channel of active cellular, and n type buried layer 12 is in N
Length immediately below+source area 4 is not less than length of the N+ source areas 4 in p-type base area 6, n type buried layer 12 and 1 phase of source metal
Mutually insulation, and be spaced by p-type base area 6 between n type buried layer 12 and N source areas 4 and between n type buried layer 12 and N-type base area 7.
Specifically, the material of semiconductor substrate includes silicon, and certainly, semiconductor substrate commonly can also partly be led using other
Body material, for N-type IGBT device, the conduction type of semiconductor substrate is N-type, and usually, the front of semiconductor substrate is formed
The back side of first interarea, semiconductor substrate forms the second interarea, and the first interarea is corresponding with the second interarea.P-type base area 6 is located at N
Top in type base area 7, N+ source areas 4 are located in p-type base area 6, p-type base area 6 and 1 Ohmic contact of source metal.It is described active
The shape of cellular 16 is in bar shaped, rectangular or round, respectively as shown in Figure 10, Figure 11 and Figure 12.
Blocker ring is located in p-type base area 6, and blocker ring is located at blocking annular in the outer ring of N+ source areas 4, i.e. N+ source areas 4
At surround ring in, N+ source areas 4 are located at the top in p-type base area 6, and top and the semiconductor substrate first of N+ source areas 4 are led
1 direct Ohmic contact of source metal on face.It is formed by blocker ring and surrounds 4 lower section surround ring of N+ source areas, the one of blocker ring
End is dielectrically separated from source metal 1, and the other end is contacted with 16 conducting channel side wall of active cellular.Blocker ring in p-type base area 6
It is equivalent to a hole barrier, therefore, can effectively open electronic current and hole current are discrete, can significantly reduce very
To preventing hole current from and electronic current only being allowed to flow to N+ source areas 4 by raceway groove through the lower section of N+ source areas 4, so as to
To improve the latch-up immunity of IGBT device.
When it is implemented, on the section of the IGBT device, blocker ring includes dielectric column 17 and n type buried layer
12, dielectric column 17 is in vertical distribution in p-type base area 6, and n type buried layer 12 is respectively positioned on dielectric column 17 with N+ source areas 4
The same side, dielectric column 17 may be used the forms such as silica column, and the upper end of dielectric column 17 and source metal 1 are straight
Contact, height of the dielectric column 17 in p-type base area 6 are less than the depth of p-type base area 6.N type buried layer 12 includes being located at N+ source electrodes
Region immediately below area 4, and one end of the n type buried layer 12 immediately below N+ source areas 4 is in contact with dielectric column 17, it is described
The other end of n type buried layer 12 is in contact with the side wall of the conducting channel of active cellular 16, i.e., the other end of n type buried layer 12 can position
In the underface of N+ source areas 4 or positioned at the outside of N+ source areas 4, position and the active cellular 16 of 12 other end of n type buried layer
Concrete form is related, and specially known to those skilled in the art, and will not be described here in detail.Dielectric column 17 and N+ source areas 4
It is non-contact.N type buried layer 12 can be dielectrically separated from by dielectric column 17 with source metal 1.
In the embodiment of the present invention, when n type buried layer 12 when being formed, can be limited by double thermal diffusions by dielectric column 17
The horizontal proliferation of n type buried layer 12 processed, so as to reduce the size of IGBT device cellular；When n type buried layer 12 passes through other techniques（Such as
Extension+ion implanting）When formation, the method by etching a groove and filling dielectric can prevent n type buried layer 12
The concentration of fringe field improves reliability, and can improve the doping concentration of n type buried layer 12, to improve the anti-door bolt of device
Lock ability.
In the specific implementation, the active cellular 16 is in planar or channel form, can be specifically determined as needed,
Active cellular 16 is illustrated in the form of planar and channel form below.
When the active cellular 16 is using planar structure, on the section of the IGBT device, the flat surface active member
Born of the same parents include that two adjacent p-type base areas 6 and the N+ source areas 4 in the p-type base area 6, adjacent p-type base area 6 pass through N-type
Base area 7 separately, in the surface for being spaced the N-type base area 7 of adjacent p-type base area 6 is equipped with conductive polycrystalline silicon 3 and insulating medium layer
2, conductive polycrystalline silicon 3 is dielectrically separated from by insulating medium layer 2 and the first interarea and source metal 1 of semiconductor substrate, and is led
The both ends of electric polysilicon 3 and the N+ source areas 4 of lower section overlap mutually, be respectively provided in each p-type base area 6 n type buried layer 12 and absolutely
Edge dielectric posts 17, one end that n type buried layer 12 is located at immediately below N+ source areas 4 are in contact with dielectric column 17, n type buried layer 12
The other end is in contact with the insulating medium layer 2 on the first interarea of semiconductor substrate, the conductive polycrystalline silicon 3 and gate metal Europe
Nurse contacts.
In the embodiment of the present invention, when the use of active cellular 16 is planar, on the section of IGBT device, p-type base area 6 exists
It is in discontinuous distribution in N-type base area 7, it is spaced by N-type base area 7 between adjacent p-type base area 6；For an active cellular
16, there are in two adjacent p-type base area 6 N+ source areas 4, the doping concentration of N+ source areas 4 to be more than the doping of N-type base area 7
Concentration.It is respectively provided with n type buried layer 12 and dielectric column 17 in each p-type base area 6, under n type buried layer 12 is located at N+ source areas 4 just
One end of side is in contact with dielectric column 17, the other end and the insulation on the first interarea of semiconductor substrate of n type buried layer 12
Dielectric layer 2 is in contact, i.e. n type buried layer 12 in addition to there are the region immediately below N+ source areas 4, there is also with 17 phase of dielectric column
The upper end of parallel part, the part parallel with dielectric column 17 is in contact with insulating medium layer 2, to pass through insulation
Dielectric posts 17 and n type buried layer 12 can carry out the lower section of the N+ source areas 4 in each p-type base area 6 and lateral area effective
It surrounds.
Conductive polycrystalline silicon 3 is surrounded by cellular insulating medium layer 2, and both ends and 4 part of N+ source areas of conductive polycrystalline silicon 3 are handed over
Folded, the part that conductive polycrystalline silicon 3 and N+ source areas 4 overlap mutually is spaced by cellular insulating medium layer 2, N+ source areas 4 remaining
Part and 1 Ohmic contact of source metal.In order to form the grid of IGBT device, after all conductive polycrystalline silicon 3 is drawn with
Conductive polycrystalline silicon 3 is drawn and this technology may be used with the concrete form of gate metal Ohmic contact by gate metal Ohmic contact
The common form in field, specially known to those skilled in the art, details are not described herein again.
When active cellular 16 is flat surface active cellular, the collector structure difference at the flat surface active cellular back side can obtain
PT type IGBT or NPT types IGBT, Fig. 3 are plane PT type IGBT devices, and Fig. 7 is plane NPT type IGBT devices.For plane NPT
Type IGBT device, the collector structure include collector electrode metal 10 and the p-type with 10 Ohmic contact of the collector electrode metal
Collecting zone 9, p-type collecting zone 9 are located between collector electrode metal 10 and the second interarea of semiconductor substrate.For plane PT type IGBT devices
Part, is additionally provided with N-type buffer layer 8 between the p-type collecting zone 9 and the second interarea of semiconductor substrate, the N-type buffer layer 8 abuts N
Type base area 7 and p-type collecting zone 9.
In addition, according to the difference of collector layer, moreover it is possible to form RC IGBT（Reverse conducting insulated
gate bipolar transistor）Device, Fig. 8 is plane PT type RC IGBT devices, if being additionally provided in p-type collecting zone 9
Dry N-type collecting zone 15, forms collector layer, to obtain plane PT type RC IGBT devices by p-type collecting zone 9 and N-type collecting zone 15
Part.In Fig. 9, it also is provided with several N-type collecting zones 15 in p-type collecting zone 9, passes through matching for p-type collecting zone 9 and N-type collecting zone 15
It closes, to obtain plane NPT type RC IGBT devices.It is worked when by the IGBT device being differently formed of collector structure
Known to Cheng Junwei those skilled in the art, details are not described herein again.
When the active cellular 16 is using channel form structure, the active cellular of groove includes the member being located in p-type base area 6
Born of the same parents' groove 13, the slot bottom of the cellular groove 13 are located in the N-type base area 7 of 6 lower section of p-type base area, the inner wall of cellular groove 13 and
Bottom wall is covered with insulation gate oxide 14, and conductive polycrystalline is filled in the cellular groove 13 for being covered with insulation gate oxide 14
13 notches of silicon 3, cellular groove are covered by the insulating medium layer 2 on the first interarea of semiconductor substrate, leading in cellular groove 13
Electric polysilicon 3 is dielectrically separated from by insulating medium layer 2 and source metal 1；N+ source areas 4 are located on 13 outer wall side of cellular groove
Side, N+ source areas 4, N-type blocker ring 12 are in contact with 13 outer wall of cellular groove, the conductive polycrystalline silicon 3 in cellular groove 13 and grid
Pole metal ohmic contact.
When it is implemented, the notch of cellular groove 13 is located on the first interarea of semiconductor substrate, and by semiconductor substrate
The first interarea extend vertically downward, cellular groove 13 passes through p-type base area 6, and the slot bottom of cellular groove 13 is located under p-type base area 6
In the N-type base area 7 of side.By techniques such as thermal oxides, there is insulation gate oxide 14 in side wall and the bottom wall growth of cellular groove 13,
The gate oxide 14 that insulate can be silicon dioxide layer, and filling is conductive more in the cellular groove 13 that growth has insulation gate oxide 14
Crystal silicon 3, conductive polycrystalline silicon 3 fill up cellular groove 13, and the insulating medium layer 2 of 13 notch of cellular groove blocks cellular conductive polycrystalline silicon
3, so that conductive polycrystalline silicon 3 is dielectrically separated from source metal 1.The doping concentration of N+ source areas 4 is more than the doping of N-type base area 7
Concentration, the depth of N+ source areas 4 are less than the depth of p-type base area 5, and N+ source areas 4 are in contact with the lateral wall of cellular groove 13, and
With 1 Ohmic contact of source metal, so as to form the source terminal of required IGBT device.
On the section of IGBT device, dielectric column 17 is mutually parallel with cellular groove 13, the height of dielectric column 17
Degree is less than the depth of cellular groove 13, and dielectric column 17 and n type buried layer 12 are symmetrically distributed in the both sides of cellular groove 13, this
When, n type buried layer 12 exists only in immediately below N+ source areas 4, the both ends of n type buried layer 12 respectively with dielectric column 17 and cellular
The outer wall of groove 13 is in contact, and so as to realize effective encirclement to N+ source areas 4, realizes to electronic current and hole current
It is effectively discrete to open, it is substantially reduced or even prevent hole current from flowing through the lower section of N+ source areas 4.Conductive polycrystalline silicon in cellular groove 13
Connection between 3 and gate metal is with being combined into known to those skilled in the art, and details are not described herein again.
In the cellular active for groove of active cellular 16, the collector structure difference at the active cellular back side of groove can obtain
PT type IGBT or NPT types IGBT, Fig. 2 are groove PT type IGBT devices, and Fig. 4 is groove NPT type IGBT devices.For groove NPT
Type IGBT device, the collector structure include collector electrode metal 10 and the p-type with 10 Ohmic contact of the collector electrode metal
Collecting zone 9, p-type collecting zone 9 are located between collector electrode metal 10 and the second interarea of semiconductor substrate.For groove PT type IGBT devices
Part, is additionally provided with N-type buffer layer 8 between the p-type collecting zone 9 and the second interarea of semiconductor substrate, the N-type buffer layer 8 abuts N
Type base area 7 and p-type collecting zone 9.
In addition, according to the difference of collector layer, moreover it is possible to form RC IGBT（Reverse conducting insulated
gate bipolar transistor）Device, Fig. 5 is groove PT type RC IGBT devices, if being additionally provided in p-type collecting zone 9
Dry N-type collecting zone 15, forms collector layer, to obtain groove PT type RC IGBT devices by p-type collecting zone 9 and N-type collecting zone 15
Part.In Fig. 6, it also is provided with several N-type collecting zones 15 in p-type collecting zone 9, passes through matching for p-type collecting zone 9 and N-type collecting zone 15
It closes, to obtain groove NPT type RC IGBT devices.It is worked when by the IGBT device being differently formed of collector structure
Known to Cheng Junwei those skilled in the art, details are not described herein again.
Further, the p-type heavily doped region 5 for being used to form anti-bolt lock structure 11 is equipped in the N-type blocker ring 12, it is described
P-type heavily doped region 5 is located at the outside and lower section of N+ source areas 4, and p-type heavily doped region 5 is contacted with N+ source areas 4, and p-type is heavily doped
Length of the miscellaneous area 5 below N+ source areas 4 is less than the length of N+ source areas.
In the embodiment of the present invention, no matter active cellular 16 uses flat surface active cellular or the active cellular of groove, active
Existing anti-bolt lock structure 11 can be set in cellular 16；The anti-bolt lock structure 11 includes the p-type coordinated with N+ source areas 4
Heavily doped region 5, the doping concentration of the p-type heavily doped region 5 are more than the doping concentration of p-type base area 6.P-type heavily doped region 5 is located at P
In type base area 6, p-type heavily doped region 5 is located at length of the length less than N+ source areas 4 of 4 lower section of N+ source areas, i.e., when active cellular
When 16 cellular active for groove, p-type heavily doped region 5 is not in contact with the outer wall of cellular groove 13.P-type heavily doped region 5 and the sources N+
Polar region 4 cooperatively form concrete form of anti-bolt lock structure 11 etc. with it is existing identical, details are not described herein again.
N type buried layer 12 is arranged in the present invention in p-type base area 6, and the region that n type buried layer 12 is located at immediately below N+ source areas 4 is long
Degree is more than the length of N+ source areas 4, i.e., is between n type buried layer 12 and N+ source areas 4 and between n type buried layer 12 and N-type base area 7
One end of p-type base area 6, n type buried layer 12 is contacted with dielectric column 17, and the other end of n type buried layer 12 is led with active cellular 16
Electric trench sidewalls contact；The lower section of N+ source areas 4 is surrounded by n type buried layer 12, with effectively by electronic current and sky
Cave electric current progress is discrete to open, and is substantially reduced or even prevents hole current from flowing through the lower section of N+ source areas 4, only allows an electronic current logical
It crosses raceway groove and flows to N+ source areas 4, the latch-up immunity of IGBT device can be improved, basis is provided to reduce conduction voltage drop, and it is existing
There is technique to be mutually compatible with, securely and reliably.
Claims (10)
1. a kind of IGBT device with high latch-up immunity, including there are two the semiconductor substrate of opposing main faces, semiconductors for tool
Two opposing main faces of substrate include the first interarea and the second interarea corresponding with the first interarea；The first of semiconductor substrate
It include the first conduction type base region between interarea and the second interarea；It is arranged in the first conduction type base region of semiconductor substrate several
Regular array and the active cellular for the distribution that is mutually parallel, the active cellular include being located at the first conduction type base region internal upper part
Second conduction type base region and the first conductive type source area in second conduction type base region, described second leads
Electric type base area, the first conductive type source area and the source metal Ohmic contact on the first interarea of semiconductor substrate；Its feature
It is：
Blocker ring of the setting positioned at the first conductive type source area outer ring in second conduction type base region；In the IGBT
On the section of device, the blocker ring includes the first conduction type buried layer and dielectric column, and the dielectric column is located at
The upper end in the outside of the first conductive type source area, dielectric column is contacted with source metal, and the first conduction type buried layer is located at
One end immediately below first conductive type source area is in contact with dielectric column, the other end of the first conduction type buried layer with lead
Electric trench sidewalls contact, and length of the first conduction type buried layer immediately below the first conductive type source area is led not less than first
Length of the electric type source area in the second conduction type base region, the first conduction type buried layer and source metal mutually insulated, and
Between first conduction type buried layer and the first conductive type source area and the first conduction type buried layer and the first conduction type base region
Between pass through the second conduction type base region interval.
2. the IGBT device according to claim 1 with high latch-up immunity, it is characterized in that：The of semiconductor substrate
Two interareas are equipped with collector structure, and the collector structure includes collector electrode metal and connect with described collector electrode metal ohm
Tactile collector layer, collector layer are located between collector electrode metal and the second interarea of semiconductor substrate, and the collector layer includes
Second conduction type collecting zone.
3. the IGBT device according to claim 2 with high latch-up immunity, it is characterized in that：The collector layer and half
It is additionally provided with the first conductive type buffer layer between second interarea of conductor substrate.
4. the IGBT device according to claim 2 with high latch-up immunity, it is characterized in that：The collector layer also wraps
Include several first conduction type collecting zones in the second conduction type collecting zone, the first conduction type collecting zone and collector
Metal ohmic contact.
5. the IGBT device according to claim 1 with high latch-up immunity, it is characterized in that：The active cellular is in flat
Planar or channel form.
6. the IGBT device according to claim 5 with high latch-up immunity, it is characterized in that：The active cellular uses
When planar structure, on the section of the IGBT device, the flat surface active cellular includes two the second adjacent conduction types
Base area and the first conductive type source area in second conduction type base region, the second adjacent conduction type base region
Separately by the first conduction type base region, the first conduction type base region of interval adjacent second conductive type base area just on
Side is equipped with conductive polycrystalline silicon and insulating medium layer, the first interarea that conductive polycrystalline silicon passes through insulating medium layer and semiconductor substrate
And source metal is dielectrically separated from, and the first conductive type source area of the both ends of conductive polycrystalline silicon and lower section overlaps mutually, every
It is respectively provided with the first conduction type buried layer and dielectric column in a second conduction type base region, is located at the first conduction type source electrode
One end immediately below area is in contact with dielectric column, and the other end and the semiconductor substrate first of the first conduction type buried layer are led
Insulating medium layer on face is in contact, the conductive polycrystalline silicon and gate metal Ohmic contact.
7. the IGBT device according to claim 5 with high latch-up immunity, it is characterized in that：The active cellular uses
When channel form structure, on the section of the IGBT device, the active cellular includes being located in the second conduction type base region
The slot bottom of cellular groove, the cellular groove is located in the first conduction type base region below the second conduction type base region, cellular
The inner wall and bottom wall of groove are covered with insulation gate oxide, and are filled with and lead in the cellular groove for being covered with insulation gate oxide
The notch of electric polysilicon, cellular groove is covered by the insulating medium layer on the first interarea of semiconductor substrate, leading in cellular groove
Electric polysilicon is dielectrically separated from by insulating medium layer and source metal；First conductive type source area is located at cellular groove outer wall side
Top, the first conductive type source area, the first conduction type buried layer the other end be in contact with cellular groove outer wall, cellular groove
Interior conductive polycrystalline silicon and gate metal Ohmic contact.
8. the IGBT device according to claim 1 with high latch-up immunity, it is characterized in that：The semiconductor substrate
Material includes silicon, and the dielectric column includes silica column, and the height of dielectric column is less than the second conduction type base region
Thickness.
9. the IGBT device according to claim 1 with high latch-up immunity, it is characterized in that：The shape of the active cellular
Shape is in bar shaped, rectangular or round.
10. the IGBT device according to claim 1 with high latch-up immunity, it is characterized in that：First conductive-type
The the second conduction type heavily doped region for being used to form anti-bolt lock structure, the second conduction type heavy doping are equipped in type blocker ring
Area is located at the outside and lower section of the first conductive type source area, the second conduction type heavily doped region and the first conduction type source electrode
Area contacts, and length of the second conduction type heavily doped region below the first conductive type source area is less than the first conduction type source
The length of polar region.
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| CN107256885B (en) * | 2017-06-30 | 2022-08-26 | 北京工业大学 | High-reliability insulated gate bipolar transistor and manufacturing method thereof |
| CN107994073B (en) * | 2017-12-27 | 2023-08-15 | 江苏中科君芯科技有限公司 | Low-on-state voltage drop IGBT capable of improving latch-up resistance |
| CN113497112B (en) * | 2020-03-19 | 2023-05-05 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, intelligent power device and electronic product |
| CN117497576B (en) * | 2023-11-30 | 2024-09-27 | 江苏索力德普半导体科技有限公司 | Groove type SiC power device with heterojunction and preparation method |
| CN117476757A (en) * | 2023-12-28 | 2024-01-30 | 深圳天狼芯半导体有限公司 | IGBT with high latch-up resistance and preparation method |
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| CN102064191A (en) * | 2010-11-02 | 2011-05-18 | 浙江大学 | Insulated gate bipolar transistor (IGBT) |
| CN205621739U (en) * | 2016-05-04 | 2016-10-05 | 江苏中科君芯科技有限公司 | IGBT device with high latch-up resistance |
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