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CN105761755B - Memory device, electric charge pump circuit and its voltage pump swash method - Google Patents

Memory device, electric charge pump circuit and its voltage pump swash method Download PDF

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Publication number
CN105761755B
CN105761755B CN201610008971.XA CN201610008971A CN105761755B CN 105761755 B CN105761755 B CN 105761755B CN 201610008971 A CN201610008971 A CN 201610008971A CN 105761755 B CN105761755 B CN 105761755B
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Prior art keywords
voltage
clock signal
output
charge pump
latch
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CN105761755A (en
Inventor
邵启意
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eMemory Technology Inc
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eMemory Technology Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
    • H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • H04L63/0457—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply dynamic encryption, e.g. stream encryption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G06F21/32—User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/606—Protecting data by securing the transmission between two devices or processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
    • H04L63/0861—Network architectures or network communication protocols for network security for authentication of entities using biometrical features, e.g. fingerprint, retina-scan
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3226—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using a predetermined code, e.g. password, passphrase or PIN
    • H04L9/3231—Biological data, e.g. fingerprint, voice or retina
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Health & Medical Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Software Systems (AREA)
  • Nonlinear Science (AREA)
  • Biomedical Technology (AREA)
  • Computing Systems (AREA)
  • Bioethics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biodiversity & Conservation Biology (AREA)
  • Multimedia (AREA)
  • Human Computer Interaction (AREA)
  • Dc-Dc Converters (AREA)
  • Read Only Memory (AREA)
  • Image Input (AREA)
  • Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
  • Collating Specific Patterns (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)

Abstract

Memory device, electric charge pump circuit and its voltage pump swash method.The present invention provides a kind of memory device, electric charge pump circuit and the pumped method of voltage.Electric charge pump circuit includes multiple delay cells, latch cicuit and multiple charge pump units.According to output clock signal, delay cell generates multiple clock signals respectively.Latch cicuit receives the final stage clock signal of clock signal and latches enable signal.Latch cicuit decides whether to latch final stage clock signal or generates output clock signal according to enable signal is latched.The charge pump unit of the first order receives an input voltage, and according to clock signal and output clock signal.Charge pump unit executes the pumped operation of voltage for input voltage to generate output voltage.

Description

Memory device, electric charge pump circuit and its voltage pump swash method
Technical field
The present invention relates to a kind of electric charge pump circuit and a kind of pumped method of voltage, and in particular to a kind of charge pump Circuit and the pumped method of voltage, to generate a program voltage and/or voltage of erasing to memory device.
Background technique
In recent years, non-volatile memory device application becomes increasingly popular in an electronic, in order to deposit non-volatile Program voltage and voltage of erasing are provided in reservoir device, in the prior art, electric charge pump circuit is filled in nonvolatile memory It is required in setting.
In the prior art, electric charge pump circuit is by the construction of multiple charge pump unit institutes, charge pump unit sequentially needle It is boosted to input voltage to generate output voltage.Voltage side Pu unit carries out voltage based on corresponding clock signal Pumped operation.If it is known that electric charge pump circuit cannot be instant stopping clock signal, then unwanted clock pulses will It is passed in charge pump unit, and output voltage is made to generate unnecessary ripple.In addition, when electric charge pump circuit again by When starting, one due to charge pump cellular chain caused by delay time be necessary on the time for regenerate output voltage , also, in above-mentioned delay time, the reduction of output voltage and other ripples on output voltage can be all generated. In other words, in the prior art, there are more ripples and peak point currents for electric charge pump circuit, therefore reduce output voltage Efficiency.
Summary of the invention
The present invention provides a kind of electric charge pump circuit and the pumped method of voltage, to generate output voltage, have reduce it is defeated The function of ripple and reduction peak point current out.
The present invention also provides a kind of memory device with electric charge pump circuit, and electric charge pump circuit is used to one A program voltage and voltage of erasing have the function of reducing output ripple and reduce peak point current.
The present invention provides a kind of electric charge pump circuit, includes multiple delay cells, latch and multiple charge pump lists Member.Delay cell is serially connected coupling, and wherein delay cell respectively generates multiple clock signals according to output clock signal.Lock Circuit coupled delay unit is deposited, the afterbody clock signal in clock signal is received and latches enable signal, wherein latching Circuit decides whether to generate output clock signal according to latch enable signal to latch afterbody clock signal.Charge pump Unit is serially connected coupling, and wherein first order charge pump unit receives input voltage, also, charge pump unit is according to clock Signal and output clock signal are to generate output voltage for the pumped operation of output voltage progress voltage.
The present invention provides a kind of memory device, including an electric charge pump circuit.Electric charge pump circuit includes multiple delays Unit, latch and multiple charge pump units.Delay cell is serially connected coupling, and wherein delay cell is according to output clock Signal respectively generates multiple clock signals.Latch cicuit coupled delay unit receives the afterbody clock in clock signal Signal and latch enable signal, wherein latch cicuit decides whether according to enable signal is latched to latch afterbody clock letter Number generate output clock signal.Charge pump unit is serially connected coupling, and wherein first order charge pump unit receives input Voltage, also, charge pump unit carries out the pumped behaviour of voltage according to clock signal and output clock signal to be directed to output voltage Make to generate output voltage.Wherein, output voltage is used as program voltage and at least one in voltage of erasing.
The present invention more provides a kind of pumped method of voltage, and the pumped method of this voltage includes: by sequentially delayed output clock Signal is to generate multiple clock signals；Input voltage is received, and according to clock signal and output clock signal for output electricity The pumped operation of press operation voltage is to generate output voltage；And when the voltage level of output voltage reaches the voltage of reference voltage When level, then the voltage level of the afterbody clock signal of latching clock signal is to generate output clock signal.
According to foregoing description, the present invention provides the electric charge pump circuit with latch cicuit.In the pumped operation of voltage The time point being completed can latch afterbody clock signal according to enable signal is latched, in this way, unwanted clock will not It is transferred into charge pump unit, the voltage levels constant of output voltage can be kept, and be can be reduced and be present in voltage side Output ripple and peak point current in pump circuit.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is painted the schematic diagram of the electric charge pump circuit of one embodiment of the invention.
Fig. 2 is painted the schematic diagram of the electric charge pump circuit of another embodiment of the present invention.
Fig. 3 is painted the schematic diagram of the electric charge pump circuit of yet another embodiment of the invention.
Fig. 4 is painted the schematic diagram of the electric charge pump circuit of yet another embodiment of the invention.
Fig. 5 is painted the schematic diagram for the adjustment circuit that the embodiment of the present invention illustrates.
Fig. 6 is painted the schematic diagram of the memory device of the embodiment of the present invention.
Fig. 7 is painted the flow chart of the pumped method of voltage of the embodiment of the present invention.
[symbol description]
100,200,300,400,620: electric charge pump circuit
111-11N, 211-214,311-314,411-414: charge pump unit
121-12M, 221-223,321-323,421-423: delay cell
IN1-IN5, IN9, INA-D: phase inverter
130,230,330,430: latch cicuit
CKO: output clock signal
CK1-CKM: clock signal
VOUT: output voltage
VIN: input voltage
ENPUMP: enable signal is latched
Vref: reference voltage
Vfb: feedback voltage
C1: capacitor
R1: voltage
GND: ground terminal is referred to
DCK3: slow clock signal
LAT1: latch
OP1: operational amplifier
I1: negative input end
I2: positive input terminal
510: divider
600: memory device
610: memory crystal cell array
ERS: voltage of erasing
PGM: program voltage
S710, S720, S730: the pumped step of voltage
Specific embodiment
Referring to FIG. 1, Fig. 1 is painted the schematic diagram of the electric charge pump circuit of one embodiment of the invention.Electric charge pump circuit 100 Including charge pump unit 111-11N, delay cell 121-12M and latch cicuit 130.Delay cell 121-12M mutually goes here and there Connection coupling, delay cell 121-12M is according to an output clock signal CKO to generate multiple clock signal CK1-CKM respectively.Electricity Lotus side Pu unit 111-11N is serially connected coupling.
It is described in detail, first order charge pump unit 111 receives input voltage VIN, and carries out for input voltage VIN The pumped operation of voltage.First order charge pump unit 111 transmits the charge pump unit 112 of the pumped result of its voltage to next stage To carry out another pumped operation of voltage.In this embodiment, by the charge carried out by charge pump unit 111-11N Pumped operation can produce the output voltage VO UT with the voltage level higher than input voltage VIN.Furthermore delay cell 121- 12M generates multiple clock signal CK1-CKM by delay output signal CKO sequentially respectively.For example, the first stage prolongs Slow unit 121 receives output clock signal CKO, and delayed output clock signal CKO is to generate clock signal CK1.Then, postpone Unit 122 receives clock signal CK1 from delay cell 121, and generates clock signal CK2 by delay clock signals CK1.
Latch cicuit 130 couples afterbody delay cell 12M, and latch cicuit 130 receives afterbody clock signal CKM is to generate output clock signal CKO.Latch cicuit 130, which more receives, latches enable signal ENPUMP, 130 basis of latch cicuit Enable signal ENPUMP is latched to decide whether to latch afterbody clock signal CKM to generate output clock signal CKO.In detail Illustrate, latches enable signal ENPUMP and be used to refer to whether the pumped operation of voltage is completed.If the pumped operation of voltage side is still It does not complete, latch cicuit 130 can postpone final stage clock signal CKM and by delay afterbody clock signal with basis Energy signal ENPUMP is latching to generate output clock signal CKO.On the other hand, it if the pumped operation of voltage is completed, latches Circuit 130 can latch afterbody clock signal CKM according to enable signal ENPUMP is latched to generate output clock signal CKO, and the voltage level of output clock signal CKO is kept, in this way, output clock signal CKO will not generate multiple voltage transitions Phenomenon.
That is, the voltage level of output clock signal CKO can be used to stop as latch enable signal ENPUMP The time point of the pumped operation of voltage is lockable.Charge pump unit 11N can be passed to by not having unnecessary pulse signal, output Unwanted ripple can also be reduced on voltage VOUT.
On the other hand, before the time point that the pumped operation of voltage is stopped, the pulse signal on clock signal CKO is exported It can be passed to delay cell 121, and after the pumped operation of voltage is stopped, delay cell 121-12M can also be of short duration Time cycle in normally operate.For example, charge pump unit 111-11M can be in of short duration time cycle normal operation.This Outside, if the pumped operation needs of voltage are restarted, a new pulse letter can be generated on output clock signal CKO Number, charge pump unit 11N then can generate immediately output voltage by the pumped operation of voltage according to output clock signal CKO The voltage drop of VOUT, output voltage VO UT can be reduced and the ripple of output voltage VO UT can be corresponded to and is lowered.
It in this embodiment, can be identical or different by the delay that delay cell 121-12M is provided respectively.Each delay Unit 121-12M can carry out construction by any other circuit structures, for example, one or more logic gates.
Each charge pump unit 111-11N is according to for the pulse signal and output clock on clock signal CK1-CKM Signal CKN to carry out the pumped operation of voltage respectively.
Referring to FIG. 2, Fig. 2 is painted the schematic diagram of the electric charge pump circuit of another embodiment of the present invention.Charge pump electricity Road 200 includes charge pump unit 211-214, delay cell 221-223 and latch cicuit 230.Delay cell 221-223 phase Coupled in series, and the multiple clock signal CK1-CK3 of generation according to output clock signal CKO respectively.Charge pump unit 211- 214 be serially connected coupling, receives clock signal CK1-CK3 and output clock signal CKO respectively, and according to being respectively received Clock signal carries out the pumped operation of voltage.
In the present embodiment, delay cell 221-223 respectively includes phase inverter IN1-IN3, and clock signal CK1 and clock Signal CK2 is complementary, and clock signal CK2 is complementary with clock signal CK3.Latch cicuit 230 includes phase inverter IN4-IN5 and latch Device LAT1.Phase inverter IN4-IN5 is used as a delay circuit, and the phase inverter IN4-IN5 delay received clock signal CK3 of institute comes Generate delay clock signals DCK3.Delay clock signals DCK3 is received by latch LAT1, and latch LAT1 more receives lock It deposits enable signal ENPUMA and generates output clock signal CKO.
It is noted that latch LAT1 can latch door for a logic, and as latch enable signal ENPUMP When for the first logic level, latch LAT1 can with transmission delay clock signal DCK3 using as output clock signal CKO, and When latching enable signal ENPUMP is for the second logic level, latch LAT1 can latch the electricity of delay clock signals DCK3 Voltage level exports clock signal CKO to generate.
Afterbody charge pump unit 214 is separately coupled to resistance R1 and capacitor C1.Resistance R1 is coupled in charge pump Between the output end and reference ground terminal GND of unit 214.Capacitor C1 is coupled in output end and the reference of charge pump unit 214 Between ground terminal GND.Resistance R1 and capacitor C1 can form the circuit for eliminating the ripple for output voltage VO UT.
The schematic diagram of the electric charge pump circuit of yet another embodiment of the invention is painted with reference to Fig. 3, Fig. 3.Electric charge pump circuit 300 Including charge pump unit 311-314, delay cell 321-323, latch cicuit 330 and phase inverter IN9.In this embodiment In, the circuit structure of all charge pump unit 311-314 can be all identical, and clock signal CK1 and clock signal CK2 are mutual It mends, clock signal CK2 is complementary with clock signal CK3, and clock signal CK3 is then complementary with output clock signal CKO.
The schematic diagram of the electric charge pump circuit of yet another embodiment of the invention is painted with reference to Fig. 4, Fig. 4.Electric charge pump circuit 400 Including charge pump unit 411-414, delay cell 421-423 and latch cicuit 430.In the present embodiment, single in delay The quantity of phase inverter in first 421-423 can not be identical.For example, delay cell 421 only includes a phase inverter IN1.Delay Unit 422 includes two phase inverters INA and INB, and delay cell 423 then includes two phase inverters INC and IND.It herein can be clear Chu Faxian, clock signal CK1 and clock signal CK2 be not mutually complementary, and clock signal CK2 and clock signal CK3 be not mutually complementary, and Clock signal CK3 and output clock signal CKO be not mutually complementary.
The schematic diagram for the adjustment circuit that the embodiment of the present invention illustrates is painted with reference to Fig. 5, Fig. 5.Adjustment circuit in Fig. 5 receives Output voltage VO UT, output voltage VO UT therein can be generated by electric charge pump circuit 100,200,300 or 400, and Adjustment circuit, which is then used to generate, latches enable signal ENPUMP.Specifically bright, the adjustment circuit of Fig. 5 includes divider 510 And operational amplifier OP1.Divider 510 receives output voltage VO UT and is divided for output voltage to generate feedback electricity Press Vfb.Voltage divider 510 includes two resistance R1 and R2.Resistance R1 and R2 is serially connected coupling, and one end of resistance R1 receives One end of the other end coupling resistance R2 of output voltage VO UT, resistance R1, and the other end of resistance R2 is then coupled to reference to ground connection Hold GND.
On the other hand, operational amplifier OP1 has an a positive input terminal I2 and negative input end I1.Positive input terminal I2 A reference voltage Vref is received, negative input end I1 then receives feedback voltage Vfb.Operational amplifier OP1 comparison reference voltage Vref and feedback voltage Vfb latch enable signal ENPUMP to generate.In embodiment, if reference voltage Vref is greater than instead Feedthrough voltage Vfb, then the pumped operation of voltage cannot be stopped and operational amplifier OP1 generate latch enable signal ENPUMP and Logic level " 1 ".Opposite, if reference voltage Vref is less than feedback voltage Vfb, the Pu operation of voltage side can be stopped, and Operational amplifier OP1 then generates the latch enable signal ENPUMP of logic level " 0 ".
The schematic diagram of the memory device of the embodiment of the present invention is painted with reference to Fig. 6, Fig. 6.Memory device 600 includes multiple Memory crystal cell, and memory crystal cell is aligned to memory crystal cell array 610.Memory device 600 further includes charge pump Circuit 620.Memory crystal cell in memory crystal cell array 610 can be nonvolatile memory structure cell.Electric charge pump circuit 620 can implement by electric charge pump circuit 100,200,300 and 400.Electric charge pump circuit 620 is used to provide to erase One or the two in voltage ERS and program voltage PGM.
With reference to Fig. 7, in accordance with an embodiment of the present disclosure, Fig. 7 is painted the flow chart of the pumped method of voltage of the embodiment of the present invention. In step S710, multiple clock signals are generated by delayed output clock signal sequentially.Then, in step S720, Input voltage is received, and for the Pu operation of input voltage operation voltage side, and according to clock signal and output clock signal Corresponding generation output voltage.It further explains, in step S730, when the voltage level of output voltage reaches reference voltage Voltage level when, the voltage level of the afterbody clock signal in clock signal is latched and uses generation output clock letter Number.In other words, it when the voltage level of output voltage reaches the voltage level of reference voltage, then carries out latching output clock signal Voltage level movement, in this way, there is no pulse signals to be passed to afterbody charge pump unit.The line of output voltage Wave can be reduced, and peak point current caused by electric charge pump circuit can be also reduced.
About the detailed operation of step S710-730, it has been described later in detail in the above-described embodiment, herein not Repeat explanation.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, and those skilled in the art exist It does not depart from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection scope of the present invention is appended by the view Subject to claims confining spectrum.

Claims (14)

1. a kind of electric charge pump circuit, includes:
Multiple delay cells, the multiple delay cell are serially connected coupling, wherein the multiple delay cell is according to an output Clock signal respectively generates multiple clock signals；
Latch cicuit couples the delay cell, receives the afterbody clock signal of the multiple clock signal and latches cause Energy signal, wherein the afterbody clock signal is generated by afterbody delay cell, and the latch cicuit is according to the latch enable Whether signal deciding latches the afterbody clock signal to generate the output clock signal；And
Multiple charge pump units, the multiple charge pump unit are serially connected coupling, wherein first order charge pump unit An input voltage is received, and the multiple charge pump unit is believed according to the multiple clock signal and the output clock respectively Number carrying out the pumped operation of voltage to the input voltage generates output voltage.
2. electric charge pump circuit as described in claim 1, wherein one of the multiple delay cell includes:
An at least phase inverter, the output end and output end of the delay cell with input terminal coupling previous stage couple next stage Delay cell input terminal.
3. electric charge pump circuit as described in claim 1, wherein the latch cicuit includes:
Delay circuit receives the afterbody clock signal and generates delay clock signals；And
One latch receives the delay clock signals and the latch enable signal, and according to the latch enable signal deciding Whether the voltage level of the delay clock signals is kept.
4. electric charge pump circuit as described in claim 1, further includes:
Adjustment circuit couples the side Pu unit and the latch cicuit, receive the output voltage and compare the output voltage and Reference voltage generates the latch enable signal.
5. electric charge pump circuit as claimed in claim 4, wherein the adjustment circuit includes:
Divider receives the output voltage and divides the output voltage to generate feedback voltage；And
Operational amplifier has negative input end to receive the feedback voltage, and positive input terminal is to receive the reference voltage and defeated Outlet is to generate the latch enable signal.
6. a kind of memory device, comprising:
Electric charge pump circuit provides program voltage and deposits at least one in voltage of erasing to the multiple of the memory device Reservoir structure cell, wherein the electric charge pump circuit include:
Multiple delay cells, the multiple delay cell are serially connected coupling, wherein when the multiple delay cell is according to output Clock signal generates multiple clock signals respectively；
Latch cicuit couples the delay cell, receives the afterbody clock signal of the multiple clock signal and latches cause Energy signal, wherein the afterbody clock signal is generated by afterbody delay cell, and the latch cicuit is according to the latch enable Signal decides whether to latch the afterbody clock signal to generate the output clock signal；And
Multiple charge pump units, the multiple charge pump unit are serially connected coupling, wherein a first order charge pump list The reception input voltage of member, and the multiple charge pump unit is respectively according to the multiple clock signal and the output clock Signal is to carry out the pumped operation of voltage for the input voltage to generate output voltage；
Wherein the output voltage is used to as the program voltage and at least one in the voltage of erasing.
7. memory device as claimed in claim 6, wherein one of the delay cell includes:
An at least phase inverter, with input terminal be coupled to previous stage delay cell output end and output end its be coupled to down The input terminal of level-one delay cell.
8. memory device as claimed in claim 6, wherein the latch cicuit includes:
Delay circuit receives the afterbody clock signal and generates a delay clock signals；And
Latch receives the delay clock signals and the latch enable signal, and is according to the latch enable signal deciding The no voltage level for keeping the delay clock signals.
9. memory device as claimed in claim 6, wherein the electric charge pump circuit also includes:
Adjustment circuit couples the side Pu unit and the latch cicuit, receive the output voltage and compare the output voltage and Reference voltage generates the latch enable signal.
10. memory device as claimed in claim 9, wherein the adjustment circuit includes:
Divider receives the output voltage and divides the output voltage to generate a feedback voltage；And operational amplifier, tool There is negative input end to receive the feedback voltage, positive input terminal generates latch cause to receive the reference voltage and output end It can signal.
11. a kind of pumped method of voltage, comprising:
By sequentially delayed output clock signal to generate multiple clock signals；
Input voltage is received, and according to the multiple clock signal and the output clock signal for input voltage operation electricity Press pump swashs operation to generate output voltage；And
When the voltage level of the voltage level arrival reference voltage of the output voltage, last of the multiple clock signal is latched The voltage level of grade clock signal is to generate the output clock signal, and wherein the afterbody clock signal is postponed by afterbody Unit generates.
12. the pumped method of voltage as claimed in claim 11, further includes:
When the voltage level of the output voltage be less than the reference voltage voltage level when, postpone the afterbody clock signal with Generate the output clock signal.
13. the pumped method of voltage as claimed in claim 11, wherein when the voltage level of the output voltage reaches reference electricity When the voltage level of pressure, the voltage level of the afterbody clock signal of the multiple clock signal is latched to generate the output The step of clock signal includes:
The voltage level of the voltage level and the reference voltage that compare the output voltage latches enable signal to generate；And
According to the voltage level of the afterbody clock signal of the multiple clock signal of latch enable signal latch to produce The raw output clock signal.
14. the pumped method of voltage as claimed in claim 13, wherein comparing the voltage level and reference electricity of the output voltage The voltage level of pressure includes: the step of the latch enable signal to generate
The output voltage is divided to generate feedback voltage；And
Compare the feedback voltage and the reference voltage to generate the latch enable signal.
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