CN105761663B - Shift register cell, gate driving circuit and display device - Google Patents
Shift register cell, gate driving circuit and display device Download PDFInfo
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- CN105761663B CN105761663B CN201610341470.3A CN201610341470A CN105761663B CN 105761663 B CN105761663 B CN 105761663B CN 201610341470 A CN201610341470 A CN 201610341470A CN 105761663 B CN105761663 B CN 105761663B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of shift register cell of disclosure offer, gate driving circuit and display device.The shift register cell includes similar the first shift register cell and the second shift register cell of structure, and first shift register cell and the second shift register cell mutually control, therefore can preferably realize the first sequential scan and the second sequential scan.In addition, in the first shift register cell, drop-down for first node and the first output end is double drop-downs, in the second shift register cell, drop-down for fourth node and second output terminal is double drop-downs, therefore the waveform of the gated sweep signal of shift register cell output is more stablized.And then the shift register cell provided by the example embodiment of the disclosure can further promote the display effect of display device.
Description
Technical field
This disclosure relates to display technology field, and in particular to a kind of shift register cell, using the shift register list
The display device of the gate driving circuit and application of the member gate driving circuit.
Background technology
With the development of optical technology and semiconductor technology, liquid crystal display device (Liquid Crystal Display,
) and the FPD dress such as organic LED display device (Organic Light Emitting Diode, OLED) LCD
Set due to, cost more frivolous with body and energy consumption is lower, reaction speed faster, excitation purity and brightness is more excellent and contrast more
The features such as high, has been widely used in each electronic product.
In above-mentioned display device, is mainly realized and shown by picture element matrix.Typically, each row pixel is both coupled to correspondence
Scanning grid line.In the display device course of work, by gate driving circuit by signals such as the clock signals of input by moving
The modules such as bit register unit are converted into the gated sweep signal of control pixel on/off, then sequentially by gated sweep signal
It is applied to the scanning grid line of each row pixel of display device, each row pixel is gated.
However, there are still the places that has much room for improvement for shift register cell in the prior art and gate driving circuit.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Invention content
The disclosure is designed to provide a kind of shift register cell, the gate driving using the shift register cell
The display device of circuit and the application gate driving circuit, for overcoming the limit due to the relevant technologies at least to a certain extent
One or more problems caused by system and defect.
Other characteristics and advantages of the disclosure will be apparent from by the following detailed description, or partially by the disclosure
Practice and acquistion.
According to the disclosure in a first aspect, provide a kind of shift register cell, including：
First input module provides one first sequential scan signal to first node for responding one first input signal,
And one second sequential scan signal is provided to the first node by one first reset signal of response；
One first clock signal is provided to the first output by the first output module, the signal for responding the first node
End；
First pull-down module, for respond the signal of a second node by a pulldown signal be provided to the first node with
And first output end；
The pulldown signal is provided to second section by the second pull-down module, the signal for responding the first node
Point and a third node；
The pulldown signal is provided to the second node by third pull-down module, the signal for responding a fourth node
And third node；
The pulldown signal is provided to the first node by the 4th pull-down module, the signal for responding one the 5th node
And first output end；
One first charging signals are provided to described second by the first charging module, the signal for responding the third node
Node；
The first sequential scan signal is provided the described 4th by the second input module for responding one second input signal
The second sequential scan signal is provided to the fourth node by node, and one second reset signal of response；
One second clock signal is provided to the second output by the second output module, the signal for responding the fourth node
End；
The pulldown signal is provided to described Section four by the 5th pull-down module, the signal for responding the 5th node
Point and the second output terminal；
The pulldown signal is provided to described Section five by the 6th pull-down module, the signal for responding the fourth node
Point and one the 6th node；
The pulldown signal is provided to described Section five by the 7th pull-down module, the signal for responding the first node
Point and the 6th node；
The pulldown signal is provided to described Section four by the 8th pull-down module, the signal for responding the second node
Point and the second output terminal；
One second charging signals are provided to the described 5th by the second charging module, the signal for responding the 6th node
Node, second charging signals are complementary with first charging signals.
In a kind of exemplary embodiment of the disclosure, the shift register cell further includes：
The pulldown signal is provided to first output by the 9th pull-down module for responding a third clock signal
End；The third clock signal and first clock signal complement；
The pulldown signal is provided to second output by the tenth pull-down module for responding one the 4th clock signal
End；4th clock signal is complementary with the second clock signal.
In a kind of exemplary embodiment of the disclosure, wherein：
First input module includes：
The control terminal of the first transistor, the first transistor receives first input signal, the first transistor
First end receive the first sequential scan signal, the second end of the first transistor is connect with the first node；
The control terminal of second transistor, the second transistor receives first reset signal, the second transistor
First end receive the second sequential scan signal, the second end of the second transistor is connect with the first node；
Second input module includes：
15th transistor, control terminal reception second input signal of the 15th transistor, the described 15th
The first end of transistor receives the first sequential scan signal, second end and the fourth node of the 15th transistor
Connection；
16th transistor, control terminal reception second reset signal of the 16th transistor, the described 16th
The first end of transistor receives the second sequential scan signal, second end and the fourth node of the 16th transistor
Connection.
In a kind of exemplary embodiment of the disclosure, wherein：
First output module includes：
Third transistor, the control terminal of the third transistor are connect with the first node, the third transistor
First end receives first clock signal, and the second end of the third transistor is connect with first output end；
First capacitance is connected between the first node and first output end；
Second output module includes：
The control terminal of 17th transistor, the 17th transistor is connect with the fourth node, and the described 17th is brilliant
The first end of body pipe receives the second clock signal, and second end and the second output terminal of the 17th transistor connect
It connects；
Second capacitance is connected between the fourth node and the second output terminal.
In a kind of exemplary embodiment of the disclosure, wherein：
First pull-down module includes：
The control terminal of 4th transistor, the 4th transistor is connect with the second node, the 4th transistor
First end receives the pulldown signal, and the second end of the 4th transistor is connect with the first node；
The control terminal of 5th transistor, the 5th transistor is connect with the second node, the 5th transistor
First end receives the pulldown signal, and the second end of the 5th transistor is connect with first output end；
5th pull-down module includes：
The control terminal of 18th transistor, the 18th transistor is connect with the 5th node, and the described 18th is brilliant
The first end of body pipe receives the pulldown signal, and the second end of the 18th transistor is connect with the fourth node；
The control terminal of 19th transistor, the 19th transistor is connect with the 5th node, and the described 19th is brilliant
The first end of body pipe receives the pulldown signal, and the second end of the 19th transistor is connect with the second output terminal.
In a kind of exemplary embodiment of the disclosure, wherein：
Second pull-down module includes：
The control terminal of 6th transistor, the 6th transistor is connect with the first node, the 6th transistor
First end receives the pulldown signal, and the second end of the 6th transistor is connect with the second node；
The control terminal of 7th transistor, the 7th transistor is connect with the first node, the 7th transistor
First end receives the pulldown signal, and the second end of the 7th transistor is connect with the third node；
6th pull-down module includes：
The control terminal of 20th transistor, the 20th transistor is connect with the fourth node, and the described 20th is brilliant
The first end of body pipe receives the pulldown signal, and the second end of the 20th transistor is connect with the 5th node；
The control terminal of 21st transistor, the 21st transistor is connect with the fourth node, and described second
The first end of 11 transistors receives the pulldown signal, and second end and the 6th node of the 21st transistor connect
It connects.
In a kind of exemplary embodiment of the disclosure, wherein：
The third pull-down module includes：
The control terminal of 8th transistor, the 8th transistor is connect with the fourth node, the 8th transistor
First end receives the pulldown signal, and the second end of the 8th transistor is connect with the second node；
The control terminal of 9th transistor, the 9th transistor is connect with the fourth node, the 9th transistor
First end receives the pulldown signal, and the second end of the 9th transistor is connect with the third node；
7th pull-down module includes：
The control terminal of 20th two-transistor, the 20th two-transistor is connect with the first node, and described second
The first end of ten two-transistors receives the pulldown signal, and second end and the 5th node of the 20th two-transistor connect
It connects；
The control terminal of 23rd transistor, the 23rd transistor is connect with the first node, and described second
The first end of 13 transistors receives the pulldown signal, and second end and the 6th node of the 23rd transistor connect
It connects.
In a kind of exemplary embodiment of the disclosure, wherein：
4th pull-down module includes：
The control terminal of tenth transistor, the tenth transistor is connect with the 5th node, the tenth transistor
First end receives the pulldown signal, and the second end of the tenth transistor is connect with the first node；
The control terminal of 11st transistor, the 11st transistor is connect with the 5th node, and the described 11st is brilliant
The first end of body pipe receives the pulldown signal, and the second end of the 11st transistor is connect with first output end；
8th pull-down module includes：
The control terminal of 24th transistor, the 24th transistor is connect with the second node, and described second
The first end of 14 transistors receives the pulldown signal, and second end and the fourth node of the 24th transistor connect
It connects；
The control terminal of 25th transistor, the 25th transistor is connect with the second node, and described second
The first end of 15 transistors receives the pulldown signal, second end and the second output terminal of the 25th transistor
Connection.
In a kind of exemplary embodiment of the disclosure, wherein：
First charging module includes：
The control terminal of tenth two-transistor, the tenth two-transistor is connect with the third node, and the described 12nd is brilliant
The first end of body pipe receives first charging signals, and the second end of the tenth two-transistor is connect with the second node；
13rd transistor, the control terminal and first end of the 13rd transistor receive first charging signals,
The second end of 13rd transistor is connect with the third node；
Second charging module includes：
The control terminal of 26th transistor, the 26th transistor is connect with the 6th node, and described second
The first ends of 16 transistors receives second charging signals, the second end of the 26th transistor with described Section five
Point connection；
27th transistor, the control terminal and first end of the 27th transistor receive the second charging letter
Number, the second end of the 27th transistor is connect with the 6th node.
In a kind of exemplary embodiment of the disclosure, wherein：
9th pull-down module includes：
14th transistor, the control terminal reception third clock signal of the 14th transistor, the described 14th
The first end of transistor receives the pulldown signal, and the second end of the 14th transistor is connect with first output end；
Tenth pull-down module includes：
28th transistor, the control terminal of the 28th transistor receive the 4th clock signal, and described the
The first end of 28 transistors receives the pulldown signal, and the second end of the 28th transistor is exported with described second
End connection.
In a kind of exemplary embodiment of the disclosure, the first sequential scan signal controls the shift register list
Member controls the shift register cell and is swept along the second sequence along the first sequential scan, the second sequential scan signal
It retouches, first sequence is opposite with second sequence direction.
In a kind of exemplary embodiment of the disclosure, first clock signal and the second clock signal section weight
It is folded；The third clock signal is Chong Die with the 4th clock signal portion.
In a kind of exemplary embodiment of the disclosure, the transistor is N-type channel transistor or is P-type channel
Transistor.
In a kind of exemplary embodiment of the disclosure, the transistor is amorphous silicon transistor, low-temperature polysilicon silicon crystal
Pipe or oxide semi conductor transistor.
According to the second aspect of the disclosure, a kind of gate driving circuit, including any one of the above shift register are provided
Unit.
In a kind of exemplary embodiment of the disclosure, the gate driving circuit includes that cascade N number of displacement is posted
Storage unit；Wherein：
First input signal described in m+1 grades of shift register cells is the described in m grades of shift register cells
The signal of one output end output；
Second input signal described in m+1 grades of shift register cells is the described in m grades of shift register cells
The signal of two output ends output；
First reset signal described in m grades of shift register cells is the described in m+1 grades of shift register cells
The signal of one output end output；
Second reset signal described in m grades of shift register cells is the described in m+1 grades of shift register cells
The signal of two output ends output；Wherein, 0<m<N.
In a kind of exemplary embodiment of the disclosure, the gate driving circuit includes that cascade N number of displacement is posted
Storage unit；Wherein：
First input signal described in m+1 grades of shift register cells is described in m-1 grades of shift register cells
The signal of second output terminal output；
Second input signal described in m+1 grades of shift register cells is the described in m grades of shift register cells
The signal of one output end output；
Second reset signal described in m-1 grades of shift register cells is described in m+1 grades of shift register cells
The signal of first output end output；
First reset signal described in m grades of shift register cells is the described in m+1 grades of shift register cells
The signal of two output ends output；Wherein, 1<m<N.
According to the third aspect of the disclosure, a kind of display device, including any one of the above gate driving circuit are provided.
In the shift register cell that the example embodiment of the disclosure is provided, including structure it is similar first displacement post
Storage unit and the second shift register cell, and the first shift register cell and the second shift register cell phase cross complaint
System, therefore can preferably realize the first sequential scan and the second sequential scan.In addition, in the first shift register cell,
Drop-down for first node and the first output end is double drop-downs, in the second shift register cell, for fourth node
Drop-down with second output terminal is double drop-downs, therefore the waveform of the gated sweep signal of shift register cell output is more steady
It is fixed.And then the shift register cell provided by the example embodiment of the disclosure can further promote display device
Display effect.
Description of the drawings
Its exemplary embodiment is described in detail by referring to accompanying drawing, the above and other feature and advantage of the disclosure will become
It is more obvious.
Fig. 1 is a kind of structural schematic diagram of shift register cell in example embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another shift register cell in example embodiment of the present invention；
Fig. 3 A are the driver' s timing of shift register cell and signal waveform schematic diagram in Fig. 2；
Fig. 3 B are the waveform diagrams of the first charging signals and the second charging signals in shift register cell in Fig. 2；
Fig. 4 is a kind of realization structural schematic diagram of gate driving circuit in example embodiment of the present invention；
Fig. 5 is that the another of gate driving circuit in example embodiment of the present invention realizes structural schematic diagram.
Specific implementation mode
Exemplary embodiment is described more fully with reference to the drawings.However, exemplary embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will
Fully and completely, and by the design of exemplary embodiment comprehensively it is communicated to those skilled in the art.In the figure in order to clear
It is clear, exaggerate, deform or simplify geomery.Identical reference numeral indicates same or similar structure in figure, thus will
Omit their detailed description.
In addition, described feature, structure or step can be incorporated in one or more implementations in any suitable manner
In example.In the following description, many details are provided to fully understand embodiment of the disclosure to provide.However,
It will be appreciated by persons skilled in the art that can be with technical solution of the disclosure without one in the specific detail or more
It is more, or other methods, step, structure may be used etc..
A kind of shift register cell is provided firstly in this example embodiment.The shift register cell includes first
Shift register cell and the second shift register cell, and the first shift register cell and the second shift register cell
With similar structure.As shown in fig. 1, the first shift register cell includes the first input module M1, the first output module
M2, the first pull-down module M3, the second pull-down module M4, third pull-down module M5, the charging moulds of the 4th pull-down module M6 and first
Block M7；Second shift register cell includes the second input module M8, the second output module M9, the 5th pull-down module M10, the 6th
Pull-down module M11, the 7th pull-down module M12, the 8th pull-down module M13 and the second charging module M14.Wherein：
First input module M1 can be used for responding one first input signal SET1 and being connected, to sweep one first sequence
It retouches signal FW and first node P1 is provided, and respond one first reset signal RESET1 and be connected, to sweep one second sequence
It retouches signal BW and is provided to the first node P1.First output module M2 can be used for responding the signal of the first node P1 and
Conducting, to which one first clock signal CK1 is provided to the first output end GOUT1.First pull-down module M3 can be used for responding
The signal of one second node P2 and be connected, to which a pulldown signal VGL is provided to the first node P1 and described first
Output end GOUT1.Second pull-down module M4 can be used for responding the signal of the first node P1 and be connected, under will be described
Signal VGL is drawn to be provided to a second node P2 and third node P3.Third pull-down module M5 can be used for responding one the
The signal of four node P4 and be connected, to which the pulldown signal VGL is provided to the second node P2 and third node P3.
4th pull-down module M6 can be used for responding the signal of one the 5th node P5 and be connected, to provide the pulldown signal VGL
To the first node P1 and the first output end GOUT1.First charging module M7 can be used for responding the third section
The signal of point P3 and be connected, to which one first charging signals V1 is provided to the second node P2.
Second input module M8 can be used for responding one second input signal SET2 and being connected, thus by first sequence
Scanning signal FW provides the fourth node P4, and one second reset signal RESET2 of response and be connected, to by described the
Two sequential scan signal BW are provided to the fourth node P4.Second output module M9 can be used for responding the fourth node P4
Signal and be connected, to which a second clock signal CK2 is provided to second output terminal GOUT2.5th pull-down module M10 can be with
It is connected for responding the signal of the 5th node P5, to which the pulldown signal VGL is provided to the fourth node P4
And the second output terminal GOUT2.6th pull-down module M11 can be used for responding the signal of the fourth node P4 and lead
It is logical, to which the pulldown signal VGL is provided to the 5th node P5 and one the 6th node P6.7th pull-down module M12
It can be used for responding the signal of the first node P1 and be connected, to which the pulldown signal VGL is provided to described Section five
Point P5 and the 6th node P6.8th pull-down module M13 can be used for responding the signal of the second node P2 and be connected, to
The pulldown signal VGL is provided to the fourth node P4 and the second output terminal GOUT2.Second charging module M14
It can be used for responding the signal of the 6th node P6 and be connected, to which one second charging signals V2 is provided to described Section five
Point P5；In this example embodiment, the second charging signals V2 and the first charging signals V1 is complementary, i.e., the second charging letter
When number V2 is located at high level, the first charging signals V1 is located at low level；When second charging signals V2 is located at low level, the first charging
Signal V1 is located at high level.
In the shift register cell that this example embodiment is provided, including the first shift register that structure is similar
Unit and the second shift register cell, and the first shift register cell and the second shift register cell mutually control,
Therefore the first sequential scan and the second sequential scan can preferably be realized.In addition, in the first shift register cell, for
The drop-down of first node P1 and the first output end GOUT1 are double drop-downs, in the second shift register cell, for Section four
The drop-down of point P4 and second output terminal GOUT2 are double drop-down, therefore the gated sweep signal of shift register cell output
Waveform is more stablized.And then display device can further be promoted by the shift register cell in this example embodiment
Display effect.
Shown in continuing to refer to figure 1, in order to further enhance the stability of the waveform of the gated sweep signal of output, originally show
In example embodiment, first shift register cell can also include the 9th pull-down module M15, second shift LD
Device unit may include the tenth pull-down module M16.Wherein：9th pull-down module M15 can be used for responding a third clock signal
CK3 and be connected, to which the pulldown signal VGL is provided to the first output end GOUT1；The third clock signal CK3
It is complementary with the first clock signal CK1, for example, the third clock signal CK3 is the reverse phase of the first clock signal CK1
Signal etc..Tenth pull-down module M16 can be used for responding one the 4th clock signal CK4 and being connected, thus by the pulldown signal
VGL is provided to the second output terminal GOUT2；The 4th clock signal CK4 and second clock signal CK2 is complementary, example
Such as, the 4th clock signal CK4 is the inversion signal etc. of the second clock signal CK2.
In the following, to the shift register list in this example embodiment by taking above-mentioned each module is mainly made of transistor as an example
Member is further detailed.In this example embodiment, each transistor includes first end, second end and control
End, for example, first end, second end and control terminal are respectively source electrode, drain electrode and the grid of transistor；Alternatively, first end,
Two ends and control terminal are respectively drain electrode, source electrode and the grid of transistor.The transistor can be N-type channel transistor
Or be P-type channel transistor, it will be by taking the transistor can be N-type channel transistor as an example in the present exemplary embodiment
It illustrates.The transistor can be amorphous silicon transistor, low-temperature polycrystalline silicon transistor, oxide semi conductor transistor or
Other kinds of transistor does not do this particular determination in the present exemplary embodiment.
Incorporated by reference to Fig. 1 and with reference to shown in figure 2, in this example embodiment, the first input module M1 may include
The first transistor T1 and second transistor T2.Wherein：The control terminal of the first transistor T1 receives the first input letter
The first end of number SET1, the first transistor T1 receive the first sequential scan signal FW, the first transistor T1's
Second end is connect with the first node P1.The control terminal of second transistor T2, the second transistor T2 receive described first
The first end of reset signal RESET1, the second transistor T2 receive the second sequential scan signal BW, and described second is brilliant
The second end of body pipe T2 is connect with the first node P1.
Similar with the first input module M1, the second input module M8 may include the 15th transistor T15 and
16 transistor T16.Wherein：The control terminal of the 15th transistor T15 receives the second input signal SET2, and described the
The first end of 15 transistor T15 receives the first sequential scan signal FW, the second end of the 15th transistor T15 with
The fourth node P4 connections.The control terminal of the 16th transistor T16 receives the second reset signal RESET2, described
The first end of 16th transistor T16 receives the second sequential scan signal BW, the second end of the 16th transistor T16
It is connect with the fourth node P4.
Shown in Fig. 2, in the present exemplary embodiment, the first output module M2 may include third crystal
Pipe T3 and the first capacitance C1.Wherein：The control terminal of the third transistor T3 is connect with the first node P1, the third
The first end of transistor T3 receives the first clock signal CK1, the second end of the third transistor T3 and described first defeated
Outlet GOUT1 connections.The first capacitance C1 is connected between the first node P1 and the first output end GOUT1.
Similar with the first output module M2, the second output module M9 may include the 17th transistor T17 and
Two capacitance C2.Wherein：The control terminal of the 17th transistor T17 is connect with the fourth node P4, the 17th crystal
The first end of pipe T17 receives the second clock signal CK2, the second end of the 17th transistor T17 and described second defeated
Outlet GOUT2 connections.The second capacitance C2 is connected between the fourth node P4 and the second output terminal GOUT2.
Shown in Fig. 2, in the present exemplary embodiment, the first pull-down module M3 may include the 4th crystal
Pipe T4 and the 5th transistor T5.Wherein：The control terminal of the 4th transistor T4 is connect with the second node P2, and described
The first end of four transistor T4 receives the pulldown signal VGL, second end and the first node of the 4th transistor T4
P1 connections.The control terminal of the 5th transistor T5 is connect with the second node P2, the first end of the 5th transistor T5
The pulldown signal VGL is received, the second end of the 5th transistor T5 is connect with the first output end GOUT1.
Similar with the first pull-down module M3, the 5th pull-down module M10 may include the 18th transistor T18 and
19 transistor T19.Wherein：The control terminal of the 18th transistor T18 is connect with the 5th node P5, and the described 18th
The first end of transistor T18 receives the pulldown signal VGL, the second end of the 18th transistor T18 with described Section four
Point P4 connections.The control terminal of the 19th transistor T19 is connect with the 5th node P5, the 19th transistor T19
First end receive the pulldown signal VGL, second end and the second output terminal GOUT2 of the 19th transistor T19
Connection.
Continuing with combining Fig. 1 and with reference to shown in figure 2, in the present exemplary embodiment, the second pull-down module M4 can be with
Including the 6th transistor T6 and the 7th transistor T7.Wherein：The control terminal of the 6th transistor T6 and the first node
P1 connections, the first end of the 6th transistor T6 receive the pulldown signal VGL, the second end of the 6th transistor T6 with
The second node P2 connections.The control terminal of the 7th transistor T7 is connect with the first node P1, the 7th crystal
The first end of pipe T7 receives the pulldown signal VGL, and the second end of the 7th transistor T7 is connect with the third node P3.
Similar with the second pull-down module M4, the 6th pull-down module M11 may include the 20th transistor T20 and
21 transistor T21.Wherein：The control terminal of the 20th transistor T20 is connect with the fourth node P4, and described second
The first end of ten transistor T20 receives the pulldown signal VGL, the second end and the described 5th of the 20th transistor T20
Node P5 connections.The control terminal of the 21st transistor T21 is connect with the fourth node P4, the 21st crystal
The first end of pipe T21 receives the pulldown signal VGL, second end and the 6th node of the 21st transistor T21
P6 connections.
Continuing with combining Fig. 1 and with reference to shown in figure 2, in the present exemplary embodiment, the third pull-down module M5 can be with
Including the 8th transistor T8 and the 9th transistor T9.Wherein：The control terminal of the 8th transistor T8 and the fourth node
P4 connections, the first end of the 8th transistor T8 receive the pulldown signal VGL, the second end of the 8th transistor T8 with
The second node P2 connections.The control terminal of the 9th transistor T9 is connect with the fourth node P4, the 9th crystal
The first end of pipe T9 receives the pulldown signal VGL, and the second end of the 9th transistor T9 is connect with the third node P3.
It is similar with third pull-down module M5, the 7th pull-down module M12 may include the 20th two-transistor T22 and
23rd transistor T23.Wherein：The control terminal of the 20th two-transistor T22 is connect with the first node P1, described
The first end of 20th two-transistor T22 receives the pulldown signal VGL, the second end of the 20th two-transistor T22 with
The 5th node P5 connections.The control terminal of the 23rd transistor T23 is connect with the first node P1, and described second
The first end of 13 transistor T23 receives the pulldown signal VGL, the second end of the 23rd transistor T23 with it is described
6th node P6 connections.
Continuing with combining Fig. 1 and with reference to shown in figure 2, in the present exemplary embodiment, the 4th pull-down module M6 can be with
Including the tenth transistor T10 and the 11st transistor T11.Wherein：The control terminal and the described 5th of the tenth transistor T10
Node P5 connections, the first end of the tenth transistor T10 receive the pulldown signal VGL, and the of the tenth transistor T10
Two ends are connect with the first node P1.The control terminal of the 11st transistor T11 is connect with the 5th node P5, described
The first end of 11st transistor T11 receives the pulldown signal VGL, the second end of the 11st transistor T11 with it is described
First output end GOUT1 connections.
It is similar with the 4th pull-down module M6, the 8th pull-down module M13 may include the 24th transistor T24 and
25th transistor T25.Wherein：The control terminal of the 24th transistor T24 is connect with the second node P2, described
The first end of 24th transistor T24 receives the pulldown signal VGL, the second end of the 24th transistor T24 with
The fourth node P4 connections.The control terminal of the 25th transistor T25 is connect with the second node P2, and described second
The first end of 15 transistor T25 receives the pulldown signal VGL, the second end of the 25th transistor T25 with it is described
Second output terminal GOUT2 connections.
Continuing with combining Fig. 1 and with reference to shown in figure 2, in the present exemplary embodiment, the first charging module M7 can be with
Including the tenth two-transistor T12 and the 13rd transistor T13.Wherein：The control terminal of the tenth two-transistor T12 with it is described
The first end of the P3 connections of third node, the tenth two-transistor T12 receives the first charging signals V1, and the described 12nd is brilliant
The second end of body pipe T12 is connect with the second node P2.The control terminal and first end of the 13rd transistor T13 receives
The first charging signals V1, the second end of the 13rd transistor T13 are connect with the third node P3.
It is similar with the first charging module M7, the second charging module M14 may include the 26th transistor T26 and
27th transistor T27.Wherein：The control terminal of the 26th transistor T26 is connect with the 6th node P6, described
The first end of 26th transistor T26 receives the second charging signals V2, the second end of the 26th transistor T26
It is connect with the 5th node P5.The control terminal and first end of the 27th transistor T27 receives second charging
Signal V2, the second end of the 27th transistor T27 are connect with the 6th node P6.
Continuing with combining Fig. 1 and with reference to shown in figure 2, in the present exemplary embodiment, the 9th pull-down module M15 can be with
Including the 14th transistor T14.Wherein：The control terminal of the 14th transistor T14 receives the third clock signal CK3,
The first end of the 14th transistor T14 receives the pulldown signal VGL, the second end of the 14th transistor T14 with
The first output end GOUT1 connections.
Similar with the 9th pull-down module M15, the tenth pull-down module M16 may include the 28th transistor T28.Its
In：The control terminal of the 28th transistor T28 receives the 4th clock signal CK4, the 28th transistor T28
First end receive the pulldown signal VGL, second end and the second output terminal of the 28th transistor T28
GOUT2 connections.
With continued reference to FIG. 2, and combining the driver' s timing figure in Fig. 3 A to the shift register in this example embodiment
The operation principle of unit is described in more detail.In this example embodiment, the first sequential scan signal FW can be controlled
The shift register cell is made along the first sequential scan, the second sequential scan signal BW can control the displacement and post
Storage unit is along the second sequential scan, and first sequence is with second sequence direction on the contrary, being for example respectively that forward direction is swept
It retouches and reverse scan.In forward scan, the first sequential scan signal FW is high level signal, and the second sequential scan signal BW is
Low level signal, in reverse scan, the first sequential scan signal FW is low level signal, and the second sequential scan signal BW is height
Level signal；It will be illustrated by taking forward scan as an example below.With reference to shown in figure 3A, in this example embodiment, first
When 1/2 signal period of phase-lead third clock signal CK3 of clock signal CK1, the first clock signal CK1 and third
The duty ratio of clock signal CK3 is 1/2, and the first clock signal CK1 is complementary with third clock signal CK3.Second clock signal CK2
1/2 signal period of the 4th clock signal CK4 of phase-lead, second clock signal CK2 and the 4th clock signal CK4's
Duty ratio is 1/2, and second clock signal CK2 and the 4th clock signal CK4 are complementary.The first clock signal CK1 with it is described
Second clock signal CK2 partly overlaps, such as the phase-lead second clock signal CK2 1/4 of the first clock signal CK1 believes
Number period.The third clock signal CK3 partly overlaps with the 4th clock signal CK4, such as third clock signal CK3
1/4 signal period of the 4th clock signal CK4 of phase-lead.In this example embodiment, first stage t1 in the example shown~
5th stage t5, the first charging signals V1 are, for example, low level, and the second charging signals V2 is, for example, high level.With reference to institute in figure 3B
Show, in this example embodiment, 1/2 signal period of the second charging signals of phase-lead V2 of the first charging signals V1, first
The duty ratio of charging signals V1 and the second charging signals V2 are 1/2, the first charging signals V1 and the second charging signals V2
Signal period for example can be 2 seconds.It is worked by taking the first shift register cell in shift register cell as an example
Journey may include with the next stage：
Continuing with A referring to figs. 2 and 3 is combined, t1, the first input signal SET1 are high level (this example in the first stage
In embodiment, by taking the first input signal SET1 and the second input signal SET2 are initial signal STV as an example), the
One clock signal CK1, third clock signal CK3 and the first reset signal RESET1 are low level；The first transistor T1 is led
It is logical.First sequential scan signal FW of high level is input to first node P1 by the first transistor T1, is filled to the first capacitance C1
Electricity.Due to first node P1 voltage be high level, to make third transistor T3, the 6th transistor T6, the 7th transistor T7,
20th two-transistor T22 and the 23rd transistor T23 conductings.Pulldown signal VGL is input to by the 6th transistor T6
Second node P2, it is low level to make second node P2.Pulldown signal VGL is input to third node P3 by the 7th transistor T7,
It is low level to make third node P3.Pulldown signal VGL is input to the 5th node P5 by the 20th two-transistor T22, makes the 5th
Node P5 is low level.Pulldown signal VGL is input to the 6th node P6 by the 23rd transistor T23, makes the 6th node P6
For low level, (in this example embodiment, the absolute value of the voltage of the pulldown signal VGL is more than the second charging signals V2
Absolute value).In addition, in the t1 stages, the voltage of fourth node P4 is high level, to keep the 8th transistor T8 and the 9th brilliant
The T9 conductings of body pipe.Pulldown signal VGL is input to second node P2 by the 8th transistor T8, make the level of second node P2 by into
One step pulls down.Pulldown signal VGL is input to third node P3 by the 9th transistor T9, keeps the level of the 9th node further
Drop-down.First clock signal CK1 is exported by third transistor T3 from the first output end GOUT1, due to the first clock signal CK1
It is low level in the t1 stages, therefore the first shift register cell output in shift register cell is low level signal.
With reference to shown in figure 3A, in second stage t2, the first clock signal CK1 is high level, the first input signal SET1,
Third clock signal CK3 and the first reset signal RESET1 is low level, the first transistor T1 shutdowns.In the first capacitance C1
Under the high level voltage signal function of storage, the voltage of first node P1 is still high level, to make third transistor T3, the 6th
Transistor T6, the 7th transistor T7, the 20th two-transistor T22 and the 23rd transistor T23 are held on.Pulldown signal
VGL is input to second node P2 by the 6th transistor T6, and it is low level to make second node P2.Pulldown signal VGL passes through the 7th
Transistor T7 is input to third node P3, and it is low level to make third node P3.Pulldown signal VGL passes through the 20th two-transistor
T22 is input to the 5th node P5, and it is low level to make the 5th node P5.Pulldown signal VGL passes through the 23rd transistor T23 inputs
To the 6th node P6, it is low level to make the 6th node P6.In addition, in the t2 stages, the voltage of fourth node P4 is high level, to
Make the 8th transistor T8 and the 9th transistor T9 conductings.Pulldown signal VGL is input to second node by the 8th transistor T8
P2 makes the level of second node P2 further be pulled down.Pulldown signal VGL is input to third node by the 9th transistor T9
P3 makes the level of the 9th node further be pulled down.First clock signal CK1 is by third transistor T3 from the first output end
GOUT1 is exported, and since the first clock signal CK1 is high level in the t2 stages, shift register cell output is high electricity
Ordinary mail number.
With reference to shown in figure 3A, it is in phase III t3, third clock signal CK3 and the first reset signal RESET1
High level, the first input signal SET1 and the first clock signal CK1 are low level, and second transistor T2 and the 14th is brilliant
The T14 conductings of body pipe.Low level first reset signal RESET1 is input to first node P1 by second transistor T2, to first
Capacitance C1 is resetted.Due to first node P1 voltage be low level, to make third transistor T3, the 6th transistor T6,
7th transistor T7, the 20th two-transistor T22 and the 23rd transistor T23 shutdowns.In addition, later half in the t3 stages
The voltage of section, fourth node P4 is low level, to make the 8th transistor T8, the 9th transistor T9 and the 21st transistor
T21 is turned off.Since the second charging signals V2 is high level, the 27th transistor T27 is connected, and the second charging signals V2 is input to
6th node P6；After the 21st transistor T21 and the 23rd transistor T23 shutdowns, the electricity of the 6th node P6
Pressure is the second charging signals V2, therefore the 6th node P6 is high level, and the 26th transistor T26 is led
It is logical.Flat the second charging signals V2 of high point is input to the 5th node P5 by the 26th transistor T26, makes
The 5th node P5 is high level.Since the voltage of the 5th node P5 is high level, to make the tenth transistor T10 and the
11 transistor T11 conductings.Pulldown signal VGL is input to first node P1 by the tenth transistor T10, makes first node P1's
Level is further pulled down.Pulldown signal VGL is input to signal output end, therefore shift LD by the 14th transistor T14
The output of device unit is low level signal.Pulldown signal VGL is input to the first output end GOUT1 by the 11st transistor T11,
The level of the first output end GOUT1 is set further to be pulled down, so that the output of shift register cell is more stablized.
In the above exemplary embodiments, the second charging signals V2 is high level, and the first charging signals V1 is low level, but the
Situation when two charging signals V2 are low level, the first charging signals V1 is high level is similar.For example, due to the first charging
Signal V1 is high level, and the 13rd transistor T13 is connected, and the first charging signals V1 is input to third node P3；In the 7th crystal
After pipe T7 and the 9th transistor T9 shutdowns, the voltage of the third node P3 is the first charging signals V1, therefore institute
It is high level to state third node P3, the tenth two-transistor T12 conductings.Flat the first charging signals V1 of high point passes through institute
It states the tenth two-transistor T12 and is input to the second node P2, it is high level to make the second node P2.Due to second node P2
Voltage be high level, to make the 4th transistor T4, the 5th transistor T5, the 24th transistor T24 and the 25th
Transistor T25 conductings.Pulldown signal VGL is input to first node P1 by the 4th transistor T4, makes the level of first node P1
Further pulled down.Pulldown signal VGL is input to the first output end GOUT1 by the 5th transistor T5, makes the first output end
The level of GOUT1 is further pulled down, so that the output of shift register cell is more stablized.
With reference to shown in figure 3A, t4 to the t5 stages after phase III t3, under the action of the second charging signals V2,
The 5th node P5 remains high level.Due to the 5th node P5 voltage be high level, to make the tenth transistor T10 with
And the 11st transistor T11 be held on.Pulldown signal VGL is input to first node P1 by the tenth transistor T10, makes first
The level of node P1 remains low level.Pulldown signal VGL is input to signal output end by the 11st transistor T11, therefore
Shift register cell output is low level signal.Also, when third clock signal CK3 is high level, the described 14th
Transistor T14 conductings, pulldown signal VGL are input to the first output end GOUT1 by the 14th transistor T14, make the first output
The level of end GOUT1 is further pulled down, so that the output of shift register cell is more stablized.
The work schedule of the second shift register cell is similar with the first shift register cell in shift register cell,
Therefore details are not described herein again.It is to be illustrated by taking forward scan as an example, but reversed in addition, in the above exemplary embodiments,
When scanning, the work schedule of shift register cell is similar with forward scan, therefore equally repeats no more herein.
The other advantage of above-mentioned shift register cell is exactly to use the transistor of single channel type to be all N-type thin
Film transistor can reduce the complexity and production cost of preparation process, Er Qieyou using the thin film transistor (TFT) of uniform type
Help Improving The Quality of Products.Certainly, those skilled in the art are easy to obtain shift register list provided by the present invention
Member can be all P-type transistor instead easily；Wherein, when each transistor is P-type transistor, the electricity of above-mentioned each signal
It is flat to be adaptively adjusted, therefore the realization method provided in this example embodiment is provided.
Further, this example embodiment additionally provides a kind of gate driving circuit, which includes upper
Any one shift register cell stated.For example：
With reference to shown in figure 4, gate driving circuit may include the first shift register cell in this example embodiment
SR1, the second shift register cell SR2, third shift register cell SR3 and the 4th shift register cell SR4 etc. are N number of
Shift register cell (remaining more shift register cell is not shown), wherein G1~G8 is indicated and each shift register list
The grid line of member electrical connection.In this example embodiment, the first input signal SET1 described in m+1 grades of shift register cells
For the signal (institute in the 1st grade of shift register cell of the first output end GOUT1 output described in m grades of shift register cells
It is initial signal STV to state the first input signal SET1)；Second input signal SET2 described in m+1 grades of shift register cells
For the signal (institute in the 1st grade of shift register cell of the outputs of second output terminal GOUT2 described in m grades of shift register cells
It is initial signal STV to state the second input signal SET2)；First reset signal RESET1 described in m grades of shift register cells
For the signal (in most final stage shift register cell of the first output end GOUT1 output described in m+1 grades of shift register cells
The first reset signal RESET1 is reset signal RST)；Second reset signal described in m grades of shift register cells
RESET2 is signal (the most final stage shift register of second output terminal GOUT2 outputs described in m+1 grades of shift register cells
Second reset signal RESET2 described in unit is reset signal RST2)；Wherein, 0<m<N.I.e. as shown in the figure, 3rd level displacement
First input signal SET1 described in register cell is that the first output end GOUT1 described in the 2nd grade of shift register cell is defeated
The signal gone out；Second input signal SET2 described in 3rd level shift register cell is described in the 2nd grade of shift register cell
The signal of second output terminal GOUT2 outputs；First reset signal RESET1 described in 2nd grade of shift register cell is 3rd level
The signal of first output end GOUT1 outputs described in shift register cell；Second is multiple described in 2nd grade of shift register cell
Position signal RESET2 is the signal etc. of second output terminal GOUT2 outputs described in 3rd level shift register cell.
With reference to shown in figure 5, gate driving circuit may include the first shift register cell in this example embodiment
SR1, the second shift register cell SR2, third shift register cell SR3, the 4th shift register cell SR4, the 5th move
N number of shift register cell (remaining more shift LD such as bit register cell S R5 and the 6th shift register cell SR6
Device unit is not shown), wherein G1~G12 indicates the grid line being electrically connected with each shift register cell.This example embodiment
In, the first input signal SET1 described in m+1 grades of shift register cells is the described in m-1 grades of shift register cells
(the first input signal SET1 is equal described in the 1st grade and the 2nd grade of shift register cell for the signal of two output end GOUT2 outputs
For initial signal STV)；Second input signal SET2 described in m+1 grades of shift register cells is m grades of shift register lists
(the second input signal SET2 is the signal of first output end GOUT1 outputs described in member described in the 1st grade of shift register cell
Initial signal STV)；Second reset signal RESET2 described in m-1 grades of shift register cells is m+1 grades of shift registers
(2nd grade reciprocal and most the described in final stage shift register cell of the signal of first output end GOUT1 output described in unit
Two reset signal RESET2 are reset signal RST)；First reset signal RESET1 described in m grades of shift register cells
For the signal (in most final stage shift register cell of the outputs of second output terminal GOUT2 described in m+1 grades of shift register cells
The first reset signal RESET1 is reset signal RST)；Wherein, 1<m<N.I.e. as shown in the figure, the 4th grade of shift register
First input signal SET1 described in unit is the letter of second output terminal GOUT2 outputs described in the 2nd grade of shift register cell
Number；Second input signal SET2 described in 4th grade of shift register cell is defeated for described in 3rd level shift register cell first
The signal of outlet GOUT1 outputs；Second reset signal RESET2 described in 2nd grade of shift register cell is that the 4th grade of displacement is posted
The signal of first output end GOUT1 outputs described in storage unit；First reset signal described in 3rd level shift register cell
RESET1 is the signal etc. of second output terminal GOUT2 outputs described in the 4th grade of shift register cell.
It will be readily appreciated by those skilled in the art that the gate driving circuit in Fig. 4 and Fig. 5 only plays example；
In other exemplary embodiments of the disclosure, including any one of the above shift register cell in this example embodiment
Gate driving circuit may be other connection types, and particular determination is not done to this in the present exemplary embodiment.
Further, this example embodiment additionally provides a kind of display device, which includes above-mentioned arbitrary
A kind of gate driving circuit.In the present exemplary embodiment, which can be liquid crystal display device or OLED display dresses
It sets, in other exemplary embodiments of the disclosure, which is also likely to be PLED (Polymer Light-Emitting
Diode, polymer LED) display device, PDP (Plasma Display Panel, plasma are shown) display device
Deng other panel display apparatus, i.e., do not limit to the scope of application in this example embodiment especially.
In conclusion in the shift register cell that this example embodiment is provided, including structure it is similar first
Shift register cell and the second shift register cell, and the first shift register cell and the second shift register cell
Mutually control, therefore can preferably realize the first sequential scan and the second sequential scan.In addition, in the first shift register list
In member, the drop-down for first node and the first output end is double drop-downs, in the second shift register cell, for the 4th
The drop-down of node and second output terminal is double drop-downs, therefore the waveform of the gated sweep signal of shift register cell output is more
Add stabilization.And then the display of display device can be further promoted by the shift register cell in this example embodiment
Effect.
The disclosure is described by above-mentioned related embodiment, however above-described embodiment is only the example for implementing the disclosure.
It must be noted that the embodiment disclosed is not limiting as the scope of the present disclosure.On the contrary, do not depart from the disclosure spirit and
It is changed and retouched made by range, belongs to the scope of patent protection of the disclosure.
Claims (18)
1. a kind of shift register cell, which is characterized in that including：
First input module provides one first sequential scan signal to first node for responding one first input signal, and
It responds one first reset signal and one second sequential scan signal is provided to the first node；
One first clock signal is provided to the first output end by the first output module, the signal for responding the first node；
One pulldown signal is provided to the first node and institute by the first pull-down module, the signal for responding a second node
State the first output end；
Second pull-down module, for respond the signal of the first node by the pulldown signal be provided to the second node with
An and third node；
Third pull-down module, for respond the signal of a fourth node by the pulldown signal be provided to the second node and
Third node；
4th pull-down module, for respond the signal of one the 5th node by the pulldown signal be provided to the first node and
First output end；
One first charging signals are provided to second section by the first charging module, the signal for responding the third node
Point；
The first sequential scan signal is provided described Section four by the second input module for responding one second input signal
The second sequential scan signal is provided to the fourth node by point, and one second reset signal of response；
One second clock signal is provided to second output terminal by the second output module, the signal for responding the fourth node；
5th pull-down module, for respond the signal of the 5th node by the pulldown signal be provided to the fourth node with
And the second output terminal；
6th pull-down module, for respond the signal of the fourth node by the pulldown signal be provided to the 5th node with
And one the 6th node；
7th pull-down module, for respond the signal of the first node by the pulldown signal be provided to the 5th node with
And the 6th node；
8th pull-down module, for respond the signal of the second node by the pulldown signal be provided to the fourth node with
And the second output terminal；
One second charging signals are provided to described Section five by the second charging module, the signal for responding the 6th node
Point, second charging signals are complementary with first charging signals.
2. shift register cell according to claim 1, which is characterized in that the shift register cell further includes：
The pulldown signal is provided to first output end by the 9th pull-down module for responding a third clock signal；Institute
State third clock signal and first clock signal complement；
The pulldown signal is provided to the second output terminal by the tenth pull-down module for responding one the 4th clock signal；Institute
It is complementary with the second clock signal to state the 4th clock signal.
3. shift register cell according to claim 2, which is characterized in that wherein：
First input module includes：
The first transistor, the control terminal of the first transistor receive first input signal, and the of the first transistor
One end receives the first sequential scan signal, and the second end of the first transistor is connect with the first node；
Second transistor, the control terminal of the second transistor receive first reset signal, and the of the second transistor
One end receives the second sequential scan signal, and the second end of the second transistor is connect with the first node；
Second input module includes：
The control terminal of 15th transistor, the 15th transistor receives second input signal, the 15th crystal
The first end of pipe receives the first sequential scan signal, and second end and the fourth node of the 15th transistor connect
It connects；
The control terminal of 16th transistor, the 16th transistor receives second reset signal, the 16th crystal
The first end of pipe receives the second sequential scan signal, and second end and the fourth node of the 16th transistor connect
It connects.
4. shift register cell according to claim 2, which is characterized in that wherein：
First output module includes：
Third transistor, the control terminal of the third transistor are connect with the first node, and the first of the third transistor
End receives first clock signal, and the second end of the third transistor is connect with first output end；
First capacitance is connected between the first node and first output end；
Second output module includes：
The control terminal of 17th transistor, the 17th transistor is connect with the fourth node, the 17th transistor
First end receive the second clock signal, the second end of the 17th transistor is connect with the second output terminal；
Second capacitance is connected between the fourth node and the second output terminal.
5. shift register cell according to claim 2, which is characterized in that wherein：
First pull-down module includes：
The control terminal of 4th transistor, the 4th transistor is connect with the second node, and the first of the 4th transistor
End receives the pulldown signal, and the second end of the 4th transistor is connect with the first node；
The control terminal of 5th transistor, the 5th transistor is connect with the second node, and the first of the 5th transistor
End receives the pulldown signal, and the second end of the 5th transistor is connect with first output end；
5th pull-down module includes：
The control terminal of 18th transistor, the 18th transistor is connect with the 5th node, the 18th transistor
First end receive the pulldown signal, the second end of the 18th transistor is connect with the fourth node；
The control terminal of 19th transistor, the 19th transistor is connect with the 5th node, the 19th transistor
First end receive the pulldown signal, the second end of the 19th transistor is connect with the second output terminal.
6. shift register cell according to claim 2, which is characterized in that wherein：
Second pull-down module includes：
The control terminal of 6th transistor, the 6th transistor is connect with the first node, and the first of the 6th transistor
End receives the pulldown signal, and the second end of the 6th transistor is connect with the second node；
The control terminal of 7th transistor, the 7th transistor is connect with the first node, and the first of the 7th transistor
End receives the pulldown signal, and the second end of the 7th transistor is connect with the third node；
6th pull-down module includes：
The control terminal of 20th transistor, the 20th transistor is connect with the fourth node, the 20th transistor
First end receive the pulldown signal, the second end of the 20th transistor is connect with the 5th node；
The control terminal of 21st transistor, the 21st transistor is connect with the fourth node, and the described 21st
The first end of transistor receives the pulldown signal, and the second end of the 21st transistor is connect with the 6th node.
7. shift register cell according to claim 2, which is characterized in that wherein：
The third pull-down module includes：
The control terminal of 8th transistor, the 8th transistor is connect with the fourth node, and the first of the 8th transistor
End receives the pulldown signal, and the second end of the 8th transistor is connect with the second node；
The control terminal of 9th transistor, the 9th transistor is connect with the fourth node, and the first of the 9th transistor
End receives the pulldown signal, and the second end of the 9th transistor is connect with the third node；
7th pull-down module includes：
The control terminal of 20th two-transistor, the 20th two-transistor is connect with the first node, and the described 22nd
The first end of transistor receives the pulldown signal, and the second end of the 20th two-transistor is connect with the 5th node；
The control terminal of 23rd transistor, the 23rd transistor is connect with the first node, and the described 23rd
The first end of transistor receives the pulldown signal, and the second end of the 23rd transistor is connect with the 6th node.
8. shift register cell according to claim 2, which is characterized in that wherein：
4th pull-down module includes：
The control terminal of tenth transistor, the tenth transistor is connect with the 5th node, and the first of the tenth transistor
End receives the pulldown signal, and the second end of the tenth transistor is connect with the first node；
The control terminal of 11st transistor, the 11st transistor is connect with the 5th node, the 11st transistor
First end receive the pulldown signal, the second end of the 11st transistor is connect with first output end；
8th pull-down module includes：
The control terminal of 24th transistor, the 24th transistor is connect with the second node, and the described 24th
The first end of transistor receives the pulldown signal, and the second end of the 24th transistor is connect with the fourth node；
The control terminal of 25th transistor, the 25th transistor is connect with the second node, and the described 25th
The first end of transistor receives the pulldown signal, and second end and the second output terminal of the 25th transistor connect
It connects.
9. shift register cell according to claim 2, which is characterized in that wherein：
First charging module includes：
The control terminal of tenth two-transistor, the tenth two-transistor is connect with the third node, the tenth two-transistor
First end receive first charging signals, the second end of the tenth two-transistor is connect with the second node；
13rd transistor, the control terminal and first end of the 13rd transistor receive first charging signals, described
The second end of 13rd transistor is connect with the third node；
Second charging module includes：
The control terminal of 26th transistor, the 26th transistor is connect with the 6th node, and the described 26th
The first end of transistor receives second charging signals, and second end and the 5th node of the 26th transistor connect
It connects；
27th transistor, the control terminal and first end of the 27th transistor receive second charging signals,
The second end of 27th transistor is connect with the 6th node.
10. shift register cell according to claim 2, which is characterized in that wherein：
9th pull-down module includes：
The control terminal of 14th transistor, the 14th transistor receives the third clock signal, the 14th crystal
The first end of pipe receives the pulldown signal, and the second end of the 14th transistor is connect with first output end；
Tenth pull-down module includes：
28th transistor, control terminal reception the 4th clock signal of the 28th transistor, the described 20th
The first end of eight transistors receives the pulldown signal, and second end and the second output terminal of the 28th transistor connect
It connects.
11. according to the shift register cell described in claim 1~10 any one, which is characterized in that first sequence
Scanning signal controls the shift register cell along the first sequential scan, and the second sequential scan signal controls the shifting
For bit register unit along the second sequential scan, first sequence is opposite with second sequence direction.
12. according to the shift register cell described in claim 2~10 any one, which is characterized in that first clock
Signal is Chong Die with the second clock signal section；The third clock signal is Chong Die with the 4th clock signal portion.
13. according to the shift register cell described in claim 3~10 any one, which is characterized in that the transistor is N
Type channel transistor is P-type channel transistor.
14. according to the shift register cell described in claim 3~10 any one, which is characterized in that the transistor is
Amorphous silicon transistor, low-temperature polycrystalline silicon transistor or oxide semi conductor transistor.
15. a kind of gate driving circuit, which is characterized in that include that displacement according to claim 1~14 any one is posted
Storage unit.
16. according to gate driving circuit described in claim 15, which is characterized in that the gate driving circuit includes cascade N
A shift register cell；Wherein：
First input signal described in m+1 grades of shift register cells is defeated for described in m grades of shift register cells first
The signal of outlet output；
Second input signal described in m+1 grades of shift register cells is defeated for described in m grades of shift register cells second
The signal of outlet output；
First reset signal described in m grades of shift register cells is defeated for described in m+1 grades of shift register cells first
The signal of outlet output；
Second reset signal described in m grades of shift register cells is defeated for described in m+1 grades of shift register cells second
The signal of outlet output；Wherein, 0<m<N.
17. according to gate driving circuit described in claim 15, which is characterized in that the gate driving circuit includes cascade N
A shift register cell；Wherein：
First input signal described in m+1 grades of shift register cells is second described in m-1 grades of shift register cells
The signal of output end output；
Second input signal described in m+1 grades of shift register cells is defeated for described in m grades of shift register cells first
The signal of outlet output；
Second reset signal described in m-1 grades of shift register cells is first described in m+1 grades of shift register cells
The signal of output end output；
First reset signal described in m grades of shift register cells is defeated for described in m+1 grades of shift register cells second
The signal of outlet output；Wherein, 1<m<N.
18. a kind of display device, which is characterized in that including according to gate driving electricity described in claim 15~17 any one
Road.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106128348B (en) * | 2016-08-24 | 2018-03-13 | 武汉华星光电技术有限公司 | Scan drive circuit |
| CN106448543B (en) * | 2016-12-20 | 2019-05-24 | 上海中航光电子有限公司 | A kind of gate driving circuit, display panel and display device |
| CN107068032B (en) * | 2017-01-22 | 2020-06-12 | 上海中航光电子有限公司 | Scanning unit and gate drive circuit |
| CN106898292B (en) * | 2017-05-05 | 2018-07-20 | 合肥鑫晟光电科技有限公司 | Scan drive circuit and its driving method, array substrate and display device |
| CN108877659B (en) | 2018-08-03 | 2021-01-22 | 京东方科技集团股份有限公司 | Gate driving circuit, display device and driving method thereof |
| CN110858469B (en) | 2018-08-23 | 2021-02-09 | 合肥京东方卓印科技有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN109686296B (en) * | 2019-03-05 | 2022-05-20 | 合肥鑫晟光电科技有限公司 | Shift register module, driving method and grid driving circuit |
| CN110619838B (en) | 2019-11-04 | 2021-12-21 | 京东方科技集团股份有限公司 | Shift register unit circuit, driving method, gate driver and display device |
| CN112687230B (en) * | 2021-01-29 | 2022-06-10 | 云谷（固安）科技有限公司 | Shift register, grid drive circuit and display panel |
| CN112951146B (en) * | 2021-04-25 | 2024-03-15 | 厦门天马微电子有限公司 | Shift register, driving method, scanning driving circuit, display panel and device |
| CN113192454B (en) * | 2021-05-14 | 2023-08-01 | 武汉天马微电子有限公司 | Scan driving circuit, method, display panel and display device |
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