CN105703774B - The time series stereodata method of SAR ADC - Google Patents
The time series stereodata method of SAR ADC Download PDFInfo
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- CN105703774B CN105703774B CN201511031526.7A CN201511031526A CN105703774B CN 105703774 B CN105703774 B CN 105703774B CN 201511031526 A CN201511031526 A CN 201511031526A CN 105703774 B CN105703774 B CN 105703774B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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Abstract
The invention discloses the time series stereodata method of SAR ADC a kind of, this method are as follows: after satisfaction first jumps condition, the ADC is jumped into sample states；It jumps after the ADC satisfaction second in sample states jumps condition into transition status；It jumps when the ADC in transition status meets after third jumps condition into sample states, jumps when the ADC in transition status meets after the forth jump turns condition into idle state.The present invention allows to adjust the sampling time, and supports to interrupt in whole work process, restart to sample or convert.
Description
Technical field
The present invention relates to a kind of technical fields of data converter, and in particular to a kind of time series stereodata of SAR ADC
Method.
Background technique
Analog-digital converter (ADC), refers to the device that the analog signal of continuous variable is converted to discrete digital signal.Number
According to converter due to the difference of resolution ratio and speed, many kinds of, wherein Approach by inchmeal (SAR) ADC is due to low-power consumption, small ruler
The advantages that very little, makes it have very big advantage under the application environment of middle high resolution, speed lower than 4Msps.SAR ADC is adopted
With the algorithm of Approach by inchmeal, generated by turn by being compared the analog signal values of input with the analogue value of mediant character code
Digital code.
Usually there are two process, sampling and conversions for SAR ADC working condition.Sampling is i.e. by externally input analog signal values
It is accurately stored in inside ADC, is stored it on capacitor under normal circumstances.The conversion stage then pass through successive approximation algorithm according to
Secondary to obtain N digit numeric code, SAR ADC conversion in General N position needs N+1 clock cycle.
Current SAR ADC is the fixed sampling time, starts sampling after starting until conversion end, in the meantime
Interior cannot be interrupted and respond the new input analogue value, these can all limit the application range of ADC.
Summary of the invention
In view of this, the main purpose of the present invention is to provide the time series stereodata methods of SAR ADC a kind of.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
The embodiment of the present invention provides the time series stereodata method of SAR ADC a kind of, this method are as follows: when satisfaction first jumps
After condition, the ADC is jumped into sample states；Entrance is jumped after the ADC satisfaction second in sample states jumps condition
Transition status；It jumps when the ADC in transition status meets after third jumps condition into sample states, when in transition status
ADC meet after the forth jump turns condition and jump into idle state；
Described first jumps condition are as follows: the sampling time be zero and ADC be in idle condition or the sampling time be not zero and
ADC is in idle condition and enabling signal is height at this time；
Second jumps condition are as follows: the sampling time is zero and ADC is in sample states and enabling signal is high at this time, or is adopted
The sample time is not zero and ADC is in sample states, and enabling signal is that the counting of low and counter reaches the sampling time at this time；
Third jumps condition are as follows: the sampling time is zero and converts marking signal to be to be not zero in the high or sampling time
And ADC is in transition status and enabling signal is height at this time；
The forth jump turns condition are as follows: the sampling time is not zero and converts marking signal as height, and enabling signal is at this time
It is low.
In above scheme, this method further include: when the ADC state transition there is a problem in logic, the ADC into
Enter to illegal state, the ADC in illegal state, which meets after the fifth jump turns condition, to be jumped into idle state, is met the 6th and is jumped
It is jumped after condition into sample states；Described the fifth jump turns condition and is not zero for the sampling time, is now in illegal state, and this
When enabling signal be it is low；Described 6th jumps condition be that zero and ADC is in illegal state or sampling time not in the sampling time
It is zero and enabling signal is high at this time and ADC is in illegal state at this time.
In above scheme, if the ADC in illegal state is not received by enabling signal, jumped immediately into idle
State is jumped immediately if receiving enabling signal into sample states.
In above scheme, this method further include: the ADC is in sample states, sets the sampling time by counter, adopts
The sample time is the clock cycle of integral multiple, when enabling signal is high, when the numerical value of the counter samples required for being set as
Between, each clock cycle rising edge counter numerical value subtracts one, when numerical value is for the moment, to generate ADC and jump into conversion in counter
The signal of state.
In above scheme, this method further include: when enabling signal is that high and ADC is in idle condition, the ADC is jumped
Into sample states.
In above scheme, this method further include: complete by turn according to successive approximation algorithm when the ADC is in transition status
At conversion, the signal converted is generated, is jumped if enabling signal arrives into sampled signal, is otherwise jumped into idle shape
State；
In above scheme, this method further include: the ADC is interrupted at work, when the ADC be in sample states or
When transition status, enabling signal arrives, then the ADC enters sample states.
Compared with prior art, beneficial effects of the present invention:
(1) present invention allows user's autonomous configuration, keeps entire sampling rate adjustable by allowing to adjust the sampling time,
There is bigger freedom degree in the use of ADC；
(2) present invention allows ADC to be interrupted in whole work process, into corresponding state, makes the application of ADC
It is more convenient, because new conversion can be started without waiting for conversion end, the operating time is saved to a certain extent, is mentioned
The high stability of data acquisitions.
Detailed description of the invention
Fig. 1 is structure principle chart of the invention；
Fig. 2 is the functional block diagram of the counter in the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
The invention discloses the time series stereodata methods of SAR ADC a kind of, as shown in Figure 1, this method are as follows: when meeting the
After one jumps condition T1, the ADC is jumped into sample states；Condition T2 is jumped when the ADC in sample states meets second
After jump into transition status；It jumps after condition T3 when the ADC in transition status meets third and jumps into sample states, when
ADC in transition status, which meets after the forth jump turns condition T4, to be jumped into idle state；
Described first jumps condition T1 are as follows: the sampling time is zero and ADC is in idle condition or the sampling time is not zero
And ADC is in idle condition and enabling signal is height at this time；
Second jumps condition T2 are as follows: and the sampling time is zero and ADC is in sample states and enabling signal is high at this time, or
Sampling time is not zero and ADC is in sample states, and enabling signal is that the counting of low and counter reaches the sampling time at this time；
Third jumps condition T3 are as follows: the sampling time is zero and converts marking signal to be the high or sampling time not to be
Zero and ADC is in transition status and enabling signal is height at this time；
The forth jump turns condition T4 are as follows: the sampling time is not zero and converts marking signal as height, and enabling signal at this time
It is low.
This method further include: when the ADC state transition there is a problem in logic, the ADC enters illegal shape
State, the ADC in illegal state, which meets after the fifth jump turns condition T5, to be jumped into idle state, after satisfaction the 6th jumps condition T6
It jumps and enters sample states；Described the fifth jump turns condition T5 and is not zero for the sampling time, is now in illegal state, and open at this time
Dynamic signal be it is low, the described 6th jumps condition T6 be that zero and ADC is in illegal state or the sampling time is not in the sampling time
Zero and enabling signal is high at this time and ADC is in illegal state at this time.
If the ADC in illegal state is not received by enabling signal, jump immediately into idle state, if receiving
It then jumps immediately to enabling signal into sample states.
The ADC is in sample states, sets the sampling time by counter, the sampling time is the clock week of integral multiple
Phase, when enabling signal is high, the numerical value of the counter is set as required sampling time, each clock cycle rising edge meter
Number device numerical value subtracts one, when numerical value is for the moment, to generate ADC and jump the signal into transition status in counter.
When enabling signal is that high and ADC is in idle condition, the ADC is jumped into sample states.
When the ADC is in transition status, completes to convert by turn according to successive approximation algorithm, generate the letter converted
Number, it jumps if enabling signal arrives into sampled signal, otherwise jumps into idle state；
The ADC is interrupted at work, and when the ADC is in sample states or transition status, enabling signal arrives,
Then the ADC enters sample states.
Embodiment:
The invention discloses the time series stereodata method of SAR ADC a kind of, as shown in Figure 1, when SAR ADC of the invention
Sequence logic control method includes four kinds of states: idle state, sample states, transition status and illegal state, wherein when ADC is multiple
Position or it is enabled after enter idle state, ADC does not work when idle state, and waiting meets after T1 jumps condition and enters sampling
State, sampling time may be configured as N number of clock cycle, and N can be arbitrary number, including zero.When N is zero and is in the free time at this time
When state, jump into sample states, when N is not zero and is now in idle state, waiting enabling signal START becomes
Height enters sample states, wherein enabling signal START only allows a clock cycle for height, and it is dynamic otherwise to will appear mistake
Make.
In sample states, satisfaction jumps condition T2 and jumps into transition status.
As shown in Fig. 2, in sample states, using the counter controls sampling time.When enabling signal START is height, counting
Device numerical value is set to N, and N is the sampling time of setting, if be in sample states at this time, counts when each rising edge clock arrives
Device numerical value subtracts one, and otherwise counter keeps current value；When the numerical value of counter is for the moment, to generate the letter for entering transition status
Number.Wherein, if N is zero, and it is in sample states at this time, then when enabling signal START is that height enters transition status, and counts
Device then keeps current value constant.
In transition status, SAR ADC works according to successive approximation algorithm.Satisfaction jump condition T3 jump entrance adopt
Sample state, satisfaction jump condition T4 and jump into idle state.ADC system can issue completion signal after the completion of successful conversion
When DATARDY, i.e. DATARDY signal are high, convert.If the sampling time is set as zero at this time, directly jumps to enter and adopt
Sample state is then jumped from transition status at this time into empty if the sampling time is not zero, and does not have enabling signal arrival at this time
Not busy state；Transition status allows to be interrupted on the way, and in transition status, enabling signal arrives, i.e., START signal is height, then jumps
It rotates into sample states, ADC starts to sample the input analogue value, requires the sampling time that cannot be set as zero at this time, no
It then will appear mistake.
It is described that jump condition T1-T6 as shown in the table:
In table, " ∨ " expression "or", " ∧ " expression " and ", IDLE=1 indicates that ADC is idle state, SAMPLE=1 at this time
Indicate that ADC is in sample states at this time, CONVERT=1 indicates that ADC is transition status at this time, and ILEGAL=1 is expressed as illegally
State, START=1 indicate that enabling signal is height at this time, and N=0 indicates that the sampling time is that zero, N ≠ 0 indicates that the sampling time is not
Zero, COUNT=1 indicate that counter counting terminates, and DATARDY=1 expression converts mark.
The present invention is described state using two binary codes, it is contemplated that state it is complete, define illegal state,
Guarantee that sequential logic will not enter endless loop because of malfunction in the process of running.When ADC system enters illegal state,
It must then jump immediately into other states.Meet T5 and jump condition and jump into idle state, meets T6 and jump condition i.e.
It jumps and enters sample states.If the not arrival of enabling signal and when being in illegal state at this time, jumps immediately into idle
State then jumps if enabling signal also arrives at this time, and is in illegal state into sample states immediately, requires to adopt at this time
The sample time is not zero.
To sum up, the entire ADC working sequence of the scheme control of adoption status machine of the present invention, and realize the adjustable of sampling time
Section property supports the interrupt action in whole work process, re-starts sampling or conversion, and that has expanded ADC significantly applies model
It encloses.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (7)
1. a kind of time series stereodata method of SAR ADC, which is characterized in that this method are as follows: after satisfaction first jumps condition,
The ADC is jumped into sample states；It jumps after the ADC satisfaction second in sample states jumps condition into conversion shape
State；It jumps when the ADC in transition status meets after third jumps condition into sample states, as the ADC for being in transition status
Meet after the forth jump turns condition and jumps into idle state；
Described first jumps condition are as follows: the sampling time is zero and ADC is in idle condition or the sampling time is not zero and ADC
It is in idle condition and enabling signal is height at this time；
Second jumps condition are as follows: the sampling time is zero and ADC is in sample states and enabling signal is high at this time, or when sampling
Between be not zero and ADC is in sample states, and enabling signal is that the counting of low and counter reaches the sampling time at this time；
Third jumps condition are as follows: the sampling time be zero and convert marking signal be high or the sampling time be not zero and
ADC is in transition status and enabling signal is height at this time；
The forth jump turns condition are as follows: the sampling time is not zero and converts marking signal as height, and enabling signal is low at this time.
2. the time series stereodata method of SAR ADC according to claim 1, which is characterized in that this method further include: when
When the ADC state transition there is a problem in logic, the ADC enters illegal state, and the ADC in illegal state meets
The fifth jump jumps after turning condition into idle state, and satisfaction the 6th jumps after jumping condition into sample states；
Described the fifth jump turns condition are as follows: the sampling time is not zero, and is now in illegal state, and enabling signal is low at this time；
Described 6th jumps condition be that zero and ADC is in illegal state or the sampling time is not zero and at this time in the sampling time
Enabling signal is high and ADC is in illegal state at this time.
3. the time series stereodata method of SAR ADC according to claim 2, it is characterised in that: described to be in illegal shape
If the ADC of state is not received by enabling signal, jumped immediately into idle state, jumped immediately if receiving enabling signal into
Enter sample states.
4. the time series stereodata method of SAR ADC according to claim 1, which is characterized in that this method further include: institute
It states ADC and is in sample states, the sampling time is set by counter, the sampling time is the clock cycle of integral multiple, when starting is believed
Number for it is high when, the numerical value of the counter is set as the required sampling time, and each clock cycle rising edge counter numerical value subtracts
One, when numerical value is for the moment, to generate ADC and jump the signal into transition status in counter.
5. the time series stereodata method of SAR ADC according to claim 1, which is characterized in that this method further include: when
When enabling signal is that high and ADC is in idle condition, the ADC is jumped into sample states.
6. the time series stereodata method of SAR ADC according to claim 1, which is characterized in that this method further include: institute
It when stating ADC and being in transition status, completes to convert by turn according to successive approximation algorithm, generates the signal converted, if starting letter
Number arrival is then jumped into sampled signal, is otherwise jumped into idle state.
7. the time series stereodata method of SAR ADC according to claim 1, which is characterized in that this method further include: institute
It states ADC to be interrupted at work, when the ADC is in sample states or transition status, enabling signal arrives, then the ADC
Into sample states.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102624389A (en) * | 2011-01-31 | 2012-08-01 | 海力士半导体有限公司 | Method and system for calibrating column parallel ADCs |
| CN102946252A (en) * | 2012-11-28 | 2013-02-27 | 国电南瑞科技股份有限公司 | Method and corresponding system for denoising horizon signals during sampling time of analog-digital converter (ADC) |
| CN103078643A (en) * | 2011-10-25 | 2013-05-01 | 联发科技股份有限公司 | Successive-approximation-register analog-to-digital convertor and related controlling method |
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| US6956518B1 (en) * | 2004-03-31 | 2005-10-18 | Silicon Labs Cp, Inc. | Method and apparatus for subclocking a SAR analog-to-digital converter |
| JP4932619B2 (en) * | 2007-07-03 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | A / D converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102624389A (en) * | 2011-01-31 | 2012-08-01 | 海力士半导体有限公司 | Method and system for calibrating column parallel ADCs |
| CN103078643A (en) * | 2011-10-25 | 2013-05-01 | 联发科技股份有限公司 | Successive-approximation-register analog-to-digital convertor and related controlling method |
| CN102946252A (en) * | 2012-11-28 | 2013-02-27 | 国电南瑞科技股份有限公司 | Method and corresponding system for denoising horizon signals during sampling time of analog-digital converter (ADC) |
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Address after: 203, room 11, building two, two software park, Shenzhen Road, Nanshan District science and technology, Guangdong, Shenzhen 518057, China Patentee after: Fengji Technology (Shenzhen) Co., Ltd Address before: 203, room 11, building two, two software park, Shenzhen Road, Nanshan District science and technology, Guangdong, Shenzhen 518057, China Patentee before: FORTIOR TECHNOLOGY (SHENZHEN) Co.,Ltd. |
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