CN105643431B - Wafer grinding method - Google Patents
Wafer grinding method Download PDFInfo
- Publication number
- CN105643431B CN105643431B CN201410720427.9A CN201410720427A CN105643431B CN 105643431 B CN105643431 B CN 105643431B CN 201410720427 A CN201410720427 A CN 201410720427A CN 105643431 B CN105643431 B CN 105643431B
- Authority
- CN
- China
- Prior art keywords
- wafer
- functional surface
- protective
- protective layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 69
- 238000000227 grinding Methods 0.000 title claims abstract description 33
- 230000001681 protective effect Effects 0.000 claims abstract description 60
- 239000011241 protective layer Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims abstract description 30
- 239000002390 adhesive tape Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 15
- 238000005498 polishing Methods 0.000 claims description 11
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 claims description 10
- 239000011261 inert gas Substances 0.000 claims description 10
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 12
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 11
- 239000002210 silicon-based material Substances 0.000 description 9
- 239000012459 cleaning agent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- -1 and the like Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a wafer grinding method, which comprises the following steps: providing a wafer, wherein the wafer comprises a functional surface and a back surface opposite to the functional surface; after a protective layer is formed on the functional surface of the wafer, covering a layer of protective adhesive tape on the protective layer; then, the wafer is placed on a grinding device, and the back surface of the wafer is ground to remove the wafer with partial thickness; and removing the protective tape, and then removing the protective layer. Before the grinding, a protective layer is formed on the functional surface of the wafer, and then a layer of protective adhesive tape is covered on the protective layer. The protective tape can effectively protect the structure on the wafer functional surface from being damaged in the grinding process, is adhered to the protective layer, can effectively overcome the contact between the protective tape and the wafer functional surface, and further can remove the defects of parts on the surface of part of the wafer functional surface in the process of tearing off the protective tape after the grinding process, so that the structural damage on the wafer functional surface is reduced.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a wafer grinding method.
Background
With the development of technology, the functions of electronic products are continuously enhanced, and the sizes of electronic products are continuously reduced. In the field of semiconductor device manufacturing, the size of semiconductor devices is continuously decreasing, and the size of electronic chips is continuously decreasing.
Therefore, in the manufacturing process of the semiconductor device, after a plurality of semiconductor devices are formed on the functional surface of the wafer, a Back Grinding (BG) process is performed, and the wafer with a part of thickness removed from the Back surface corresponding to the functional surface is ground by a planarization process, so as to reduce the thickness of a chip formed subsequently.
In the process of grinding the back of the wafer, a layer of protective tape (BG tape) is covered on the functional surface of the wafer to prevent the functional surface of the wafer from being polluted by impurities generated in the process of grinding the back of the wafer and prevent the functional surface of the wafer from being damaged due to direct contact between the functions of the wafer and grinding equipment (such as a sucker for fixing the wafer), thereby reducing the quality of the formed chip.
However, even after the wafer BG process, after the protective tape on the functional surface of the wafer is removed, it is found that the functional surface of the wafer still has damage (Peeling), which affects the chip quality.
Therefore, it is an urgent problem to be solved by those skilled in the art how to improve the polishing process of the wafer to reduce the wafer damage.
Disclosure of Invention
The invention provides a wafer grinding method to reduce the wafer damage degree in the wafer Backside Grinding (BG) process.
In order to solve the above problems, the present invention provides a wafer polishing method, comprising:
providing a wafer, wherein the wafer comprises a functional surface and a back surface opposite to the functional surface;
forming a protective layer on the functional surface of the wafer;
covering a protective adhesive tape on the protective layer;
placing the wafer on a grinding device, and grinding the back surface of the wafer to remove a part of the thickness of the wafer;
and removing the protective tape, and then removing the protective layer.
Optionally, the material of the protective layer is an organic silicon material.
Optionally, the material of the protective layer is hexamethyldisiloxane.
Optionally, the step of forming the protective layer comprises: and forming a hexamethyldisiloxane layer on the functional surface of the wafer by adopting chemical vapor deposition, and then carrying out an annealing process to form the protective layer.
Optionally, the annealing process includes: and under the inert gas environment, controlling the annealing temperature to be 180-200 ℃, and continuously annealing for 2-3 hours.
Optionally, the inert gas is nitrogen.
Optionally, the method for removing the protection layer is a wet cleaning process.
Optionally, in the wet cleaning process, an organic cleaning agent is used to remove the protective layer.
Optionally, in the wet cleaning process, the organic cleaning agent is a phenol solution.
Optionally, the step of the wet cleaning process includes: the volume ratio concentration of the phenol solution is greater than or equal to 20%, the cleaning temperature is 70-90 ℃, and the cleaning is continued for 3-10 minutes.
Compared with the prior art, the technical scheme of the invention has the following advantages:
before the grinding, a protective layer is formed on the functional surface of the wafer, and then a layer of protective adhesive tape is covered on the protective layer. The protective tape can effectively protect the structure on the wafer functional surface from being damaged in the grinding process, is adhered to the protective layer and can effectively overcome the contact between the protective tape and the wafer functional surface, so that the protective tape can damage the part of the part on the surface of the wafer functional surface in the process of tearing off the protective tape after the grinding process, and further the structural damage on the wafer functional surface is reduced.
Further optionally, the protective layer is made of an organic silicon material, and the organic silicon material and the wafer have good bonding strength, so that the bonding strength between the subsequent protective tape and the wafer is improved, and the wafer is protected by the protective tape; moreover, the organic silicon material removing process is convenient, and the damage of the organic silicon material removing process to the wafer is small, so that the damage of the wafer can be reduced after the grinding process, the removing process of the protective layer is simplified, and the process cost is reduced.
Drawings
FIG. 1 is a schematic diagram illustrating a wafer damaged by a protective tape torn off from a functional surface of the wafer in the prior art;
fig. 2 to 6 are schematic structural views illustrating a wafer polishing method according to an embodiment of the present invention.
Detailed Description
As described in the background art, in the conventional wafer back grinding process, even if the functional surface of the wafer is covered with the protective tape (BG tape), the functional surface of the wafer is still damaged after the protective tape is removed. The reason is analyzed:
the existing protective adhesive tape is adhered to the functional surface of the wafer, and the protective adhesive tape and the wafer have strong adhesion, so that the protective adhesive tape is prevented from falling off in the grinding process, the functional surface of the wafer is better protected and prevented from being polluted, and the functional surface of the wafer is prevented from being damaged due to direct contact with grinding equipment. However, after the grinding process, referring to fig. 1, due to the strong adhesion between the protective tape 20 and the wafer 10, during the process of tearing the protective tape 20 from the functional surface of the wafer 10, the protective tape 20 may damage parts 11 on the surface of the functional surface of the wafer 10, so as to damage the semiconductor device structure on the functional surface of the wafer 10, and further reduce the performance of the wafer 10. Particularly, as the size of the semiconductor device is continuously reduced, the structure is more precise, the damage of the semiconductor device caused by tearing off the protective tape is gradually increased, and the influence on the performance of the chip is gradually increased.
Therefore, the invention provides a wafer grinding method, which comprises the following steps: providing a wafer, wherein the wafer comprises a functional surface and a back surface opposite to the functional surface; after a protective layer is formed on the functional surface of the wafer, covering a layer of protective adhesive tape on the protective layer; then, the wafer is placed on a grinding device, and the back surface of the wafer is ground to remove the wafer with partial thickness; and removing the protective tape, and then removing the protective layer.
In the process of grinding the wafer, the protective adhesive tape can effectively protect the structure on the functional surface of the wafer from being damaged in the grinding process; before the protective tape is adhered to the functional surface of the wafer, the protective layer is formed on the functional surface, and then the protective tape is formed on the protective layer, so that the protective tape is prevented from being in direct contact with the functional surface of the wafer, the defect that the protective tape damages parts on the functional surface of the wafer in the process of tearing the protective tape after a grinding process due to the fact that the protective tape is caused by strong adhesion between the protective tape and the functional surface of the wafer is avoided, and further structural damage on the functional surface of the wafer is reduced, and the performance of a formed semiconductor device is ensured.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 6 are schematic structural views illustrating a wafer polishing method according to an embodiment of the present invention.
The wafer polishing method of the embodiment comprises the following steps:
referring initially to fig. 2, a wafer 100 is provided, the wafer 100 including a functional side 110 and a backside 120 opposite the functional side 110.
The material of the wafer 100 includes various materials such as silicon, silicon germanium, and the like, and semiconductor devices (not shown) such as CMOS transistors are formed on the surface of the functional surface 110 of the wafer 100 and in the wafer 100. The wafer 100 is a wafer commonly used in the art, and the structure and material of the wafer 100 are not limited in the present invention.
In this embodiment, the back surface of the wafer 100 is subsequently polished to remove a portion of the thickness of the wafer 100 to a predetermined thickness, thereby forming a chip with a specific thickness.
Before the wafer 100 is polished, a protective tape is adhered to the functional surface 110 of the wafer 100 to prevent by-products generated during the polishing process and damage to the wafer 100 caused by the polishing equipment.
Referring next to fig. 3, before a protective tape is attached to the wafer 100, a protective layer 130 is formed on the functional surface of the wafer 100 to protect the semiconductor devices and other structures on the functional surface 110 of the wafer 100.
In this embodiment, the material of the protection layer 130 is an organic silicon material.
The organic silicon material and the wafer 100 made of silicon or silicon germanium and the like have good bonding strength, so that the bonding strength between the subsequent protective tape and the wafer 100 is improved, and the protective effect of the protective tape on the wafer 100 is ensured.
Optionally, in this embodiment, the material of the protection layer 130 is Hexamethyldisiloxane (HMDS)
The hexamethyldisiloxane has a good bonding strength with the wafer 100, and the removal process of hexamethyldisiloxane is mature, and the wafer 100 is not damaged greatly during the removal process of hexamethyldisiloxane, so that the formation and removal processes of the protection layer 130 can be simplified while the safety of the wafer 100 is ensured.
In this embodiment, the forming process of the protection layer 130 includes:
forming an HMDS layer on the functional surface 110 of the wafer 100 by using Chemical Vapor Deposition (CVD) and HMDS Vapor under reduced pressure (in this case, the HMDS layer is an HMDS monomolecular layer and is in a fluid state); and then, annealing the HMDS layer to cure the HMDS layer and improve the stress of the HMDS layer and the bonding strength with the wafer 100.
In other embodiments of the present invention, the HMDS layer forming method may further include forming an HMDS layer on the functional surface 110 of the wafer 100 by using processes such as spraying, dipping, and spin coating, and then performing an annealing process to form the protective layer 130. These simple modifications are all within the scope of the present invention.
Optionally, the annealing process includes controlling the annealing temperature to 180-200 ℃ in an inert gas environment, and continuously annealing for 2-3 hours.
Under the above conditions, the HMDS passivation layer 130 with excellent performance can be formed, and the wafer 100 can be prevented from being damaged due to over-high temperature and over-long time.
And the annealing process is carried out in the inert gas environment, so that the defect that the wafer is oxidized can be effectively inhibited, and the safety of the annealing process is improved.
In this embodiment, the inert gas is nitrogen (N)2) To reduce the process cost. In other embodiments of the present invention, the inert gas further includes a plurality of inert gases such as helium (He), neon (Ne), or argon (Ar). The use of said inert gas does not limit the scope of protection of the present invention.
Referring to fig. 4, a protective tape 140 is coated on the protective layer 130.
The protective tape 140 is a mature technology in the field, and can be various tapes such as a plastic adhesive tape, and the material of the protective tape is not limited in the present invention.
Referring next to fig. 5, the wafer 100 is placed on a grinding apparatus, and the back surface 120 of the wafer 100 is ground to remove a portion of the thickness of the wafer 100.
In the process of polishing the wafer 100, the polishing apparatus includes a chuck 220 for holding the wafer 100, and a polishing pad 210 for pressing and polishing the back surface 120 of the wafer 100.
During the polishing process, the chuck 220 holds the functional surface 110 of the wafer 100 and provides a supporting force to the wafer 100. The protective tape 140 is located on the functional surface of the wafer 100, so as to prevent the chuck 220 from directly contacting the wafer 100, thereby reducing damage to the wafer 100 caused by the chuck 220 directly contacting the wafer 100; in addition, the protective tape 140 covers the surface of the wafer 100, so as to prevent the wafer 100 from being contaminated by-products generated by polishing the wafer 100.
Referring next to fig. 6, after the wafer 100 is polished, the protective tape 140 on the functional surface 110 of the wafer 100 is peeled off.
Compared with fig. 1 and fig. 6, in the embodiment, since the protective layer 130 is formed on the functional surface 110 of the wafer 100, and the protective tape 140 is adhered to the surface of the protective layer 130, when the protective tape 140 is peeled off, the problem that the component 11 (shown in fig. 1) on the functional surface 110 of the wafer 100 is removed together with the protective tape 140 due to the strong adhesiveness of the protective tape 140 can be avoided, and thus the damage to the semiconductor device structure on the wafer 100 is reduced.
After removing the protective tape 140, the protective layer 130 on the functional surface 110 of the wafer 100 is removed.
In this embodiment, a wet cleaning process is used to remove the protection layer 130.
In this embodiment, the material of the protection layer 130 is an organic silicon material, and hexamethyldisiloxane is optionally used as the material of the protection layer 130, and therefore in this embodiment, an organic cleaning agent may be used to remove the protection layer 130.
In this embodiment, the wet cleaning process specifically includes: phenol solution is used as organic cleaning agent. Optionally, the volume ratio concentration of the phenol solution is greater than or equal to 20%, and the cleaning temperature is 70-90 ℃. And continuously performing the wet cleaning process for 3-10 minutes to remove the protective layer 130.
Further optionally, the phenol solution has a concentration of about 20% by volume.
The phenol solution has low corrosion to the wafer made of semiconductor materials such as silicon, so that the damage to the wafer 100 can be effectively reduced in the process of removing the protective layer 130, and the quality of the wafer after the protective layer 130 is removed is ensured.
After removing the protection layer 130, a dicing process of the wafer 100 may be performed, so that the wafer 100 is diced into a plurality of chips. This step is a well-established process in the art and will not be described further herein.
In this embodiment, a protection layer 130 made of a silicone material (optionally, hexamethyldisiloxane) is formed on the functional surface 110 of the wafer 100, and then a protection tape 140 is covered on the protection layer 130, so as to reduce damage to the functional surface 110 of the wafer 100 when the back surface 120 of the wafer 100 is polished.
The protective layer 130 has strong adhesion with the wafer 100, so that the bonding force between the protective tape 140 and the wafer 100 can be ensured; in the step of removing the protective tape 140 after the grinding process, the protective layer 130 prevents the protective tape 140 from directly contacting the functional surface 110 of the wafer 100, so as to avoid the defect that the parts on the surface of the functional surface 110 of the wafer 100 are damaged when the protective tape is removed due to the strong adhesion between the protective tape 140 and the surface of the wafer 100, thereby reducing the structural damage on the functional surface of the wafer 100 and ensuring the performance of the subsequently formed semiconductor device; in addition, the protection layer 130 formed by the organic silicon material is easy to remove, and other damages to the wafer 100 during the process of removing the protection layer 130 are avoided.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (2)
1. A method of polishing a wafer, comprising:
providing a wafer, wherein the wafer comprises a functional surface and a back surface opposite to the functional surface;
forming a protective layer on the functional surface of the wafer, wherein the protective layer is made of hexamethyldisiloxane;
covering a protective adhesive tape on the protective layer;
placing the wafer on a grinding device, and grinding the back surface of the wafer to remove a part of the thickness of the wafer;
removing the protective tape, and then removing the protective layer; the method for removing the protective layer is a wet cleaning process, in the wet cleaning process, a phenol solution is used for removing the protective layer, and the wet cleaning process comprises the following steps: the volume ratio concentration of the phenol solution is more than or equal to 20%, the cleaning temperature is 70-90 ℃, and the cleaning is continued for 3-10 minutes;
the step of forming the protective layer includes: forming a hexamethyldisiloxane layer on the functional surface of the wafer by adopting chemical vapor deposition, and then carrying out an annealing process to form the protective layer;
the annealing process comprises the following steps: and under the inert gas environment, controlling the annealing temperature to be 180-200 ℃, and continuously annealing for 2-3 hours.
2. The wafer polishing method as recited in claim 1, wherein the inert gas is nitrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410720427.9A CN105643431B (en) | 2014-12-02 | 2014-12-02 | Wafer grinding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410720427.9A CN105643431B (en) | 2014-12-02 | 2014-12-02 | Wafer grinding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105643431A CN105643431A (en) | 2016-06-08 |
| CN105643431B true CN105643431B (en) | 2020-06-09 |
Family
ID=56481156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410720427.9A Active CN105643431B (en) | 2014-12-02 | 2014-12-02 | Wafer grinding method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105643431B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172498A (en) * | 2017-11-23 | 2018-06-15 | 南昌易美光电科技有限公司 | cleaning method based on chip thinning |
| CN108417480A (en) * | 2018-03-16 | 2018-08-17 | 成都海威华芯科技有限公司 | A kind of reduction grinding wafer front damage method |
| CN114161258B (en) * | 2021-12-10 | 2024-08-27 | 中国电子科技集团公司第四十六研究所 | Edge grinding method for preventing gallium oxide wafer from cleavage |
| CN115319639A (en) * | 2022-09-22 | 2022-11-11 | 西安奕斯伟材料科技有限公司 | Grinding device, grinding method and silicon wafer |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0642472B2 (en) * | 1983-10-15 | 1994-06-01 | ロ−ム株式会社 | Method for manufacturing semiconductor device |
| JPS63160342A (en) * | 1986-12-24 | 1988-07-04 | Mitsubishi Electric Corp | Removal of protective film and protective tape |
| US6245677B1 (en) * | 1999-07-28 | 2001-06-12 | Noor Haq | Backside chemical etching and polishing |
| CN101202201A (en) * | 2006-12-13 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing process of thinning crystal circle for large tin ball |
| CN101367192B (en) * | 2007-08-17 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Wafer reverse side grinding method |
| CN202572118U (en) * | 2012-04-24 | 2012-12-05 | 正恩科技有限公司 | Thinning structure of LED wafer |
-
2014
- 2014-12-02 CN CN201410720427.9A patent/CN105643431B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN105643431A (en) | 2016-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10256148B2 (en) | Method of processing wafer | |
| JP6197422B2 (en) | Manufacturing method of semiconductor device and wafer with supporting substrate | |
| CN105643431B (en) | Wafer grinding method | |
| JP2013008915A (en) | Substrate processing method and substrate processing apparatus | |
| TW201130022A (en) | Methods of fabricating stacked device and handling device wafer | |
| JP2013522896A (en) | Semiconductor on insulator type substrate finishing method | |
| WO2011079170A3 (en) | Automated thermal slide debonder | |
| CN109786325B (en) | Method for manufacturing small diameter wafer | |
| WO2009032536A3 (en) | Method for manufacturing a semiconductor die and a semiconductor device comprising the semiconductor die obtained thereby | |
| US20140113452A1 (en) | Wafer edge trimming method | |
| TWI631626B (en) | Handler wafer removal | |
| US8574398B2 (en) | Apparatus and method for detaping an adhesive layer from the surface of ultra thin wafers | |
| CN109712926B (en) | Method for manufacturing semiconductor device | |
| JPH08148452A (en) | Substrate surface protecting tape and substrate backside grinding method | |
| JPH11145089A (en) | Method for grinding backside of semiconductor wafer and protective tape used therefor | |
| JP7551787B2 (en) | Wafer back grinding method and electronic device manufacturing method | |
| JP2019009198A (en) | Wafer processing method | |
| TWI773838B (en) | Grinding method of workpiece | |
| TWI592982B (en) | Method of manufacturing semiconductor device | |
| TWI668755B (en) | Method for polishing semiconductor wafer | |
| JP2014082380A (en) | Peeling method of surface protective tape | |
| JP2013069946A (en) | Support substrate, manufacturing method of support substrate, and manufacturing method of semiconductor device | |
| JP2008218919A (en) | Method for protecting surface of semiconductor wafer and structure for surface protection | |
| JP2012015231A (en) | Tape sticking method | |
| US9064863B2 (en) | Method for directly adhering two plates together, including a step of forming a temporary protective nitrogen |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |