CN105632956A - Method and system for evaluating surface appearance of chip after chemical mechanical polishing - Google Patents
Method and system for evaluating surface appearance of chip after chemical mechanical polishing Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 142
- 238000005498 polishing Methods 0.000 title claims abstract description 44
- 239000000126 substance Substances 0.000 title abstract description 5
- 238000012876 topography Methods 0.000 claims abstract description 96
- 239000007788 liquid Substances 0.000 claims description 67
- 238000009826 distribution Methods 0.000 claims description 46
- 238000011156 evaluation Methods 0.000 claims description 19
- 238000004364 calculation method Methods 0.000 claims description 6
- 239000000284 extract Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000012530 fluid Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 25
- 239000002184 metal Substances 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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Abstract
The invention discloses a method and a system for evaluating the surface appearance of a chip after chemical mechanical polishing, and belongs to the technical field of integrated circuit manufacturing. The method for evaluating the surface appearance of the chip after chemical mechanical polishing comprises the following steps: obtaining the surface appearance parameters of the chip in the last process stage and the selection ratio of the grinding fluid; acquiring the technological parameters of the current technological stage and the selection ratio of the grinding fluid; dividing a current surface layout of a chip into a plurality of continuous panes, and extracting layout characteristic parameters of each pane respectively; judging whether the selection ratio of the grinding fluid is changed, if so, calculating the surface topography parameter of the chip in the current process stage according to the surface topography parameter, the process parameter, the layout characteristic parameter and the selection ratio of the grinding fluid in the current process stage; and evaluating the surface appearance of the chip according to the surface appearance parameters of the current process stage. The method for evaluating the surface appearance of the chip after the chemical mechanical polishing can accurately evaluate the surface appearance of the chip.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly to chip surface morphology evaluating method and system after a kind of chemically mechanical polishing.
Background technology
At integrated circuit (IntegratedCircuit, be called for short IC) manufacture process in, metal, electrolyte and other materials are used such as physical vapour deposition (PVD), chemical vapour deposition (CVD) and are applied to the surface of silicon chip in interior various methods, to form the metal structure of layering. Integrated circuit generally includes multi-layer metal structure, is connected with multiple metal filled through holes again, can be coupled together by metal structure so that integrated circuit has significantly high complexity and current densities between each layer of circuit between every layer of metal. Therefore, in ic manufacturing process, a committed step is in that to form metal structure.
Owing to layer on surface of metal flatness can affect the stress distribution of the depth of focus required in photoetching and interconnection structure. In order to obtain flatness necessary to manufacture multilayer circuit, it is common to use CMP process makes the pattern of metallic dielectric layer planarize. Wherein, chemically mechanical polishing (ChemicalMechanicalPolishing, it being called for short CMP) abrasive action of chemical attack effect and ultramicron that is made by polishing fluid forms bright and clean, smooth surface on the dielectric surface being ground, and is super large-scale integration stage best material global planarizartion method.
In CMP process, owing to different lapping liquids is different to the clearance of different materials, lapping liquid selects the change of ratio to make chip surface in CMP process and after CMP not completely flat, but there is topology and rise and fall. In order to improve chip production yield, reduce production cost, it is necessary to the pattern of chip surface after evaluation and test CMP in advance, thus assessing whether this pattern can produce impact to subsequent optical carving technology etc.
As it is shown in figure 1, be the flow chart of chip surface morphology evaluating method after chemically mechanical polishing of the prior art, specifically include following steps:
Step 101: obtain the chip surface topography parameters at a upper operation stage;
Step 102: obtain the technological parameter in current process stage;
Step 103: the Current surface domain of chip is divided into multiple continuous pane, extracts the domain characteristic parameter of each pane respectively;
Step 104: according to the surface topography parameters of a upper operation stage, technological parameter and domain characteristic parameter, computing chip is at the surface topography parameters in current process stage;
Step 105: the surface topography of chip is evaluated and tested according to the surface topography parameters in current process stage.
Owing to CMP process is more complicated, specifically can be divided into multiple operation stage, need to select different lapping liquids to be ground polishing in the different process stage, and the clearance of different materials is differed by different lapping liquids, so would potentially result in the selection of lapping liquid ratio and change. Above-mentioned evaluating method is when the selection ratio of lapping liquid remains unchanged, chip surface morphology after chemically mechanical polishing can be carried out accurate assessment, but select ratio when changing at lapping liquid, the surface topography that will cause chip changes, thus causing accurately the surface topography of chip being evaluated and tested.
Summary of the invention
Embodiments provide chip surface morphology evaluating method and system after a kind of chemically mechanical polishing, it is possible to accurately chip surface morphology is evaluated and tested.
The technical scheme that the embodiment of the present invention provides is as follows:
On the one hand, it is provided that chip surface morphology evaluating method after a kind of chemically mechanical polishing, including:
Obtain the selection ratio of the chip surface topography parameters at a upper operation stage and lapping liquid;
Obtain the technological parameter in current process stage and the selection ratio of lapping liquid;
The Current surface domain of chip is divided into multiple continuous pane, extracts the domain characteristic parameter of each described pane respectively;
Judge that whether the selection of lapping liquid than changes, if, then the selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, calculates the described chip surface topography parameters in the current process stage;
The surface topography of described chip is evaluated and tested by the surface topography parameters according to the described current process stage.
Preferably, the described selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, calculate the described chip surface topography parameters in the current process stage, including:
Selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, the pressure distribution of computing chip;
Clearance according to described calculation of pressure distribution chip;
The surface topography parameters in current process stage is calculated according to described clearance.
Preferably, described method also includes: judge whether the current process stage arrives grinding endpoint, if it is, terminate surface topography evaluation and test.
Preferably, if the current process stage does not arrive grinding endpoint, then the height Regional Distribution of Registered according to the surface topography parameters computing chip surface in described current process stage.
Preferably, described method also includes:
Judge whether the height Regional Distribution of Registered of a upper operation stage and the chip surface in current process stage changes;
If it is, the relatively high district in described height Regional Distribution of Registered and relatively low district are swapped mutually.
On the other hand, it is provided that chip surface morphology evaluating system after a kind of chemically mechanical polishing, including:
First acquisition module, for obtaining the selection ratio of the chip surface topography parameters at a upper operation stage and lapping liquid;
Second acquisition module, for obtaining the technological parameter in current process stage and the selection ratio of lapping liquid;
Domain divides module, for the Current surface domain of chip is divided into multiple continuous pane;
Characteristic extracting module, for extracting the domain characteristic parameter of each described pane respectively;
First judge module, for judging that whether the selection of lapping liquid than changes;
Computing module, for judging to select ratio after changing at described first judge module, selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage;
Evaluation and test module, evaluates and tests the surface topography of described chip for the surface topography parameters according to the described current process stage.
Preferably, described computing module includes:
First computing unit, for the selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, the pressure distribution of computing chip;
Second computing unit, for the clearance according to described calculation of pressure distribution chip;
3rd computing unit, for calculating the surface topography parameters in current process stage according to described clearance.
Preferably, described system also includes:
Second judge module, is used for judging whether the current process stage arrives grinding endpoint;
Described evaluation and test module, is additionally operable to, after described second judge module judges that the described current process stage arrives grinding endpoint, terminate surface topography evaluation and test.
Preferably, described computing module, it is additionally operable to the height Regional Distribution of Registered after described second judge module judges that the current process stage does not arrive grinding endpoint, according to described surface topography parameters computing chip surface.
Preferably, described system also includes:
3rd judge module, for judging whether the height Regional Distribution of Registered of a upper operation stage and the chip surface in current process stage changes;
Switching Module, after on judging at described 3rd judge module, the height Regional Distribution of Registered of an operation stage and the chip surface in current process stage changes, swaps mutually by the relatively high district in described height Regional Distribution of Registered and relatively low district.
Chip surface morphology evaluating method and system after the chemically mechanical polishing that the embodiment of the present invention provides, select ratio when changing at a upper operation stage and the lapping liquid in current process stage, selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage, then surface topography evaluation and test is carried out, take into full account that lapping liquid selects the impact of comparison chip surface morphology, it is possible to the surface topography of chip is accurately evaluated and tested.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment will be briefly described below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of chip surface morphology evaluating method after chemically mechanical polishing of the prior art;
Fig. 2 is the flow chart of chip surface morphology evaluating method after a kind of chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 3 is the flow chart of chip surface morphology evaluating method after the second chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 4 is the flow chart of chip surface morphology evaluating method after the third chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 5 is the flow chart of chip surface morphology evaluating method after the 4th kind of chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 6 is the structural representation of chip surface morphology evaluating system after a kind of chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 7 is the structural representation of chip surface morphology evaluating system after the second chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 8 is the structural representation of chip surface morphology evaluating system after the third chemically mechanical polishing that the embodiment of the present invention provides;
Fig. 9 is the structural representation of chip surface morphology evaluating system after the 4th kind of chemically mechanical polishing that the embodiment of the present invention provides.
Detailed description of the invention
In order to make those skilled in the art be more fully understood that the scheme of the embodiment of the present invention, below in conjunction with drawings and embodiments, the embodiment of the present invention is described in further detail.
Chip surface morphology evaluating method after a kind of chemically mechanical polishing of embodiment of the present invention offer, as in figure 2 it is shown, comprise the following steps:
Step 201: obtain the selection ratio of the chip surface topography parameters at a upper operation stage and lapping liquid.
Owing to CMP process is essentially by selected lapping liquid, the process under certain process conditions, the material of chip surface is ground, removed. Wherein, the selection ratio of lapping liquid is a key parameter, and the ratio that selects of materials A and material B is the materials A ratio to the clearance of material B when same process by lapping liquid. If selecting ratio more than 1, then after CMP, chip surface materials A is depression, and material B protrudes; Whereas if select ratio less than 1, then after CMP, chip surface materials A is to protrude, and material B is depression. In modern CMP, often adopt the lapping liquid of different choice ratio to reach required process goal at different operation stages.
Step 202: obtain the technological parameter in current process stage and the selection ratio of lapping liquid.
CMP process is complex, is generally divided into multiple stage such as P1, P2, P3, and wherein, the output result of a upper operation stage is as the input of next operation stage. Different according to the material of required removal in each stage, it is therefore possible to use the consumable goodss such as different grinding pad, lapping liquid, adopt the technological parameters such as different pressure, rotating speed, to reach different process goals simultaneously.
Step 203: the Current surface domain of chip is divided into multiple continuous pane, extracts the domain characteristic parameter of each pane respectively.
Wherein, domain characteristic parameter is the relevant parameter characterizing chip surface domain structure, it is possible to includes equivalence live width, equivalent separation and density etc., specifically needs to extract which domain characteristic parameter, it is possible to select according to actual needs. Above-mentioned steps 201, step 202 and step 203 are not limited to above-mentioned execution sequence, and concrete execution sequence can arbitrarily be adjusted as required, and the embodiment of the present invention is not specifically limited.
Step 204: judge that whether the selection of lapping liquid than changes, if, the then selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage.
Wherein, lapping liquid select than change may include that a upper operation stage lapping liquid select than more than 1 the selection ratio of the lapping liquid of this operation stage less than 1, and a upper operation stage lapping liquid select than less than 1 the selection ratio of the lapping liquid of this operation stage more than 1 two kinds of situations, namely, the selection of the lapping liquid of adjacent two operation stages is than not being entirely more than 1 or entirely less than 1, then it is assumed that the selection ratio of lapping liquid changes.
When the selection ratio of lapping liquid changes, it will the surface topography of chip is produced impact, therefore, in calculating the process of surface topography parameters in current process stage, it is necessary to the selection of lapping liquid is used for input factor and takes in. Wherein, the method for concrete gauging surface structural parameters can adopt method of the prior art, and those skilled in the art are easily known, repeat no more herein.
Step 205: the surface topography of chip is evaluated and tested according to the surface topography parameters in current process stage.
After chemically mechanical polishing, the surface topography of chip can be characterized by surface topography parameters, and be often used in the characteristic parameter describing surface topography and include metal dish and erosion medium resistance etc. Wherein, metal dish has been normally defined the difference of graphics field thickness of dielectric layers and metal thickness; And erosion medium resistance is normally defined without graphics field thickness of dielectric layers and the difference having graphics field thickness of dielectric layers. Usual variable is relevant to the live width of figure, spacing etc. for metal dish and erosion medium resistance, shows very big systematicness and regularity. Surface topography after CMP rises and falls as metal dish and erosion medium resistance can affect the depth of focus of subsequent optical carving technology, also can affect the electrical characteristics such as resistance of interconnection line simultaneously, thus affecting Interconnect Delay, yield and performance to chip impact simultaneously, by surface topography parameters, surface topography is evaluated and tested, according to actual needs in design and processes process, it is possible to control this surface topography within the acceptable range.
As shown in Figure 3, for the selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip, at the flow chart of the surface topography parameters in current process stage, specifically may comprise steps of:
Step 301: the selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, the pressure distribution of computing chip.
Step 302: the clearance according to calculation of pressure distribution chip.
Step 303: calculate the surface topography parameters in current process stage according to clearance.
Owing to pressure distribution situation is relevant to many factors such as the surface topography of chip, process conditions, and material remove rate also can be produced impact by pressure distribution, select ratio after calculating pressure distribution by the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and lapping liquid, pressure distribution is multiplied by particular factor and can calculate clearance, wherein, particular factor can be obtained by test data fitting. Owing to the kind of lapping liquid is specific and it is specific to remove material, according to clearance, it is possible to calculate surface topography parameters.
As shown in Figure 4, after above-mentioned chemically mechanical polishing, chip surface morphology evaluating method can include step 206 further: judges whether the current process stage arrives grinding endpoint; If it is determined that the current process stage has arrived at grinding endpoint, then terminate surface topography evaluation and test; If it is determined that the current process stage does not arrive grinding endpoint, then proceed to step 207: the height Regional Distribution of Registered according to the surface topography parameters computing chip surface in current process stage.
The surface topography of chip can be evaluated and tested by CMP process in real time, for specific operation stage, after arriving grinding endpoint, surface topography evaluation and test will be terminated. Wherein it is possible to judge whether to arrive grinding endpoint by grinding duration, grinding thickness etc., specifically can the standard set by reality judge accordingly.
As it is shown in figure 5, after calculating the height Regional Distribution of Registered obtaining chip surface, after above-mentioned chemically mechanical polishing, chip surface morphology evaluating method can also comprise the following steps:
Step 208: judge whether the height Regional Distribution of Registered of a upper operation stage and the chip surface in current process stage changes.
If the selection ratio of lapping liquid changes, then it is likely to change the height Regional Distribution of Registered making chip surface, for the up-and-down chip surface of height, height Regional Distribution of Registered can pass through relatively high district and relatively low district is characterized, height Regional Distribution of Registered changes the relatively high district and relatively low district that refer to an operation stage chip surface, being changed to the relatively low district of current process stage chip surface and relatively high district respectively, namely relatively high district and relatively low district exchange.
Step 209: if it is, the relatively high district in height Regional Distribution of Registered and relatively low district are swapped mutually.
If through judging that the height Regional Distribution of Registered finding chip surface changes, then illustrate to be selected the change of ratio by lapping liquid, the clearance causing different materials changes, and then causes that starting relatively high district originally from certain particular moment has been changed to relatively low district through grinding. Such as: in the P1 stage, the clearance of the materials A clearance more than material B, then after the P1 stage, materials A is depression, and material B protrudes; But, in the P2 stage, the clearance of the materials A clearance less than material B, then at certain time point in P2 stage, materials A will be transferred to protrusion by depression, and material B will be transferred to depression by protrusion. That is, when selecting ratio when changing, exchange causing between originally higher region and originally relatively low region. After height Regional Distribution of Registered changes, upper zone becomes lower region originally, and lower region becomes upper zone originally, correspondingly needs relevant parameter is adjusted, for instance, the density of upper zone is �� originallyB, the density of lower region is ��A, and after exchanging, the density of upper zone is ��A, the density of lower region is ��B, wherein, ��A=1-��B��
Owing to the height Regional Distribution of Registered after exchange can reflect the real surface topography of chip, therefore, using the height Regional Distribution of Registered after exchange as the surface topography parameters input calculating the current process stage, thus ensureing the accuracy of evaluation result. Additionally, by the input that the height Regional Distribution of Registered after exchange is fed back to next operation stage such that it is able to ensure that the chip surface morphology that next operation stage obtains is more nearly practical situation, and then ensure the accuracy of follow-up evaluation result.
Chip surface morphology evaluating method after the chemically mechanical polishing that the embodiment of the present invention provides, select ratio when changing at a upper operation stage and the lapping liquid in current process stage, selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage, then surface topography evaluation and test is carried out, take into full account that lapping liquid selects the impact of comparison chip surface morphology, it is possible to the surface topography of chip is accurately evaluated and tested.
Correspondingly, the embodiment of the present invention additionally provides chip surface morphology evaluating system after a kind of chemically mechanical polishing, and as described in Figure 6, after this chemically mechanical polishing, chip surface morphology evaluating system may include that
First acquisition module 401, for obtaining the selection ratio of the chip surface topography parameters at a upper operation stage and lapping liquid;
Second acquisition module 402, for obtaining the technological parameter in current process stage and the selection ratio of lapping liquid;
Domain divides module 403, for the Current surface domain of chip is divided into multiple continuous pane;
Characteristic extracting module 404, for extracting the domain characteristic parameter of each pane respectively;
First judge module 405, for judging that whether the selection of lapping liquid than changes;
Computing module 406, for judging to select ratio after changing at the first judge module 405, selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage;
Evaluation and test module 407, evaluates and tests the surface topography of chip for the surface topography parameters according to the current process stage.
As it is shown in fig. 7, computing module 406 may include that
First computing unit 501, for the selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, the pressure distribution of computing chip;
Second computing unit 502, for the clearance according to calculation of pressure distribution chip
3rd computing unit 503, for calculating the surface topography parameters in current process stage according to clearance.
As shown in Figure 8, after above-mentioned chemically mechanical polishing, chip surface morphology evaluating system can also include further:
Second judge module 408, is used for judging whether the current process stage arrives grinding endpoint;
Evaluation and test module 407, is additionally operable to, after the second judge module 408 judges that the current process stage arrives grinding endpoint, terminate surface topography evaluation and test.
As it is shown in figure 9, chip surface morphology evaluating system can also include further after above-mentioned chemically mechanical polishing:
3rd judge module 409, for judging whether the height Regional Distribution of Registered of a upper operation stage and the chip surface in current process stage changes;
Switching Module 410, after on judging at the 3rd judge module 409, the height Regional Distribution of Registered of an operation stage and the chip surface in current process stage changes, swaps mutually by the relatively high district in height Regional Distribution of Registered and relatively low district.
Chip surface morphology evaluating system after the chemically mechanical polishing that the embodiment of the present invention provides, select ratio when changing at a upper operation stage and the lapping liquid in current process stage, selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage, then surface topography evaluation and test is carried out, take into full account that lapping liquid selects the impact of comparison chip surface morphology, it is possible to the surface topography of chip is accurately evaluated and tested.
Each embodiment in this specification all adopts the mode gone forward one by one to describe, between each embodiment identical similar part mutually referring to, what each embodiment stressed is the difference with other embodiments. Especially for system embodiment, owing to it is substantially similar to embodiment of the method, so describing fairly simple, relevant part illustrates referring to the part of embodiment of the method. System embodiment described above is merely schematic, the wherein said unit illustrated as separating component can be or may not be physically separate, the parts shown as unit can be or may not be physical location, namely may be located at a place, or can also be distributed on multiple NE. Some or all of module therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme. Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (10)
1. chip surface morphology evaluating method after a chemically mechanical polishing, it is characterised in that including:
Obtain the selection ratio of the chip surface topography parameters at a upper operation stage and lapping liquid;
Obtain the technological parameter in current process stage and the selection ratio of lapping liquid;
The Current surface domain of chip is divided into multiple continuous pane, extracts the domain characteristic parameter of each described pane respectively;
Judge that whether the selection of lapping liquid than changes, if, then the selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, calculates the described chip surface topography parameters in the current process stage;
The surface topography of described chip is evaluated and tested by the surface topography parameters according to the described current process stage.
2. chip surface morphology evaluating method after chemically mechanical polishing according to claim 1, it is characterized in that, the described selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, calculate the described chip surface topography parameters in the current process stage, including:
Selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, the pressure distribution of computing chip;
Clearance according to described calculation of pressure distribution chip;
The surface topography parameters in current process stage is calculated according to described clearance.
3. chip surface morphology evaluating method after the chemically mechanical polishing according to any one of claim 1 or 2, it is characterised in that described method also includes: judge whether the current process stage arrives grinding endpoint, if it is, terminate surface topography evaluation and test.
4. chip surface morphology evaluating method after chemically mechanical polishing according to claim 3, it is characterized in that: if the current process stage do not arrive grinding endpoint, then the height Regional Distribution of Registered according to the surface topography parameters computing chip surface in described current process stage.
5. chip surface morphology evaluating method after chemically mechanical polishing according to claim 4, it is characterised in that described method also includes:
Judge whether the height Regional Distribution of Registered of a upper operation stage and the chip surface in current process stage changes;
If it is, the relatively high district in described height Regional Distribution of Registered and relatively low district are swapped mutually.
6. chip surface morphology evaluating system after a chemically mechanical polishing, it is characterised in that including:
First acquisition module, for obtaining the selection ratio of the chip surface topography parameters at a upper operation stage and lapping liquid;
Second acquisition module, for obtaining the technological parameter in current process stage and the selection ratio of lapping liquid;
Domain divides module, for the Current surface domain of chip is divided into multiple continuous pane;
Characteristic extracting module, for extracting the domain characteristic parameter of each described pane respectively;
First judge module, for judging that whether the selection of lapping liquid than changes;
Computing module, for judging to select ratio after changing at described first judge module, selection ratio according to the surface topography parameters of a upper operation stage, technological parameter, domain characteristic parameter and current process stage lapping liquid, computing chip is at the surface topography parameters in current process stage;
Evaluation and test module, evaluates and tests the surface topography of described chip for the surface topography parameters according to the described current process stage.
7. chip surface morphology evaluating system after chemically mechanical polishing according to claim 6, it is characterised in that described computing module includes:
First computing unit, for the selection ratio according to the surface topography parameters of a described upper operation stage, described technological parameter, described domain characteristic parameter and described current process stage lapping liquid, the pressure distribution of computing chip;
Second computing unit, for the clearance according to described calculation of pressure distribution chip;
3rd computing unit, for calculating the surface topography parameters in current process stage according to described clearance.
8. chip surface morphology evaluating system after the chemically mechanical polishing according to any one of claim 6 or 7, it is characterised in that described system also includes:
Second judge module, is used for judging whether the current process stage arrives grinding endpoint;
Described evaluation and test module, is additionally operable to, after described second judge module judges that the described current process stage arrives grinding endpoint, terminate surface topography evaluation and test.
9. chip surface morphology evaluating system after chemically mechanical polishing according to claim 8, it is characterised in that:
Described computing module, is additionally operable to the height Regional Distribution of Registered after described second judge module judges that the current process stage does not arrive grinding endpoint, according to described surface topography parameters computing chip surface.
10. chip surface morphology evaluating system after chemically mechanical polishing according to claim 9, it is characterised in that described system also includes:
3rd judge module, for judging whether the height Regional Distribution of Registered of a upper operation stage and the chip surface in current process stage changes;
Switching Module, after on judging at described 3rd judge module, the height Regional Distribution of Registered of an operation stage and the chip surface in current process stage changes, swaps mutually by the relatively high district in described height Regional Distribution of Registered and relatively low district.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111356897A (en) * | 2020-02-24 | 2020-06-30 | 长江存储科技有限责任公司 | System and method for semiconductor chip surface topography metrology |
| US11243067B2 (en) | 2020-02-24 | 2022-02-08 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for semiconductor chip surface topography metrology |
| US11454491B2 (en) | 2020-02-24 | 2022-09-27 | Yangtze Memory Technologies Co., Ltd. | Systems having light source with extended spectrum for semiconductor chip surface topography metrology |
| US11562919B2 (en) | 2020-02-24 | 2023-01-24 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for semiconductor chip surface topography metrology |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090089732A1 (en) * | 2007-09-28 | 2009-04-02 | Synopsys, Inc. | Method and apparatus for performing dummy-fill by using a set of dummy-fill cells |
| CN103020384A (en) * | 2012-12-27 | 2013-04-03 | 中国科学院微电子研究所 | Aluminum gate CMP chemical reaction kinetics simulation and layout design optimization method |
| CN103123922A (en) * | 2012-12-21 | 2013-05-29 | 中国科学院微电子研究所 | Method and system for determining surface morphology of aluminum metal gate chip |
| CN103226627A (en) * | 2013-03-21 | 2013-07-31 | 中国科学院微电子研究所 | Method and device for simulating chip surface morphology |
| CN103544331A (en) * | 2012-07-16 | 2014-01-29 | 复旦大学 | Dummy comprehensive optimization method based on CMP simulation model |
-
2014
- 2014-11-07 CN CN201410643976.0A patent/CN105632956B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090089732A1 (en) * | 2007-09-28 | 2009-04-02 | Synopsys, Inc. | Method and apparatus for performing dummy-fill by using a set of dummy-fill cells |
| CN103544331A (en) * | 2012-07-16 | 2014-01-29 | 复旦大学 | Dummy comprehensive optimization method based on CMP simulation model |
| CN103123922A (en) * | 2012-12-21 | 2013-05-29 | 中国科学院微电子研究所 | Method and system for determining surface morphology of aluminum metal gate chip |
| CN103020384A (en) * | 2012-12-27 | 2013-04-03 | 中国科学院微电子研究所 | Aluminum gate CMP chemical reaction kinetics simulation and layout design optimization method |
| CN103226627A (en) * | 2013-03-21 | 2013-07-31 | 中国科学院微电子研究所 | Method and device for simulating chip surface morphology |
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|---|---|---|---|---|
| CN111356897A (en) * | 2020-02-24 | 2020-06-30 | 长江存储科技有限责任公司 | System and method for semiconductor chip surface topography metrology |
| US11243067B2 (en) | 2020-02-24 | 2022-02-08 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for semiconductor chip surface topography metrology |
| US11448499B2 (en) | 2020-02-24 | 2022-09-20 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for semiconductor chip surface topography metrology |
| US11454491B2 (en) | 2020-02-24 | 2022-09-27 | Yangtze Memory Technologies Co., Ltd. | Systems having light source with extended spectrum for semiconductor chip surface topography metrology |
| US11562919B2 (en) | 2020-02-24 | 2023-01-24 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for semiconductor chip surface topography metrology |
| US11796307B2 (en) | 2020-02-24 | 2023-10-24 | Yangtze Memory Technologies Co., Ltd. | Systems and methods for semiconductor chip surface topography metrology |
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