CN105630458B - The Forecasting Methodology of average throughput under a kind of out-of order processor stable state based on artificial neural network - Google Patents
The Forecasting Methodology of average throughput under a kind of out-of order processor stable state based on artificial neural network Download PDFInfo
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Abstract
The invention discloses a kind of Forecasting Methodology of average throughput under out-of order processor stable state based on artificial neural network, the micro-architecture independent parameter of object phase is obtained by the fully simulated environment of instruction set simulator, SOM and Kmeans algorithms are recycled to extract the characteristic point in input data, finally by BP neural network fitting micro-architecture independent parameter and the relation of stable state average throughput, the higher model of precision is trained.After the completion of model training, the micro-architecture irrelevant information of program is obtained by simulator, is imported into the neutral net trained, you can rapidly and accurately predict actual stable state average throughput value.The present invention uses artificial neural network, drastically increases the precision of prediction and speed of average throughput under out-of order processor stable state.
Description
Technical field
The present invention relates to a kind of Forecasting Methodology of average throughput under out-of order processor stable state based on artificial neural network,
Belong to Hardware/Software Co-design Technology.
Background technology
Framework is assessed before silicon based on hardware behavior modeling and design space exploration can provide chip design guidance opinion, is dropped
The low chip design iteration cycle.In the case where par-ticular processor and designated program are run, being averaged under out-of order processor stable state
Throughput is characterized in the case of not having deletion events, the limit of processor performance, while is also reflected to a certain extent
Whether the design of application program is adapted to hardware.Meanwhile the average throughput under out-of order processor stable state contribute to it is follow-up
The analysis modeling of out-of order processor overall performance.
At present is lived through to the understanding of average throughput under out-of order processor stable state two stages, first stage is direct
Assume the width of front end instruction issue level as the average throughput under out-of order processor stable state, this method：When out of order processing
When device does not have deletion events, the instruction with front end instruction issue level width equivalent can be handled in each clock of processor.
This method, which have ignored, to be examined factors such as instruction dependence, functional unit value volume and range of product, instruction delay, serial command distributions
Consider, be a kind of hypothesis of very coarseness；Second stage thinks that average throughput is sent out with front end instruction under out-of order processor stable state
It is related to penetrate level width, critical path depth, functional unit number and type, and it is maximum to think that average throughput is limited only in influence
A factor.This method is compared to first method, it is contemplated that and it is more to influence the factor of average throughput, but be confined to single
Influence factor, without it is contemplated that coupled relation between each key element.
Average throughput under out-of order processor stable state refers in the case where not having deletion events, when average each
The number of instructions of clock transmitting.In parallel instructions degree under conditions of high and processor back-end function unit abundance, averagely gulped down under stable state
The width D that rate is equal to front end instruction issue level is told, the parameter is also average throughput ideally.But exist when between instruction
During stronger dependence, such as, the implementing result that the data required for the execution of latter bar instruction are instructed by previous bar provides,
The number of instructions that then average each clock can be launched is reduced, and as dependency chain is longer, more, and average throughput is just under stable state
Can be lower.When processor back-end function unit number and inadequate species, even if instruction stream has higher degree of parallelism in itself, firmly
Part unit is limited to number, species and the influence for performing delay, can not also ensure highest average throughput D.It is worth in addition
It is noted that serial command DSB, DMB, ISB for being introduced in Android system, also limit average throughput under stable state, serially refer to
Instruction or data access of the order requirement before the instruction must be fully completed, and can just continue executing with follow-up instruction, then
Even in instruction stream degree of parallelism itself under conditions of high and processor back-end function unit abundance, the distribution of serial command is also very big
Average throughput under stable state is have impact in degree.
It is lastly noted that it is not simple between the size of average throughput and each influence factor under stable state
Single interactively, i.e., coupling effect between each factor also in the case where affecting stable state average throughput size, this is undoubtedly
Increase the difficulty of mechanistic point analysis.Simultaneously because fully simulated time overhead is excessive, so the present invention carries regarding to the issue above
A kind of Forecasting Methodology of average throughput under out-of order processor stable state based on artificial neural network is gone out, for rapidly and accurately
Predict average throughput under stable state
The content of the invention
Goal of the invention：In order to overcome the deficiencies in the prior art, the present invention provides one kind and is based on artificial neural network
Out-of order processor stable state under average throughput Forecasting Methodology, unrest can rapidly and accurately be predicted according to micro-architecture independent parameter
Average throughput under sequence processor stable state, and Forecasting Methodology precision is high, speed is fast.
Technical scheme：To achieve the above object, the technical solution adopted by the present invention is：
The Forecasting Methodology of average throughput under a kind of out-of order processor stable state based on artificial neural network, including following step
Suddenly：
(1) discontinuous point that the time point that thread number switches when instruction set simulator is emulated is split as fragment, so that will
Whole target program is divided into some fragments, and all fragments are divided and sorted by thread number, each fragment is counted and includes
Clock number, delete clock number be less than threshold value (such as 1000) fragment；
(2) to the fragment remained in subject thread, related micro- frame of each fragment of instruction set simulator acquisition is utilized
Structure independent parameter, the micro-architecture independent parameter includes dynamic instruction flow mixing ratio, and (floating-point, fixed point, SIMD, Load/Store refer to
Number of order etc.), critical path depth (for the difference of processor rear end design, count the distribution of corresponding critical path depth,
This patent statistics critical path depth be 1 to 40 number distribution), serialized instructions, front end emission command rate (for processing
The difference of device Front-end Design, count corresponding firing order number distribution, the number that this patent statistics firing order number is 0 to 4
Mesh be distributed) and subject thread operation total time；
(3) first, requirement (dynamic instruction flow mixing ratio, critical path depth of the BP neural network to input data are considered
Distribution, serialized instructions), the related micro-architecture independent parameter of each fragment is pre-processed, forms the correlation of homologous segment
Micro-architecture independent parameter vector；Then, each related micro-architecture independent parameter vector is dropped by principal component analysis (PCA)
Dimension, denoising, form the MicaData data sets (micro-structural extraneous data collection) of homologous segment.
(4) to the fragment remained in subject thread, first, by SOM (SelfOrganizingFeatureMaps,
Self-organized mapping network) all MicaData data sets are divided into N number of major class (such as 200 major classes)；Then, k- averages are passed through
N-th of major class is divided into M by cluster (Kmeans clusters) algorithmn(number of general each group is segment inside major class to individual group
Number 15%), 1≤n≤N；Choose characteristic point of the point closest from central point in each group as the group；Step
(3) and step (4) processing so that reduce BP neural network model training on the premise of initial data main information is retained
Input data and reduce the time needed for BP neural network model training；
(5) to the fragment remained in subject thread, the input using all characteristic points as BP neural network, BP nerves
The output of network is the stable state average throughput of subject thread, and input and output to BP neural network are fitted, and pass through tune
The iterations and training precision of BP neural network are saved, training obtains the BP neural network model of subject thread；
(6) after the completion of BP neural network model training, micro- frame of other threads to be predicted is obtained by instruction set simulator
Structure independent parameter information, it imported into the BP neural network model trained, you can rapidly and accurately predict that actual stable state is averaged
Throughput value；Other threads to be predicted include the thread in target program, or the thread in other applications.
Specifically, in the step (5), BP neural network has three hidden layers, and the first hidden layer uses 30 neurons,
Second hidden layer uses 15 neurons, and the 3rd hidden layer uses 15 neurons；Between input layer and the first hidden layer, first
Logsig transmission functions are used between hidden layer and the second hidden layer, between the second hidden layer and the 3rd hidden layer, the 3rd implicit
Use purelin transmission functions between layer and output layer, the weighted value between each layer node (quantifies to be conjugated using trainscg
Gradient method) it is adjusted, training method uses LM (LevenbergMarquard) algorithm.
Beneficial effect：It is provided by the invention based on artificial god compared with the Forecasting Methodology of existing stable state average throughput
The Forecasting Methodology of average throughput under out-of order processor stable state through network, covering influences the multiple micro- of stable state average throughput
Framework independent parameter, including：Dynamic instruction mixing ratio, critical path depth distribution, serial command distribution；In addition, this hair
It is bright that stable state average throughput is predicted using neutral net, the coupling between micro-architecture independent parameter can be adequately taken into account
Conjunction property, and the model by training can quickly and accurately predict the value of stable state average throughput.
Brief description of the drawings
Fig. 1 is the particular flow sheet using present invention training Ann models；
Fig. 2 is that neural network model training, the input of test and target export block diagram；
Fig. 3 is neutral net level figure.
Embodiment
The present invention is further described below in conjunction with the accompanying drawings.
The Forecasting Methodology of average throughput under a kind of out-of order processor stable state based on artificial neural network, including following step
Suddenly：
(1) discontinuous point that the time point that thread number switches when instruction set simulator is emulated is split as fragment, so that will
Whole target program is divided into some fragments, and all fragments are divided and sorted by thread number, each fragment is counted and includes
Clock number, delete clock number be less than 1000 fragment；
(2) to the fragment remained in subject thread, obtain each fragment using instruction set simulator and be averaged with stable state
The related micro-architecture independent parameter of throughput, the micro-architecture independent parameter include dynamic instruction flow mixing ratio, critical path path length
Degree, serialized instructions, the operation total time of front end instruction issue speed and target program；By the structure for defining instruction type
Body, the type of every instruction is recorded, the distribution situation of all types of instructions is counted, so as to obtain dynamic instruction flow mixing ratio；Pass through
Definition structure body, count under fixed instruction window size, the distribution situation for relying on dependent instruction number maximum be present, so as to
To critical path depth distribution situation；By defining search instruction type, and the number of ISB, DSB, DMB instruction is counted, can be with
Obtain serialized instructions number；At the same time, monitor processor front end instruction issue level and count a period of time or a finger
The number of instructions launched in flow section and the clock number of cost are made, to calculate front end instruction issue speed；
(3) first, requirement of the BP neural network to input data is considered, to the related micro-architecture independent parameter of each fragment
Pre-processed (especially dynamic instruction flow mixing ratio relevant parameter), formed the related micro-architecture independent parameter of homologous segment to
Amount；Then, by principal component analysis (choosing the pivot composition for including more than 95% initial data, reduce original data volume) to every
Individual related micro-architecture independent parameter vector carries out dimensionality reduction, denoising, forms the MicaData data sets of homologous segment；
(4) to the fragment remained in subject thread, first, all MicaData data sets are divided into by SOM N number of
Major class；Then, n-th of major class is divided into by M by k- means clustering algorithmsnIndividual group, 1≤n≤N；Choose in each group
Characteristic point of the heart point as the group；
(5) to the fragment remained in subject thread, the input using all characteristic points as BP neural network, BP nerves
The output of network is the stable state average throughput of subject thread, and input and output to BP neural network are fitted, and pass through tune
The iterations and training precision of BP neural network are saved, training obtains the BP neural network model of subject thread；
(6) utilize instruction set simulator operational objective program and add software inserting stake, statistics dynamic instruction flow mixing ratio,
Critical path depth and serial command distribution, all characteristic points of related linear program are obtained after handling obtained data,
And it imported into the BP neural network model of subject thread, you can it is steady in out-of order processor quickly and accurately to predict subject thread
Average throughput under state.
Fig. 1 is the particular flow sheet of training Ann models.After taking out data from instruction set simulator, enter according to thread number
Row is sorted out, and then data are pre-processed, then carries out dimensionality reduction by PCA, and finally by SOM, Kmeans algorithm picks go out most
Input of the representative characteristic point as model, train the higher model of precision.
Fig. 2 is that neural network model training, the input of test and target export block diagram.Emulated by instruction set simulator,
We can obtain the parameter input and target output of model, so as to train the higher model of precision；Be predicted when
Wait, it is only necessary to the relevant parameter of destination application is drawn by simulator, these parameters are then imported into model, it is possible to be fast
Stable state average throughput value is predicted fastly；The flow for training process of bold portion in figure, dotted portion are prediction process
Flow.
Fig. 3 is neutral net level figure.The present invention is according to hidden layer node number empirical equation：
Wherein：H represents node in hidden layer, and m represents output layer nodes, and n represents input layer number, and a represents one
Constant (1≤a≤10).This case uses three hidden layers, and the first hidden layer uses 30 neural units, and the second hidden layer uses 15
Individual neuron, the 3rd hidden layer use 15 neurons；Training method uses LM (LevenbergMarquard) algorithm.
Described above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (4)
- A kind of 1. Forecasting Methodology of average throughput under out-of order processor stable state based on artificial neural network, it is characterised in that： Comprise the following steps：(1) discontinuous point that the time point that thread number switches when instruction set simulator is emulated is split as fragment, so as to by entirely Target program is divided into some fragments, and all fragments are divided and sorted by thread number, count that each fragment includes when Clock number, delete the fragment that clock number is less than threshold value；(2) to the fragment remained in subject thread, using instruction set simulator obtain the related micro-architecture of each fragment without Related parameter, micro-architecture independent parameter include dynamic instruction flow mixing ratio, critical path depth, serialized instructions, front end instruction hair The operation total time of firing rate rate and subject thread；By defining the structure of instruction type, the type of every instruction, statistics are recorded The distribution situation of all types of instructions, so as to obtain dynamic instruction flow mixing ratio；By definition structure body, fixed instruction window is counted Under size, the distribution situation for relying on dependent instruction number maximum be present, so as to obtain critical path depth distribution situation；Pass through Search instruction type is defined, and counts the number of ISB, DSB, DMB instruction, obtains serialized instructions number；At the same time, monitor Processor front end instruction issue level simultaneously counts the number of instructions launched in a period of time or an instruction stream fragment and cost Clock number, to calculate front end instruction issue speed；(3) first, consider requirement of the BP neural network to input data, the related micro-architecture independent parameter of each fragment is carried out Pretreatment, form the related micro-architecture independent parameter vector of homologous segment；Then, by principal component analysis to each micro- frame of correlation Structure independent parameter vector carries out dimensionality reduction, denoising, forms the micro-structural extraneous data collection of homologous segment；(4) to the fragment remained in subject thread, first, by self-organized mapping network by all micro-structural extraneous datas Collection is divided into N number of major class；Then, n-th of major class is divided into by M by k- means clustering algorithmsnIndividual group, 1≤n≤N；Choose each Characteristic point of the point closest from central point as the group in group；(5) to the fragment remained in subject thread, the input using all characteristic points as BP neural network, BP neural network Output be the stable state average throughput of subject thread, input and output to BP neural network be fitted, and training obtains mesh The BP neural network model of graticule journey；(6) after the completion of BP neural network model training, by instruction set simulator obtain the micro-architectures of other threads to be predicted without Related parameter information, it imported into the BP neural network model trained, you can rapidly and accurately predict actual stable state average throughput Rate value.
- 2. the prediction of average throughput under the out-of order processor stable state according to claim 1 based on artificial neural network Method, it is characterised in that：In the step (5), BP neural network has three hidden layers, and the first hidden layer uses 30 nerves Member, the second hidden layer use 15 neurons, and the 3rd hidden layer uses 15 neurons；Between input layer and the first hidden layer, Logsig transmission functions are used between first hidden layer and the second hidden layer, between the second hidden layer and the 3rd hidden layer, the 3rd Use purelin transmission functions between hidden layer and output layer, the weighted value between each layer node is carried out using trainscg Regulation, training method use LM algorithms.
- 3. the prediction of average throughput under the out-of order processor stable state according to claim 1 based on artificial neural network Method, it is characterised in that：In the step (1), threshold value 1000, that is, the fragment that clock number is less than 1000 is deleted.
- 4. the prediction side of average throughput under the out-of order processor stable state according to claim 1 based on artificial neural network Method, it is characterised in that：In the step (6), other threads to be predicted include the thread in target program, or other application journey Thread in sequence.
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