CN105592624B - The High density of PCB plate and edge for efficiently inhibiting edge radiation radiate suppressing method - Google Patents
The High density of PCB plate and edge for efficiently inhibiting edge radiation radiate suppressing method Download PDFInfo
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- CN105592624B CN105592624B CN201510964145.8A CN201510964145A CN105592624B CN 105592624 B CN105592624 B CN 105592624B CN 201510964145 A CN201510964145 A CN 201510964145A CN 105592624 B CN105592624 B CN 105592624B
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000005855 radiation Effects 0.000 title abstract description 13
- 230000002401 inhibitory effect Effects 0.000 title abstract description 6
- 238000013461 design Methods 0.000 claims abstract description 19
- 238000010276 construction Methods 0.000 claims description 37
- 230000005670 electromagnetic radiation Effects 0.000 abstract description 12
- 230000005764 inhibitory process Effects 0.000 abstract description 8
- 230000002829 reductive effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000003475 lamination Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A kind of efficient High density of PCB plate for inhibiting edge radiation of the present invention and edge radiation suppressing method.The main source of EMI is power distribution network in pcb board, power/ground planes in power distribution network are to forming a resonant cavity, serious electromagnetic radiation can be caused at resonant frequency, High density of PCB plate and edge proposed by the present invention radiate suppressing method, electromagnetic radiation that can be in high-efficiency shielding power supply/ground, optimal state is reduced to by EMI.Wherein stack-design uses inlaid flat capacitive stack, this to be considered as ac short circuit in high band to the inlaid flat capacitance constituted by thin dielectric and power supply ground level, can reach particularly preferred electromagnetic radiation inhibition.
Description
Technical field
The present invention relates to pcb board field, relate more specifically to a kind of efficient High density of PCB plate for inhibiting edge radiation and side
Along radiation suppressing method.
Background technology
With the high speed development of semiconductor technology, the collection of electronic system is increasing on a large scale, and volume is smaller and smaller, speed
It is getting faster, function is also stronger and stronger.But be also integrated into just because of numerous transistors in single chip, processor and
The power consumption of chip is continuously increased, and supply voltage constantly reduces, and voltage noise tolerance also reduces therewith, and electromagnetic radiation is continuously increased,
Problems of Signal Integrity is more and more severeer.Electromagnetic interference（EMI）Problem has become high-speed digital system and designs faced one
Huge challenge.
The fringe radiation inhibition of PCB is a part of High-Speed PCB EMI/EMC (plate grade EMI) designs, while being also most
An important part.At this stage, some are often used in that the method for electromagnetic radiation is inhibited to have：20-H criterion, the protection of edge via
Column, electromagnetic bandgap structure, Split type electric container decoupling wall etc..20-H criterion are a rule of thumb, are reached many times
Inhibition it is unsatisfactory.Edge via protective fence is to order some at the edge of PCB similar to the via buffer zone of fence to come
Electromagnetic radiation is shielded, good inhibition can be played.Electromagnetic bandgap structure can also play preferable inhibition, still
General mushroom-shaped EBG structures have poor low frequency isolation and stopband is relatively narrow.Split type electric container decouples wall design simply, still
Performance protrudes when only frequency is low, and in high frequency, performance is bad.
Scheme provided by the invention is mainly based upon the stack-design of the PCB of inlaid flat decoupling capacitor and short circuit hole is set
Meter.Present veneer and system velocity is higher and higher, and the lamination of veneer PCB is more and more important.The lamination of veneer PCB is exactly will letter
Number floor, power plane layer and ground plane layer require but also meet reasonably to be stacked under veneer performance requirement not only meeting mechanical technology
Together.Rational lamination can not only play the role of signal transmssion line impedance control, while play system noise in suppressing plate again
Effect, can play inhibit electromagnetic radiation effect.The design method proposed decouples electricity primarily directed to inlaid flat
The stack-design of appearance.Inlaid flat capacitance needs to access noise in the entire current loop of PCB using short circuit hole, so
The connection type of short circuit hole also influences the effect of EMI.
Invention content
The present invention is to solve the defect of the above prior art, provides a kind of efficient High density of PCB for inhibiting edge radiation
EMI is reduced to optimal state by plate, electromagnetic radiation that can be in high-efficiency shielding bus plane/stratum.
To realize the above goal of the invention, the technical solution adopted is that：
A kind of efficient High density of PCB plate for inhibiting edge radiation, it is characterised in that：Using asymmetric laminated construction or
Symmetrical laminated construction, wherein stratum-electricity that the laminated construction of the asymmetric is sequentially distributed from top to bottom by several
Active layer is to constituting, wherein the stratum-bus plane centering stratum is located at the top of bus plane；The laminated construction of the symmetrical expression by
Several bus plane-stratum-bus planes being sequentially distributed from top to bottom are to constituting, wherein the stratum is arranged in two layers of bus plane
Between；
In the laminated construction of asymmetric and symmetrical laminated construction, one is provided between adjacent stratum and bus plane
The dielectric layer of floor height dielectric constant, stratum, bus plane are bonded with dielectric layer；The dielectric constant of the dielectric layer of the high-k
More than 3.7；
In the laminated construction of asymmetric and symmetrical laminated construction, all bus plane/stratum pass through short-circuit via
It is attached.
In said program, the inlaid flat capacitance being made of dielectric layer and bus plane, stratum, due to larger distribution electricity
Hold and in high band be considered as ac short circuit, bus plane, stratum can be considered as the short circuit of infinitely small impedance as a result,.It is such a
Inlaid flat capacitance can be considered a plane, and in this case, inlaid flat capacitance just can be considered ground short circuit hole.
Preferably, the thickness of the dielectric layer is 0.4mm.
Preferably, the thickness of the dielectric layer is 0.01mm, dielectric constant 20.
Preferably, the laminated construction of the asymmetric or symmetrical expression laminated construction in, bus plane, stratum thickness one
It causes.
Preferably, the radius of the short-circuit via is 0.15mm.
Meanwhile the present invention also provides a kind of edges to radiate suppressing method, concrete scheme is as follows：
A kind of edge radiation suppressing method carries out selection and to short-circuit mistake by the laminated construction to High density of PCB plate
The design in hole inhibits edge to radiate, and includes the following steps：
S1. judge that EMI interference for low-frequency disturbance or High-frequency Interference, if low-frequency disturbance, then makes High density of PCB plate use
Symmetrical laminated construction then makes High density of PCB plate use the laminated construction of asymmetric if High-frequency Interference；
S2. the period of short-circuit via is calculated, if the period of short-circuit via is more than 20H, makes High density of PCB plate using non-right
The laminated construction of title formula, and short-circuit via is made only to connect all stratum；If the period of short-circuit via is less than 20H,
Make, make High density of PCB plate using symmetrical laminated construction, and short-circuit via is made to connect all stratum, all bus planes
It picks up and；
If the laminated construction that S3. S1, S2 are determined mutually conflicts, the laminated construction determined using step S1.
Compared with prior art, the beneficial effects of the invention are as follows：
（1）Inlaid flat decoupling capacitor can provide quick conversion speed, and the power to improve high speed circuit passes
Defeated performance.
（2）The power of high-frequency noise is efficiently reduced, signal integrity performance is improved, reduces EMI.
（3）It has excellent performance, good inhibition can be reached.
（4）Inhibit band that can reach very wide, obtains very high corner frequency.
Description of the drawings
Fig. 1 is experimental prototype plate schematic diagram.
Fig. 2 is inlaid flat decoupling capacitor structural schematic diagram.
Fig. 3 is asymmetric laminated construction schematic diagram.
Fig. 4 is symmetrical laminated construction schematic diagram.
Fig. 5 is G short circuit via schematic diagrames.
Fig. 6 is P short circuit via schematic diagrames.
Fig. 7 is P/G short circuit via schematic diagrames.
Fig. 8 is ground short circuit hole schematic diagram.
Specific implementation mode
The attached figures are only used for illustrative purposes and cannot be understood as limitating the patent；
Below in conjunction with drawings and examples, the present invention is further elaborated.
Embodiment 1
1, experimental plate prototype selection of the invention.
For the present invention using the most common three layers of pcb board of existing size as experimental plate prototype, size is 80mm × 120mm, is situated between
Material is the FR4 that most common dielectric constant is 4.4, and the thickness of dielectric layer is 0.4mm, and power/ground planes layer thickness is
0.03mm.Driving source encourages for lump port, is located at the lower right side of pcb board, as shown in Figure 1.
2, inhibit the inlaid flat capacitive stack design of edge radiation.
For this prototype board, electromagnetic radiation can be generated due to various.At horizontal edge in current path
Disconnected, change in the instantaneous impedance, signal occurs transmitting and generates ring, and peak value, aggravation radiation occurs at ringing frequency in frequency spectrum.Power supply/Horizon
In face of constituting surface plate resonant cavity, resonance phenomena is occurred by the electric current of interplanar or noise excitation, to be produced in PCB edge
Raw serious electromagnetic radiation.This inlaid flat capacitive stack design proposed by the present invention, can reach good electromagnetism spoke
Inhibition is penetrated, is as follows：
（1）Each bus plane of prototype board and stratum are designed as inlaid flat capacitance structure, i.e., by very thin, high
The thickness of the power/ground planes pair that the medium of dielectric constant separates, new medium layer usually takes 0.01mm, dielectric constant 20.
（2）There are two types of the laminations of inlaid flat decoupling capacitor, and one is the laminations of asymmetric G-P-G-P-G-P to set
Meter, as shown in figure 3, another kind is the stack-design of symmetrical P-G-P-P-G-P, as shown in Figure 4.
For Fig. 3, the effect is relatively poor for top planes capacitor decoupling when low frequency, and electric current more more options are P short circuit holes paths
And subsequent bottom plane capacitance circulates and is formed into a loop, when high frequency, top planes capacitor decoupling effect is substantially improved, electric current
Selection top planes capacitance and G short circuit vias circulate and are formed into a loop.Similar for the analysis of Fig. 4, only electric current passes through when low frequency
The short circuit hole crossed is G short circuit holes, and the short circuit hole that high frequencies current passes through is P short circuit holes.Observation chart 3 and Fig. 4 can be seen that non-right
Title formula and symmetrical lamination, short circuit hole path is different, and when low frequency, the P short circuit holes of G short circuits hole length ratio Fig. 3 of Fig. 4 are long
Spend short, corresponding parasitic inductance and its impedance brought are also small, so noise decoupling performance is more preferable, the electromagnetic radiation of generation also can
Smaller.And in high frequency, the P short circuits via length in Fig. 4 is then longer than the G short circuit via lengths of Fig. 3, so denoising performance ratio
Poor, the electromagnetic radiation brought is also just than Fig. 3 bigger.
So EMI when low frequency inhibits to use symmetrical stack-design, EMI when high frequency inhibits using the folded of asymmetric
Layer structure.
3, the design of short-circuit via wall.
As long as the edge surrounding in pcb board is connected upper and lower inlaid flat decoupling capacitor with short circuit hole,
Realize effective management to power supply noise, to prevent interplanar noise, steps are as follows for the major design of short-circuit via wall：
（1）The determination of via, pad, anti-pad size.
The problems such as connection of via belongs to non-ideal interconnection, can bring change in the instantaneous impedance, reflection.Pad is that via exists with cabling
Mutually melt part in junction, it is therefore an objective to make junction impedance matching as possible.Via makes to be formed by the plane of unnecessary connection
Anti-pad, radius were slightly larger than, and were commonly called as clearance hole.From the aspect of cost and signal quality two, the via of reasonable size is selected
Size, the mistake pore size that the present invention selects are 0.15mm.Clearance hole is equivalent to plane, and there are one small flutings, can destroy
The continuity of plane so that the loop inductance of plane becomes larger, and electromagnetism integrality is deteriorated, so should be used as possible in redesign small
Clearance hole and keep the distance between clearance hole big as possible.
（2）The determination in via period.
The period of short-circuit via can calculate according to following formula：
Wherein fcIndicate the corner frequency of short-circuit via, C0For the light velocity in vacuum, k is a correction factor, is worth and is
0.13, p is short circuit hole distribution period, and r is short-circuit pore radius, and ε r are the dielectric constant of medium.
The decoupling wall design of the short circuit hole of each period and radius all corresponds to a radiation and inhibits band, and the period is smaller, and half
Diameter is bigger, inhibits band wider, and the upper limiting frequency of our this inhibition band is referred to as the corner frequency of short circuit hole.In actual design,
If it is known that the radius of required corner frequency and short circuit hole, can find out the week of short-circuit via according to formula above
Phase.
（3）The selection of short circuit hole connection type
Short circuit hole is there are three types of connection type, G short circuits via, P short circuits via and P/G short circuit vias, correspond to respectively Fig. 5,
6,7.Under normal circumstances, only to the connection of the P short circuit vias of bus plane and only to the G short circuit vias connection effect on stratum all it is poor not
It is more, but the effect for all simultaneously all not connecting bus plane P with short circuit via with stratum G is good, so all selecting under normal circumstances
Select the connection of P/G short circuit vias.
The short-circuit via period is excessive, it should the lamination using asymmetric and single G short circuit vias, if short-circuit via
Period it is sufficiently small, it should using the lamination of asymmetric add mixing P/G short circuit holes design.
4, high frequency equivalent designs
By thin dielectric and power supply ground level to the inlaid flat capacitance that constitutes, as shown in Fig. 2, due to larger distribution
Capacitance is considered as ac short circuit in high band, and power supply ground level is to that can be considered as the short circuit of infinitely small impedance as a result,.Such one
A inlaid flat capacitance can be considered a plane, and in this case, inlaid flat capacitance just can be considered ground short circuit
Hole, as shown in Figure 8.
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
All any modification, equivalent and improvement etc., should be included in the claims in the present invention made by within the spirit and principle of invention
Protection domain within.
Claims (5)
1. a kind of edge radiates suppressing method, it is characterised in that：By the laminated construction to High density of PCB plate carry out selection and
Inhibit edge to radiate the design of short-circuit via, includes the following steps：
S1. judge that EMI interference for low-frequency disturbance or High-frequency Interference, if low-frequency disturbance, then makes High density of PCB plate using symmetrical
The laminated construction of formula then makes High density of PCB plate use the laminated construction of asymmetric if High-frequency Interference；
S2. the period of short-circuit via is calculated, if the period of short-circuit via is more than 20H, High density of PCB plate is made to use asymmetric
Laminated construction, and make short-circuit via only all stratum are connected；If the period of short-circuit via is less than 20H, make then
Make High density of PCB plate using symmetrical laminated construction, and short-circuit via is made to connect all stratum, all bus planes
Come；
If the laminated construction that S3. S1, S2 are determined mutually conflicts, the laminated construction determined using step S1；
Laminated construction or symmetrical laminated construction of the laminated construction of the wherein described High density of PCB plate using asymmetric,
Described in asymmetric stratum-bus plane for being sequentially distributed from top to bottom by several of laminated construction to constituting, wherein described
Stratum-bus plane centering stratum is located at the top of bus plane；The laminated construction of the symmetrical expression by several from top to bottom successively
Bus plane-stratum-bus plane of distribution is to constituting, wherein the stratum is arranged between two layers of bus plane；
In the laminated construction of asymmetric and symmetrical laminated construction, a floor height is provided between adjacent stratum and bus plane
The dielectric layer of dielectric constant, stratum, bus plane are bonded with dielectric layer；The dielectric constant of the dielectric layer of the high-k is more than
3.7；
In the laminated construction of asymmetric and symmetrical laminated construction, all bus plane/stratum are carried out by short-circuit via
Connection.
2. edge according to claim 1 radiates suppressing method, it is characterised in that：The thickness of the dielectric layer is 0.4mm.
3. edge according to claim 1 radiates suppressing method, it is characterised in that：The thickness of the dielectric layer is
0.01mm, dielectric constant 20.
4. edge according to claim 1 radiates suppressing method, it is characterised in that：The laminated construction of the asymmetric or
In symmetrical laminated construction, bus plane, stratum consistency of thickness.
5. edge according to claim 1 radiates suppressing method, it is characterised in that：It is described short circuit via radius be
0.15mm。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510964145.8A CN105592624B (en) | 2015-12-17 | 2015-12-17 | The High density of PCB plate and edge for efficiently inhibiting edge radiation radiate suppressing method |
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| CN201510964145.8A CN105592624B (en) | 2015-12-17 | 2015-12-17 | The High density of PCB plate and edge for efficiently inhibiting edge radiation radiate suppressing method |
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| CN105592624A CN105592624A (en) | 2016-05-18 |
| CN105592624B true CN105592624B (en) | 2018-11-13 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107801296A (en) * | 2017-11-07 | 2018-03-13 | 上海斐讯数据通信技术有限公司 | The printed circuit board (PCB) and terminal device of fringe radiation can be reduced |
| US11096277B2 (en) | 2019-09-12 | 2021-08-17 | International Business Machines Corporation | Printed circuit board shielding and power distribution via edge plating |
| CN111310304B (en) * | 2020-01-17 | 2024-01-19 | 中山大学 | Method for estimating relative deflection sensitivity of radiation power to differential pair signals based on network parameters |
| CN117320254A (en) * | 2022-06-24 | 2023-12-29 | 华为技术有限公司 | Circuit board and terminal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1699275A2 (en) * | 2005-03-02 | 2006-09-06 | Samsung Electro-mechanics Co., Ltd | Printed circuit board with embedded capacitors therein and manufacturing process thereof |
| CN101682989A (en) * | 2007-03-10 | 2010-03-24 | 新美亚通讯设备有限公司 | Embedded capacitive stack |
| CN205726708U (en) * | 2016-05-03 | 2016-11-23 | 深圳市朤科自动化设备有限公司 | Chip mounter flies up to or the spacing adjusting device of suction nozzle |
-
2015
- 2015-12-17 CN CN201510964145.8A patent/CN105592624B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1699275A2 (en) * | 2005-03-02 | 2006-09-06 | Samsung Electro-mechanics Co., Ltd | Printed circuit board with embedded capacitors therein and manufacturing process thereof |
| CN101682989A (en) * | 2007-03-10 | 2010-03-24 | 新美亚通讯设备有限公司 | Embedded capacitive stack |
| CN205726708U (en) * | 2016-05-03 | 2016-11-23 | 深圳市朤科自动化设备有限公司 | Chip mounter flies up to or the spacing adjusting device of suction nozzle |
Non-Patent Citations (1)
| Title |
|---|
| 高速PCB电源完整性设计与分析;苏良碧;《中国硕士学位论文全文数据库》;20110815;全文 * |
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