CN105573789A - FPGA (Field Programmable Gate Array) multi-mirror upgrading-loading method and device based on soft-core processor - Google Patents
FPGA (Field Programmable Gate Array) multi-mirror upgrading-loading method and device based on soft-core processor Download PDFInfo
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array) multi-mirror upgrading-loading method based on a soft-core processor. A single FPGA way is adopted, and the soft-core processor and control modules are embedded inside to implement an interface function; a program file caching function is implemented; and a chip scale interconnected bus interface function is implemented together with a CPLD (Complex Programmable Logic Device). The upgrading-loading method is implemented by an FPGA and the CPLD. The invention also discloses an FPGA multi-mirror upgrading-loading device based on the soft-core processor. The device comprises an upper computer, an interface receiving-transmitting module, an FPGA module, an external caching module, an external storage module and a CPLD module. Through adoption of the FPGA multi-mirror upgrading-loading method and device, FPGA multi-mirror rapid upgrading and flexible loading based on different application scenes are realized.
Description
Technical Field
The invention relates to the field of FPGA (field programmable gate array) upgrading and loading, in particular to a method and a device for FPGA multi-image upgrading and loading.
Background
At present, there are two main ways of program upgrading of an FPGA (field programmable gate array): using an FPGA programmer to upgrade the FPGA program through burning software of the FPGA; and the FPGA sends the program file of the FPGA to the FPGA through application software, and the FPGA carries out program self-upgrade through an internal RSU function.
Both of these two methods have certain limitations, and the first upgrading method has the disadvantages that: the upgrading speed is very slow, remote upgrading cannot be carried out, and only single-image program file upgrading is supported; the second upgrading mode has the advantages and disadvantages that: the method has the advantages of supporting remote upgrading and having the defect of low upgrading speed and only supporting single-image program file upgrading.
With the continuous development of the FPGA technology, peripheral functions that the FPGA can complete are more and more abundant, and applications with different functions can be completed in the same FPGA, but the functions supported by the FPGA cannot be completely placed in the same mirror image program due to the limitation of the FPGA resources, and when the same mirror image program includes multiple functions, the stability, timing sequence and power consumption of the whole system are greatly affected. In order to solve the problems, the functions can be divided according to different application scenes, different mirror image files are adopted in the same FPGA to complete different functions, and the purposes of optimizing time sequence, reducing power consumption, improving system stability and the like are achieved.
Disclosure of Invention
The invention provides a method and a device for upgrading and loading a multi-image of an FPGA (field programmable gate array) based on a soft-core processor, aiming at solving the problems of low upgrading speed and small number of images of the current FPGA program and realizing rapid upgrading and flexible loading of the multi-image of the FPGA based on different application scenes.
On one hand, the invention provides an FPGA multi-image upgrading and loading method based on a soft-core processor, which comprises the following steps:
the method comprises the steps that an upper computer selects a mirror image file needing to be upgraded, an upgrade starting command is issued through an interface, a protocol stack in the FPGA analyzes command information and then sends the command information to a soft core processor module of the FPGA, the soft core processor module of the FPGA obtains the file name and the file length of an upgrade mirror image according to the command, and then sends a message packet that the FPGA is ready for upgrading to the upper computer;
after receiving the packet, the upper computer starts to issue mirror image file data;
the soft core processor module of the FPGA stores the image file data sent by the upper computer into an external cache module through the control module by setting the control module of the FPGA;
after the image file data is issued, the soft core processor module of the FPGA informs the soft core processor module of the CPLD through the control module, and transmits the file name and the file length of the image file to the CPLD;
after the CPLD is ready, the soft core processor module of the FPGA reads out image file data needing to be upgraded from an external cache module of the FPGA through a control module of the FPGA, and then sends the image file data to the CPLD through a main external bus interface, and the soft core processor module of the CPLD reads the data through the external bus interface and then sends the data to a storage control block to finish the storage of the upgraded image file;
after all data are written into the external storage module of the CPLD, the CPLD sets the current mirror image file as the next loading file and updates the state of the register after upgrading, and after the soft kernel processor module of the FPGA inquires the state of the register, the upper computer is informed of finishing the upgrading operation through an interface;
and after the upgrading is finished, the loading of the FPGA is realized.
Further, the soft core processor module of the FPGA stores the image file data sent by the upper computer into an external cache module through a cache control block in the control module by setting a main control block in the FPGA control module.
Further, after the image file data is sent, the soft core processor module of the FPGA notifies the soft core processor module of the CPLD through the main external storage interface control block in the control module.
Further, after the upgrade is completed, the method for implementing loading of the FPGA specifically includes:
after the FPGA image file is upgraded, the CPLD actively reads the image file which is just upgraded from the external storage module, and sends the image file to the configuration module of the FPGA to realize the loading of the FPGA.
On the other hand, the invention provides an FPGA multi-image upgrading loading device based on a soft core processor, which comprises: the device comprises an upper computer, an interface transceiver module, an FPGA module, an external cache module, an external storage module and a CPLD module; wherein,
the upper computer is used for man-machine interaction and carrying out program upgrading and mirror image switching control;
the interface transceiving module is used for bidirectional communication interaction between the upper computer and the FPGA module;
the FPGA module is used for integrating the soft-core processor and the respective definition function modules;
the external cache module is used for temporarily storing the data to be processed by the system;
the external storage module is used for storing program file data of the FPGA;
and the CPLD module and the external mounting memory are used for storing the program file of the FPGA and communicating with the FPGA module to complete program upgrading.
Further, the FPGA module includes: the system comprises a protocol stack module, a control module, a soft-core processor module and a configuration module; wherein,
the protocol stack module is used for analyzing the data transmitted by the interface, transmitting the command data to the soft-core processor module and transmitting the mirror image file data to the control module;
the control module is used for exchanging and controlling data with the protocol stack module, the soft-core processor module, the external cache module and the CPLD module;
the soft core processor module is used for scheduling tasks in the FPGA, managing a file system, analyzing and distributing control commands and controlling a work flow;
and the configuration module is used for entering an initialization state after receiving the program file data of the FPGA, then entering a user state and executing corresponding user application operation.
Further, the control module of the FPGA includes: the device comprises a main control block, a cache control block and a main external storage interface control block; wherein,
the main control block is used for large data volume transmission, bus switching and multiplexing;
the cache control block is used for interacting with the main control block data and performing read-write access on the external cache module;
and the main external storage interface control block is used for carrying out data interaction with the main control block and controlling an external bus to carry out data transmission with the CPLD.
Further, the CPLD module includes: the device comprises a storage control block, a soft-core processor module and a loading module; wherein,
the storage control block is used for performing data interaction with the soft-core processor module, the loading module, the FPGA module and the external storage module, and controlling, forwarding and storing upgrading program file data and upgrading command data;
the soft-core processor module is used for scheduling internal tasks of the CPLD, managing a file system, analyzing and distributing control commands and controlling a work flow;
the loading module is used for receiving the FPGA program file data sent by the storage control block, controlling an external bus and sending the program file data to the configuration module in the FPGA.
Further, the memory control block includes: from the external storage interface control subblock, store the control subblock; wherein,
the slave external storage interface control sub-block is used for performing bus interaction with the FPGA, receiving upgrading program file data and upgrading command data of the FPGA, forwarding the program file data to the storage control sub-block, and forwarding the command data to the soft core processor module of the CPLD;
the storage control sub-block is used for receiving data from the external storage interface control sub-block, storing the data into the external storage module, receiving a control command of the soft-core processor module, reading program file data of the FPGA from the external storage module, and sending the program file data to the loading module.
In the technical scheme, the FPGA multi-image upgrading and loading method and device based on the soft-core processor adopt a single FPGA mode, and the soft-core processor and each control block are embedded inside the FPGA multi-image upgrading and loading device to realize an interface function, a program file caching function, a chip-level interconnection bus interface function completed by the same CPLD and the like. And the single CPLD is adopted to realize the multi-image program file upgrading management of the FPGA, the selection, loading and starting functions of the FPGA program file and the like.
In the technical scheme, the method for realizing the remote upgrade is jointly completed by the FPGA and the CPLD.
In the technical scheme, the FPGA multi-image upgrading and loading method and device based on the soft-core processor have the main functions of completing multi-image program upgrading of the FPGA and selecting a corresponding image file to load the FPGA according to related configuration. The loading method comprises the following steps:
the multi-image loading of the FPGA is mainly completed by the assistance of the CPLD, firstly, after the CPLD normally operates, the CPLD selects a corresponding FPGA image file by reading the configuration information of the external storage memory, then, the image file data is read out from the external storage module and sent to the configuration module of the FPGA, and the loading starting of the FPGA is realized.
Compared with the prior art, the invention has the following advantages:
(1) the remote upgrading time is greatly shortened, and the upgrading process of a single image file is completed within 2 seconds. Whereas, the program upgrading method for the FPGA by adopting the programmer is about 3 minutes, and the remote upgrading mode with the RSU function is about 40 seconds.
(2) The device supports multiple mirror image functions and supports 2 and more than 2 FPGA mirror image files according to the size of an external storage space. The application programs of the plurality of FPGA are programmed into the device at one time, different image files can be selected to be started through setting in practical application, the application diversity of the device is met, and the operation of repeatedly upgrading the programs in different application processes is avoided.
Drawings
FIG. 1 is a schematic diagram of an FPGA multi-image upgrade loading device composition based on a soft core processor;
FIG. 2 is another schematic diagram of an FPGA multi-image upgrade loading device based on a soft-core processor.
The following reference numerals are marked thereon in conjunction with the accompanying drawings: the system comprises an upper computer 1, a 2-interface transceiving module, a 3-FPGA module, a 4-external cache module, a 5-external storage module and a 6-CPLD module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On one hand, the invention provides an FPGA multi-image upgrading and loading method based on a soft-core processor, which comprises the following steps:
the method comprises the steps that an upper computer selects a mirror image file needing to be upgraded, an upgrade starting command is issued through an interface, a protocol stack in the FPGA analyzes command information and then sends the command information to a soft core processor module of the FPGA, the soft core processor module of the FPGA obtains the file name and the file length of an upgrade mirror image according to the command, and then sends a message packet that the FPGA is ready for upgrading to the upper computer;
after receiving the packet, the upper computer starts to issue mirror image file data;
the soft core processor module of the FPGA stores the image file data sent by the upper computer into an external cache module through the control module by setting the control module of the FPGA;
after the image file data is issued, the soft core processor module of the FPGA informs the soft core processor module of the CPLD through the control module, and transmits the file name and the file length of the image file to the CPLD;
after the CPLD is ready, the soft core processor module of the FPGA reads out image file data needing to be upgraded from an external cache module of the FPGA through a control module of the FPGA, and then sends the image file data to the CPLD through a main external bus interface, and the soft core processor module of the CPLD reads the data through the external bus interface and then sends the data to a storage control block to finish the storage of the upgraded image file;
after all data are written into the external storage module of the CPLD, the CPLD sets the current mirror image file as the next loading file and updates the state of the register after upgrading, and after the soft kernel processor module of the FPGA inquires the state of the register, the upper computer is informed of finishing the upgrading operation through an interface;
and after the upgrading is finished, the loading of the FPGA is realized.
Further, the soft core processor module of the FPGA stores the image file data sent by the upper computer into an external cache module through a cache control block in the control module by setting a main control block in the FPGA control module.
Further, after the image file data is sent, the soft core processor module of the FPGA notifies the soft core processor module of the CPLD through the main external storage interface control block in the control module.
Further, after the upgrade is completed, the method for implementing loading of the FPGA specifically includes:
after the FPGA image file is upgraded, the CPLD actively reads the image file which is just upgraded from the external storage module, and sends the image file to the configuration module of the FPGA to realize the loading of the FPGA.
In the technical scheme, the soft-core processor comprises NiosII series products.
On the other hand, as shown in fig. 1, fig. 1 is a schematic diagram of an FPGA multi-image upgrade loading device based on a soft-core processor, where the upgrade loading device includes: the system comprises an upper computer 1, an interface transceiver module 2, an FPGA module 3, an external cache module 4, an external storage module 5 and a CPLD module 6; wherein,
the upper computer 1 is used for man-machine interaction and carrying out program upgrading and mirror image switching control;
the interface transceiver module 2 is used for bidirectional communication interaction between the upper computer 1 and the FPGA module 3; optionally, the interface includes an ethernet interface, a serial port, and a USB interface;
the FPGA module 3 is used for integrating a soft-core processor and defining function modules respectively;
the external cache module 4 is used for temporarily storing data to be processed by the system; optionally, the external cache module comprises a DDR series memory;
the external storage module 5 is used for storing program file data of the FPGA; optionally, the external storage module comprises a nandflash and a norflash;
and the CPLD module 6 and the external mounting memory are used for storing the program file of the FPGA and communicating with the FPGA module 3 to finish program upgrading.
Further, the FPGA module 3 includes: a protocol stack module 31, a control module 32, a soft core processor module 33, and a configuration module 34; wherein,
the protocol stack module 31 is configured to parse data transmitted by the interface, transmit command data to the soft-core processor module 33, and transmit image file data to the control module 32;
the control module 32 is used for exchanging and controlling data with the protocol stack module 31, the soft core processor module 33, the external cache module 4 and the CPLD module 6;
the soft core processor module 33 is used for scheduling tasks in the FPGA, managing a file system, analyzing and distributing control commands, and controlling a work flow;
the configuration module 34 is configured to enter an initialization state after receiving the program file data of the FPGA, and then enter a user state to execute a corresponding user application operation.
Further, the CPLD module 6 includes: a storage control block 61, a soft core processor module 62, and a loading module 63; wherein,
the storage control block 61 is used for performing data interaction with the soft core processor module 62, the loading module 63, the FPGA module 3 and the external storage module 5, and controlling, forwarding and storing upgrade program file data and upgrade command data;
the soft-core processor module 62 is used for scheduling internal tasks of the CPLD, managing a file system, analyzing and distributing control commands, and controlling a workflow;
the loading module 63 is configured to receive the FPGA program file data sent by the storage control block, control the external bus, and send the program file data to the configuration module inside the FPGA.
FIG. 2 is another schematic diagram of an FPGA multi-image upgrade loading device based on a soft-core processor. As shown in fig. 2, the upgrade loading apparatus includes: the system comprises an upper computer 1, an interface transceiver module 2, an FPGA module 3, an external cache module 4, an external storage module 5 and a CPLD module 6; wherein,
the upper computer 1 is used for man-machine interaction and carrying out program upgrading and mirror image switching control;
the interface transceiver module 2 is used for bidirectional communication interaction between the upper computer 1 and the FPGA module 3; optionally, the interface includes an ethernet interface, a serial port, and a USB interface;
the FPGA module 3 is used for integrating a soft-core processor and defining function modules respectively;
the external cache module 4 is used for temporarily storing data to be processed by the system; optionally, the external cache module comprises a DDR series memory;
the external storage module 5 is used for storing program file data of the FPGA; optionally, the external storage module comprises a nandflash and a norflash;
and the CPLD module 6 and the external mounting memory are used for storing the program file of the FPGA and communicating with the FPGA module 3 to finish program upgrading.
Further, the FPGA module 3 includes: a protocol stack module 31, a control module 32, a soft core processor module 33, and a configuration module 34; wherein,
the protocol stack module 31 is configured to parse data transmitted by the interface, transmit command data to the soft-core processor module 33, and transmit image file data to the control module 32;
the control module 32 is used for exchanging and controlling data with the protocol stack module 31, the soft core processor module 33, the external cache module 4 and the CPLD module 6;
the soft core processor module 33 is used for scheduling tasks in the FPGA, managing a file system, analyzing and distributing control commands, and controlling a work flow;
the configuration module 34 is configured to enter an initialization state after receiving the program file data of the FPGA, then enter a user state, and execute a corresponding user application operation after entering the user state.
Further, the CPLD module 6 includes: a storage control block 61, a soft core processor module 62, and a loading module 63; wherein,
the storage control block 61 is used for performing data interaction with the soft core processor module 62, the loading module 63, the FPGA module 3 and the external storage module 5, and controlling, forwarding and storing upgrade program file data and upgrade command data;
the soft-core processor module 62 is used for scheduling internal tasks of the CPLD, managing a file system, analyzing and distributing control commands, and controlling a workflow;
the loading module 63 is configured to receive the FPGA program file data sent by the storage control block, control the external bus, and send the program file data to the configuration module inside the FPGA.
Further, the control module 32 of the FPGA module includes: a main control block 321, a cache control block 322, a main external storage interface control block 323; wherein,
the main control block 321 is used for large data volume transmission, bus switching and multiplexing;
the cache control block 322 is configured to interact with the main control block 321, and perform read-write access on the external cache module 4;
the main external storage interface control block 323 is configured to perform data interaction with the main control block 321, and control an external bus to perform data transmission with the CPLD.
Further, the storage control module 61 of the CPLD module includes: from external storage interface control sub-block 611, storage control sub-block 612; wherein,
the slave external storage interface control sub-block 611 is configured to perform bus interaction with the FPGA, receive upgrade program file data and upgrade command data of the FPGA, forward the program file data to the storage control sub-block 612, and forward the command data to the soft core processor module 62 of the CPLD;
the storage control sub-block 612 is configured to receive data from the external storage interface control sub-block 611, store the data in the external storage module 5, receive a control command of the soft-core processor module 62, read program file data of the FPGA from the external storage module 5, and send the program file data to the loading module 63.
In the technical scheme, the loading mode has two applications, namely online loading and power-on loading:
1) online loading
The first situation is that after the FPGA image file is upgraded, the CPLD can actively read the image file which is just upgraded from an external storage module and send the image file to a configuration module of the FPGA, so that the loading and starting of the FPGA are realized.
And in the second situation, in the running process of the program, after the application scene of the upper computer is changed (namely different functions are selected), the application software sends the changed application scene to a soft-core processor of the FPGA through an interface, the soft-core processor automatically searches for a proper application image according to the received application scene, then sends the name of the image file to be switched to the soft-core processor of the CPLD through a main external bus interface, and sends a switching image command, and the soft-core processor of the CPLD reads out the image file to be loaded from an external memory according to the name of the image file sent by the soft-core processor of the FPGA and sends the image file to a configuration module of the FPGA to realize the loading and starting of the FPGA.
2) Power-on loading
The power-on loading is mainly applied to FPGA loading in power-on. After the CPLD is electrified, the CPLD selects the image file to be loaded according to the configuration information of the current loaded image, reads the image file to be loaded from the external memory, and sends the image file to the configuration module of the FPGA to realize the loading and starting of the FPGA.
In the technical scheme, the multi-image file refers to a plurality of FPGA programs with different functions, and only one program can be upgraded each time, the programs cannot be upgraded simultaneously, but the programs can be upgraded sequentially. Upgrading one file 2s at a time can be done.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A FPGA multi-image upgrading and loading method based on a soft-core processor is characterized by comprising the following steps:
the method comprises the steps that an upper computer selects a mirror image file needing to be upgraded, an upgrade starting command is issued through an interface, a protocol stack in the FPGA analyzes command information and then sends the command information to a soft core processor module of the FPGA, the soft core processor module of the FPGA obtains the file name and the file length of an upgrade mirror image according to the command, and then sends a message packet that the FPGA is ready for upgrading to the upper computer;
after receiving the packet, the upper computer starts to issue mirror image file data;
the soft core processor module of the FPGA stores the image file data sent by the upper computer into an external cache module through the control module by setting the control module of the FPGA;
after the image file data is issued, the soft core processor module of the FPGA informs the soft core processor module of the CPLD through the control module, and transmits the file name and the file length of the image file to the CPLD;
after the CPLD is ready, the soft core processor module of the FPGA reads out image file data needing to be upgraded from an external cache module of the FPGA through a control module of the FPGA, and then sends the image file data to the CPLD through a main external bus interface, and the soft core processor module of the CPLD reads the data through the external bus interface and then sends the data to a storage control block to finish the storage of the upgraded image file;
after all data are written into the external storage module of the CPLD, the CPLD sets the current mirror image file as the next loading file and updates the state of the register after upgrading, and after the soft kernel processor module of the FPGA inquires the state of the register, the upper computer is informed of finishing the upgrading operation through an interface;
and after the upgrading is finished, the loading of the FPGA is realized.
2. The upgrade loading method according to claim 1, wherein the soft core processor module of the FPGA, by setting the control module of the FPGA, stores the image file data issued by the upper computer into the external cache module through the control module, and the specific implementation method is as follows:
the soft core processor module of the FPGA stores the image file data sent by the upper computer into an external cache module through a cache control block in the control module by setting a main control block in the FPGA control module.
3. The upgrade loading method according to claim 1, wherein after the image file data is completely issued, the specific implementation method for the soft core processor module of the FPGA to notify the soft core processor module of the CPLD through the control module is as follows:
after the image file data is issued, the soft core processor module of the FPGA informs the soft core processor module of the CPLD through the main external storage interface control block in the control module.
4. The upgrade loading method according to claim 1, wherein the method for implementing loading of the FPGA after the upgrade is completed specifically comprises:
after the FPGA image file is upgraded, the CPLD actively reads the image file which is just upgraded from the external storage module, and sends the image file to the configuration module of the FPGA to realize the loading of the FPGA.
5. The utility model provides a loading device is upgraded to FPGA many mirrors based on soft core processor which characterized in that, the device includes: the device comprises an upper computer, an interface transceiver module, an FPGA module, an external cache module, an external storage module and a CPLD module; wherein,
the upper computer is used for man-machine interaction and carrying out program upgrading and mirror image switching control;
the interface transceiving module is used for bidirectional communication interaction between the upper computer and the FPGA module;
the FPGA module is used for integrating the soft-core processor and the respective definition function modules;
the external cache module is used for temporarily storing the data to be processed by the system;
the external storage module is used for storing program file data of the FPGA;
and the CPLD module and the external mounting memory are used for storing the program file of the FPGA and communicating with the FPGA module to complete program upgrading.
6. The upgrade loading apparatus according to claim 5, wherein the FPGA module comprises: the system comprises a protocol stack module, a control module, a soft-core processor module and a configuration module; wherein,
the protocol stack module is used for analyzing the data transmitted by the interface, transmitting the command data to the soft-core processor module and transmitting the mirror image file data to the control module;
the control module is used for exchanging and controlling data with the protocol stack module, the soft-core processor module, the external cache module and the CPLD module;
the soft core processor module is used for scheduling tasks in the FPGA, managing a file system, analyzing and distributing control commands and controlling a work flow;
and the configuration module is used for entering an initialization state after receiving the program file data of the FPGA, then entering a user state and executing corresponding user application operation.
7. The upgrade loading apparatus according to claim 6, wherein the control module comprises: the device comprises a main control block, a cache control block and a main external storage interface control block; wherein,
the main control block is used for large data volume transmission, bus switching and multiplexing;
the cache control block is used for interacting with the main control block data and performing read-write access on the external cache module;
and the main external storage interface control block is used for carrying out data interaction with the main control block and controlling an external bus to carry out data transmission with the CPLD.
8. The upgrade loading device according to claim 5, wherein the CPLD module includes: the device comprises a storage control block, a soft-core processor module and a loading module; wherein,
the storage control block is used for performing data interaction with the soft-core processor module, the loading module, the FPGA module and the external storage module, and controlling, forwarding and storing upgrading program file data and upgrading command data;
the soft-core processor module is used for scheduling internal tasks of the CPLD, managing a file system, analyzing and distributing control commands and controlling a work flow;
the loading module is used for receiving the FPGA program file data sent by the storage control block, controlling an external bus and sending the program file data to the configuration module in the FPGA.
9. The upgrade loading apparatus according to claim 8, wherein the storage control block comprises: from the external storage interface control subblock, store the control subblock; wherein,
the slave external storage interface control sub-block is used for performing bus interaction with the FPGA, receiving upgrading program file data and upgrading command data of the FPGA, forwarding the program file data to the storage control sub-block, and forwarding the command data to the soft core processor module of the CPLD;
the storage control sub-block is used for receiving data from the external storage interface control sub-block, storing the data into the external storage module, receiving a control command of the soft-core processor module, reading program file data of the FPGA from the external storage module, and sending the program file data to the loading module.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510937954.XA CN105573789B (en) | 2015-09-07 | 2015-12-16 | The many image upgrade loading methods of FPGA and device based on soft-core processor |
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| PCT/CN2016/087212 WO2017041567A1 (en) | 2015-09-07 | 2016-06-27 | Fpga multi-mirror upgrade loading method and device based on soft core processor |
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| CN106598650A (en) * | 2016-11-25 | 2017-04-26 | 积成电子股份有限公司 | Device and method for online upgrade of FPGA program based on fiber communication |
| CN108415715A (en) * | 2018-02-12 | 2018-08-17 | 四川爱创科技有限公司 | Method for upgrading software based on scene analysis suitable for automatic vending machine |
| CN109240758A (en) * | 2018-07-25 | 2019-01-18 | 武汉精测电子集团股份有限公司 | A kind of method and microkernel architecture for supporting card i/f synchronous asynchronous unified call |
| CN109683985A (en) * | 2018-12-19 | 2019-04-26 | 中国电子科技集团公司第五十四研究所 | A kind of more image starting methods of DSP based on AIS order |
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| KR20180077163A (en) | 2018-07-06 |
| KR102504172B1 (en) | 2023-02-24 |
| WO2017041567A1 (en) | 2017-03-16 |
| CN105573789B (en) | 2017-08-08 |
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