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CN105575928A - 半导体装置和制造半导体装置的方法 - Google Patents

半导体装置和制造半导体装置的方法 Download PDF

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Publication number
CN105575928A
CN105575928A CN201510708562.6A CN201510708562A CN105575928A CN 105575928 A CN105575928 A CN 105575928A CN 201510708562 A CN201510708562 A CN 201510708562A CN 105575928 A CN105575928 A CN 105575928A
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China
Prior art keywords
semiconductor element
solder
welding material
parent metal
engaged
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Granted
Application number
CN201510708562.6A
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CN105575928B (zh
Inventor
门口卓矢
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Denso Corp
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Toyota Motor Corp
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Publication of CN105575928B publication Critical patent/CN105575928B/zh
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Abstract

一种半导体装置,包括:半导体元件;被接合构件,其被接合到半导体元件并且包括镍膜;以及接合层,其被接合至所述被接合构件并且包含2.0wt%或以上的铜,其中接合层包括焊料部分和Cu6Sn5部分,焊料部分的基体金属至少包含作为构成元素的锡并且包含单质的铜,并且Cu6Sn5部分与镍膜接触。

Description

半导体装置和制造半导体装置的方法
技术领域
本发明涉及一种半导体装置和制造半导体装置的方法。特别地,本发明涉及一种半导体元件的电极被接合到被接合构件的半导体装置。
背景技术
日本专利申请公开号2007-67158(JP2007-67158A)公开了一种半导体元件被接合到被接合构件的半导体装置。在JP2007-67158A中,半导体元件通过Sn-Cu焊料(锡和铜的混合合金焊料)来接合到被接合构件。组成焊料的Cu的比例被调整到3.0wt%到7.0wt%(重量百分比)。也就是,半导体元件通过Sn-3.0~7.0Cu焊料来接合到被接合构件。JP2007-67158A描述了当熔化的焊料凝固时,在被接合构件的表面上形成Cu6Sn5化合物。由于Cu6Sn5化合物的形成,防止了焊料和被接合构件之间的扩散。
如在JP2007-67158A中描述的,当使用包含低于0.9wt%的Cu的Sn-Cu焊料时,理论上,不在被接合构件的表面形成Cu6Sn5化合物。因此,JP2007-67158A描述了半导体元件通过包含0.9wt%或者以上的Cu的Sn-Cu焊料来接合到被接合构件。在该描述中,如上所述,更倾向于将Sn-Cu焊料中Cu的比例调整到3.0wt%到7.0wt%。
发明内容
但是,当组成Sn-Cu焊料的Cu的比例增加时,焊料的熔点(或者液相线温度)增加。例如,在Sn-3.0Cu焊料的情况中,液相线温度高于310℃。当使用具有高熔点(液相线温度)的焊料时,需要提高半导体元件的耐热性以防止半导体元件损坏。因此,需要Cu6Sn5化合物形成在被接合构件的表面上而不用提高半导体元件的耐热性的半导体装置。
根据本发明的一个方面,提供了一种半导体装置,包括:半导体元件;被接合构件,其被接合到半导体元件并且包括镍膜;以及接合层,其被接合到所述被接合构件并且包含2.0wt%或者以上的铜,其中接合层包括焊料部分和Cu6Sn5部分,焊料部分的基体金属至少包含作为构成元素的锡并包含单质的铜,以及Cu6Sn5部分与镍膜接触。
“焊料部分”指接合层的一部分,在该部分处半导体元件接合到被接合构件。另一方面,用于形成接合层的材料(也就是,熔化以形成接合层之前的材料)称作“焊接材料”并且区别于“焊料部分”。此外,“Cu6Sn5部分(或者Cu6Sn5)”包括其中一部分Cu由Ni替代的化合物。也就是,“Cu6Sn5部分(或者Cu6Sn5)”包括(Cu,Ni)6Sn5。例如,当使用添加Ni的Sn-Cu焊料时,Ni固溶于Cu6Sn5中以形成(Cu,Ni)6Sn5。Cu6Sn5和(Cu,Ni)6Sn5展现了基本上相同的作用。被接合构件不限于直接接合到半导体元件的构件,并且包括与接合到半导体元件的构件相接合的构件。也就是,本说明书中描述的被接合构件指直接或者间接接合到半导体元件的构件。
在半导体装置中,焊料部分包含基体金属中包含的单质的Cu。这暗示用于将半导体元件接合到被接合构件的焊接材料的基体金属包含单质的Cu。单质的Cu不构成基体金属。当焊接材料熔化并且接着凝固以接合半导体元件到被接合构件时,焊接材料的基体金属中包含的单质的Cu可以为形成Cu6Sn5部分的Cu成分。因此,在使用该焊接材料来接合期间,即使焊接材料的基体金属中的Cu的比例(以合金出现在基体金属中的Cu的比例)低时,也能够形成Cu6Sn5部分。例如,当半导体元件通过其中单质的Cu引入到基体金属中的焊接材料接合到被接合构件时,即使在焊接材料的基体金属中包含的作为合金的Cu的比例低于0.9wt%的情况中,Cu6Sn5部分也能够形成在接合层的一部分中。特别地,在该半导体装置中,接合层中包含的铜的比例为2.0wt%或者以上。以这一方式,当接合层包含2.0wt%或者以上的铜时,能够可靠地获得Cu6Sn5部分。此外,通过引入单质的Cu到焊接材料的基体金属中,焊接材料的基体金属中包含的作为合金的Cu的比例能够减少。因此,焊接材料的熔点(或者液相线温度)能够降低。因此,对于半导体元件,不一定要求高耐热性。
根据本发明的另一方面,提供了一种制造半导体装置的方法,包括:通过焊接材料来接合半导体元件到被接合构件,所述被接合构件包括镍膜,所述焊接材料的基体金属至少包含作为构成元素的锡并且包含单质的铜,在该单质的铜中铜的比例为2.0wt%或者以上。
附图说明
以下将参照所附附图来描述本发明的示例性实施例的特征、优点、以及技术和工业意义,其中相同的附图标记代表相同的元素,并且其中:
图1为示出半导体装置的示意图;
图2为示出图1中的由虚线包围的一部分的放大视图;
图3为Cu-Sn二元相图;
图4为示出图3的一部分(Sn:80到100)的放大视图;
图5为示出示例1中的半导体元件与被接合构件之间的接合界面的SEM图像;以及
图6为示出比较例1中的半导体元件与被接合构件之间的接合界面的SEM图像。
具体实施方式
参见图1,将描述半导体装置100。在半导体装置100中,半导体元件6布置在两个金属板2、10之间,并且各部件使用树脂8来模制。金属板2、10对应于半导体装置100的电极板。此外,金属板2、10对应于将半导体元件6的热散到半导体装置100外部的散热板。每个金属板2、10的一个表面裸露于树脂8的表面。在图1中,未示出连接到半导体元件6的端子、焊线以及类似物。
接合层4设置在半导体元件6与金属板2之间。更具体地,设置在半导体元件6的金属板2侧(此后,称作“后表面”)上的电极6a焊接到金属板2。此外,设置在半导体元件6的金属板10侧(此后,称作“前表面”)上的电极6b焊接到金属垫片14的后表面。垫片14的前表面焊接到金属板10的后表面。也就是,半导体元件6通过接合层4接合到金属板2,半导体元件6通过接合层16接合到垫片14,以及垫片14通过接合层12接合到金属板10。可以说金属板10间接接合到半导体元件6。金属板2、10和垫片14为接合构件的示例。
半导体元件6、金属板2、10、垫片14、以及接合层4、12、16的表面覆有底漆(未示出)。通过使用底漆,树脂8与半导体元件6、金属板2和10、垫片14、以及接合层4、12和16之间的接合性能提高。热固性聚酰亚胺树脂用作底漆,以及环氧树脂用作树脂8。
图2示意性地示出了金属板2与接合层4之间的界面。如图2中所示,金属板2包括Cu部分2b和Ni膜2a。Cu部分2b具有板形。Ni膜2a覆盖了Cu部分2b的表面。Ni膜2a的厚度调整为2μm到20μm。接合层4包括焊料部分4a和Cu6Sn5部分4b。在焊料部分4a中,Cu粒子20(单质的Cu)分散在作为基体金属的Sn-0.7Cu中。在以下描述中,Cu粒子20将被称作Cu球20。Cu部分和覆盖Cu部分的表面的Ni膜还设置在电极6a的表面上。因此,电极6a与接合层4之间的界面还具有与金属板2与接合层4之间的界面相同的配置。
焊料部分4a包含1.3wt%的Cu球20。此外,如上所述,因为焊料部分4a的基体金属为Sn-0.7Cu,基体金属包含作为合金的Cu。Cu与焊料部分4a的总重量的比例为2.0wt%。Cu6Sn5部分4b与Ni膜2a接触。Cu6Sn5部分4b的厚度调整为3μm到20μm。Cu6Sn5部分4b从焊接材料(包含1.3wt%的Cu球20的Sn-0.7Cu焊料)沉积,通过该焊接材料,金属板2和半导体元件6彼此接合。Cu6Sn5部分4b的厚度比焊料部分4a的厚度小得多。因此,金属板2和半导体元件6彼此接合之前的焊接材料的配置基本上与金属板2和半导体元件6彼此接合之后的焊料部分4a的配置相同。
将描述半导体元件6接合到金属板2的步骤。准备其中Ni膜形成于电极6a的表面上的半导体元件6,以及其中镍Ni电镀在Cu板的表面上的金属板2。接下来,半导体元件6的电极6a和金属板2通过焊接材料彼此接合。如上所述,焊接材料具有与焊料部分4a基本上相同的配置。也就是,焊接材料的基体金属为Sn-0.7Cu。Cu球20以分散于其中的状态包含在焊接材料的基体金属中。Cu与焊接材料的总重量的比例为2.0wt%。在接合步骤中,首先,焊接材料被布置成与金属板2的Ni膜2a和半导体元件6的电极6a接触。接下来,焊接材料通过加热来熔化并且接着凝固。通过使焊接材料凝固,形成接合层4。金属板2的Ni膜2a和半导体元件6的电极6a通过接合层4彼此接合。
当焊接材料凝固时,Cu6Sn5沉积在Ni膜2a的表面。结果,如图2中所示,形成Cu6Sn5部分4b。在相关技术中,当组成焊接材料的Cu的比例减少时,Cu6Sn5不沉积于Ni膜的表面上。另一方面,在实施例中,Cu球20分散在焊接材料的基体金属中。Cu球20可以为材料Cu6Sn5。因此,尽管构成焊接材料的Cu的比例低(0.7wt%),Cu6Sn5部分4b也能够在焊接材料的凝固期间形成。如上所述,包含基体金属和Cu球的焊接材料中的Cu的比例为2.0wt%。当焊接材料中的Cu的比例为2.0wt%时,Cu6Sn5部分4b能够可靠地形成。
通过包含Cu球20的焊接材料,焊接材料的基体金属中包含的作为合金的Cu的比例被压缩到较低的0.7wt%。以这一方式,通过压缩焊接材料的基体金属中包含的Cu的比例,焊接材料的熔点(或者液相线温度)能够降低。如图3中所示,Sn-0.7Cu的熔点为227℃,其比Sn-2.0Cu的液相线温度(270℃到280℃)更低。当半导体元件6和金属板2彼此接合时,应用于半导体元件6的温度能够减少到比将不包含Cu球的Sn-2.0Cu焊接材料用于接合的情况的温度更低。因此,使用根据实施例的方法,焊接步骤中应用于半导体元件6的温度能够降低。
如在金属板2中那样,在金属板10中,Ni被镀在Cu板的表面。在垫片14中,Ni被镀在Cu板的两个表面(前表面和后表面)上。此外,Ni膜形成在电极6b的表面上。电极6b和垫片14之间的接合部分和垫片14和金属板10之间的接合部分具有与半导体元件6和金属板2之间的接合部分基本相同的结构。因此,将使用对金属板2和接合层4之间的界面的说明来替代半导体元件6和接合层16之间的界面、垫片14和接合层16之间的界面、垫片14和接合层12之间的界面、以及金属板10和接合层12之间的界面的描述。
将描述半导体装置100的有益效果。如上所述,Cu6Sn5部分4b设置在焊料部分4a和Ni膜2a之间。因此,Cu6Sn5部分4b起阻挡层的作用。因此,即使当热从半导体元件6产生时,也能够抑制焊料部分4a和Ni膜2a之间的反应。当焊料部分4a和Ni膜2a之间的反应达到Cu部分2b时,金属板2会从半导体元件6脱落。由于Cu6Sn5部分4b的存在,能够防止这样的脱落。
此外,焊接材料包含Cu球20。结果,当焊接材料熔化时,能够抑制焊接材料的形状的显著变化。具体地,当焊接材料熔化时,焊接材料不从金属板2和半导体元件6之间的空隙流动,使得能够防止金属板2和半导体元件6之间的接触。换而言之,包含Cu球20的焊接材料起防止金属板2和半导体元件6之间接触的垫片的作用。
图5为示出当半导体元件和金属板彼此通过焊接材料接合时焊料部分和金属板(其上形成Ni膜的Cu板)之间的接合界面的SEM图像,在该焊接材料中,1.3wt%的Cu球被引入到Sn-0.7Cu形成的基体金属中(示例1)。此外,图6为示出当半导体元件和金属板彼此通过不包含铜球的Sn-0.7Cu形成的焊接材料接合时焊料部分和金属板之间的接合界面的SEM图像(比较例1)。
在示例1和比较例1中,因为焊接材料的基体金属相同(Sn-0.7Cu焊料),焊接材料的熔点相同。如图6中所示,在比较例1中,在Ni膜2a和焊料部分4a之间形成的并非Cu6Sn5层、而是Ni3Sn4层。这一结果显示:当基体金属中包含的Cu的比例低(0.7wt%)时,不形成Cu6Sn5层。在比较例1中,当通过驱动半导体装置增加接合层的温度时,焊料部分中的Sn扩散,并且Ni3Sn4层增长。
另一方面,在示例1中,Cu6Sn5部分4b形成在Ni膜2a和焊料部分4a之间。通过分散在Sn-0.7Cu的基体金属中的1.3wt%的Cu球,在半导体元件和金属板的接合期间,Cu6Sn5部分能够形成在金属板的表面上,而不增加温度。
在以上所述的实施例的示例的描述中,半导体元件和金属板通过如下焊接材料彼此接合,该焊接材料中,1.3wt%的Cu球分散在Sn-0.7Cu的基体金属中。但是,即使当半导体元件和金属板彼此通过如下焊接材料接合时也能够获得相同的效果,该焊接材料中,2.0wt%的Cu球分散在基体金属Sn(锡100%)中。在这一情况中,基体金属Sn的熔点为232℃,其比焊接材料Sn-2.0Cu的液相线温度(270℃到280℃)更低。
在以上所述的实施例的描述中,在半导体装置中,半导体元件6的电极6a、6b、金属板2、10、以及垫片14中的每个包括Cu部分(Cu板)和覆盖Cu部分的Ni膜。但是,半导体装置可以具有其中电极6a、6b、金属板2、10、以及垫片14中的至少一个包括Cu部分和覆盖Cu部分的Ni膜的结构。在半导体装置中,由热引起的接合部分中的缺陷的风险取决于制造步骤期间的热条件和环境温度、来自半导体元件的热产生等而变化。在半导体装置100中,缺陷很可能由于与半导体元件6直接接触的部分中的热而发生。也就是,在半导体装置100中,缺陷很可能发生在金属板2与半导体元件6之间的接合部分和半导体元件6与垫片14之间的接合部分中。特别地,缺陷很可能发生在半导体元件6与垫片14之间的接合部分中。本说明书中公开的涉及接合层(基体金属中包含单质的铜的焊料部分,以及与镍膜接触的Cu6Sn5部分)的技术可以仅仅应用于以上所述的其中很可能发生缺陷的部分。
将概述本说明书中公开的半导体装置中使用的焊接材料的特性。焊接材料包含:基体金属(此后,还称作“焊料基体金属”),其至少包含作为构成元素的锡;以及引入到焊料基体金属中的单质的铜。焊料基体金属中的锡的比例可以为100%(铜含量比例:0wt%)。此外,当焊料基体金属为Sn-Cu焊料时,焊料基体金属中的Cu含量比例可以为0.3wt%或者以上并且优选0.5wt%或者以上。更优选地,焊料基体金属为Sn-0.7Cu(Cu含量比例:0.7%)。此外,焊料基体金属中的Cu含量比例可以为7.6wt%或者以下,并且优选5.0wt%或者以下,并且更优选地,为4.0wt%或者以下。
将描述本说明书中公开的半导体装置的某些技术特性。下面的特征具有单独的技术意义。
半导体装置包括:半导体元件;被接合构件,其被接合到半导体元件并且包括镍膜;以及接合层,其被接合到该被接合构件。接合层可以包括:焊料部分;以及与镍膜接触的Cu6Sn5部分。焊料部分的基体金属至少可以包含作为构成元素的锡。此外,焊料部分可以在基体金属中包含单质的铜(Cu)。接合层中包含的Cu的比例可以为2.0wt%或者以上。
焊料部分的基体金属中的锡(Sn)的比例可以为100%。此外,焊料部分的基体金属可以为Cu和Sn的化合物(Sn-Cu焊料)。单质的Cu可以不构成焊料部分的基体金属。单质的Cu可以为微粒。在半导体元件和接合构件彼此接合之前,单质的Cu可以提前分散在焊接材料的基体金属中。当半导体元件和接合构件彼此接合时,Cu6Sn5部分可以沉积在被接合构件的表面(镍膜的表面)上。
当焊料部分的基体金属为Sn-Cu焊料时,基体金属中的Cu含量比例可以为0.3wt%或者以上并且优选0.5wt%或者以上。如能够从图3中清楚地,在Sn-0.3Cu焊料和Sn-0.5Cu焊料中,η(eta)相化合物(Cu6Sn5)在从液相到固相的相变化期间形成。通过调整Sn-Cu焊料中包含的Cu含量比例到0.3wt%或者以上,即使当焊接材料的基体金属中的单质的Cu的分散不充分时,Cu6Sn5部分也能够形成在镍膜的表面上。通过调整Cu含量比例到0.5wt%或者以上,Cu6Sn5部分能够更可靠地形成。此外,“Sn-Cu焊料”为包含作为主要成分的锡和铜的合金的一般术语,并且,除了锡和铜,可以进一步包含例如Ni、P(磷)、Bi(铋)、Sb(锑)、或者Ag(银)。
焊料部分的基体金属中的Cu含量比例可以为7.6wt%或者以下并且优选为5.0wt%或者以下,并且更优选4.0wt%或者以下。如图3和4中所示,当Sn-Cu焊料中的Cu含量比例高于7.6wt%时,ε(upsilon)相化合物(Cu3Sn)在从液相到固相的基体金属的相变化期间形成。另一方面,当Cu含量比例为7.6wt%或者以下时,η(eta)相化合物(Cu6Sn5)在从液相到固相的基体金属的相变化期间形成。通过调整焊料部分的基体金属中的Cu含量比例到7.6wt%或者以下,Cu6Sn5部分能够可靠地形成。
如图4中所示,其中Cu含量比例为5.0wt%的Sn-Cu焊料(Sn-5.0Cu焊料)具有350℃的熔点。用于半导体元件的元件保护膜会在高于350℃的温度处恶化。因此,当Cu含量比例高于5.0wt%时,需要采取对策,以抑制元件保护膜的恶化。通过调整焊料部分(焊接材料)的基体金属中的Cu含量比例到5.0wt%或者以下,元件保护膜的恶化能够在不采取任何特殊对策的情况下被抑制。
如图4中所示,其中Cu含量比例为4.0wt%的Sn-Cu焊料(Sn-4.0Cu焊料)具有330℃的熔点。半导体元件中使用的电极会取决于其材料而在高于330℃的温度处破裂。因此,当Cu含量比例高于4.0wt%时,需要采取对策,以防止电极的破裂。例如,需要限制电极的材料。通过调整Cu含量比例为4.0wt%或者以下,能够在不采取任何特殊对策的情况下获得其中电极的破裂被抑制的半导体装置。更优选地,焊料部分的基体金属(以及焊接材料的基体金属)为Sn-0.7Cu(Cu含量比例:0.7%),而非尽可能地降低Sn-0.1~7.6Cu中的焊接材料的基体金属的熔点。
接合层(基体金属、单质的Cu、以及焊料部分的Cu6Sn5部分)中包含的Cu的比例可以为2.0wt%或者以上并且优选3.0wt%或者以上。如从图3和4中清楚地看到的,在Sn-2.0Cu焊料中,η(eta)相化合物(Cu6Sn5)在从液相到固相的相变化期间形成。也就是,通过调整接合层中包含的Cu的比例到2.0wt%或者以上,Cu6Sn5部分能够可靠地形成在镍膜的表面上。此外,通过调整接合层中包含的Cu的比例到3.0wt%或者以上,Cu6Sn5部分能够更稳定地形成在镍膜的表面。单质的Cu的比例可以取决于组成焊料部分的基体金属的Cu的比例来调整。如上所述,从可靠地形成Cu6Sn5部分的角度,接合层中包含的Cu的比例优选为7.6wt%或者以下。
在上文中,已经具体描述了本发明的具体示例。但是,这些示例仅仅是示例性的并且不限制权利要求。权利要求中描述的技术包括以上所述的具体示例的各种变化和改变。本说明书和附图中描述的技术特征展示了当被单独或按其组合使用时的技术意义,并且不限于提交申请时的权利要求中描述的组合。本说明书和附图中例证的技术同时达到多个目标,并且技术意义通过达到目标之一来获得。

Claims (6)

1.一种半导体装置,其特征在于包括:
半导体元件;
被接合构件,其被接合至所述半导体元件并且包括镍膜;以及
接合层,其被接合至所述被接合构件并且包含2.0wt%或以上的铜;
其中
所述接合层包括焊料部分和Cu6Sn5部分;
所述焊料部分的基体金属至少包含作为构成元素的锡并且包含单质的铜,以及
所述Cu6Sn5部分与所述镍膜接触。
2.根据权利要求1所述的半导体装置,其特征在于:
所述接合层中包含的铜的比例为7.6wt%或以下。
3.根据权利要求1或2所述的半导体装置,其特征在于:
所述基体金属为包含作为主要成分的锡和铜的合金。
4.根据权利要求3所述的半导体装置,其特征在于:
所述基体金属为包含作为主要成分的Sn-0.7Cu的合金。
5.一种制造半导体装置的方法,其特征在于包括:
通过焊接材料将半导体元件接合至被接合构件,所述被接合构件包括镍膜,所述焊接材料的基体金属至少包含作为构成元素的锡并且包含单质的铜,在该单质的铜中铜的比例为2.0wt%或以上。
6.根据权利要求5所述的方法,其特征在于:
通过所述焊接材料来将所述半导体元件接合至所述被接合构件上的所述镍膜。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111435646A (zh) * 2019-01-11 2020-07-21 丰田自动车株式会社 半导体装置及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6287759B2 (ja) 2014-10-30 2018-03-07 トヨタ自動車株式会社 半導体装置とその製造方法
JP6281468B2 (ja) 2014-10-30 2018-02-21 トヨタ自動車株式会社 半導体装置とその製造方法
JP6330786B2 (ja) 2015-11-16 2018-05-30 トヨタ自動車株式会社 半導体装置の製造方法
JP6638626B2 (ja) * 2016-11-21 2020-01-29 トヨタ自動車株式会社 半導体装置の製造方法
JP7428595B2 (ja) * 2020-06-08 2024-02-06 日立Astemo株式会社 半導体装置、および半導体装置の製造方法
US11610861B2 (en) * 2020-09-14 2023-03-21 Infineon Technologies Austria Ag Diffusion soldering with contaminant protection
DE112022000145T5 (de) * 2021-05-18 2023-07-06 Fuji Electric Co., Ltd. Halbleitervorrichtung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040007384A1 (en) * 2002-03-08 2004-01-15 Hitachi, Ltd. Electronic device
EP1760783A2 (en) * 2005-08-31 2007-03-07 Hitachi, Ltd. Semiconductor device and automotive ac generator
US20090243089A1 (en) * 2008-03-31 2009-10-01 Infineon Technologies Ag Module including a rough solder joint
CN101958259A (zh) * 2009-07-13 2011-01-26 Lsi公司 通过添加铜对焊料互连的改善

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6844621B2 (en) * 2002-08-13 2005-01-18 Fuji Electric Co., Ltd. Semiconductor device and method of relaxing thermal stress
JP2005340275A (ja) 2004-05-24 2005-12-08 Denso Corp 電子部品接合体、その製造方法、およびそれを含む電子装置
CN101432095B (zh) 2006-04-28 2013-01-16 株式会社电装 泡沫焊锡和电子器件
US20100291399A1 (en) 2006-09-01 2010-11-18 Rikiya Kato Lid for a functional part and a process for its manufacture
US8211752B2 (en) 2007-11-26 2012-07-03 Infineon Technologies Ag Device and method including a soldering process
JP2010179336A (ja) * 2009-02-05 2010-08-19 Toyota Central R&D Labs Inc 接合体、半導体モジュール、及び接合体の製造方法
JP2011044624A (ja) 2009-08-24 2011-03-03 Hitachi Ltd 半導体装置および車載用交流発電機
JP5517694B2 (ja) 2010-03-29 2014-06-11 株式会社 日立パワーデバイス 半導体装置
US8802553B2 (en) 2011-02-10 2014-08-12 Infineon Technologies Ag Method for mounting a semiconductor chip on a carrier
JP5557788B2 (ja) 2011-04-07 2014-07-23 株式会社 日立パワーデバイス 電子装置の製造方法
WO2013133134A1 (ja) * 2012-03-07 2013-09-12 トヨタ自動車株式会社 半導体装置及びその製造方法
JP5677346B2 (ja) 2012-03-22 2015-02-25 株式会社日立製作所 半導体素子、半導体装置、半導体装置の製造方法及び接続材料
US8814030B2 (en) * 2012-04-17 2014-08-26 Toyota Motor Engineering & Manufacturing North America, Inc. Improvements of long term bondline reliability of power electronics operating at high temperatures
JP6061248B2 (ja) * 2013-03-29 2017-01-18 国立研究開発法人産業技術総合研究所 接合方法及び半導体モジュールの製造方法
JP6287759B2 (ja) 2014-10-30 2018-03-07 トヨタ自動車株式会社 半導体装置とその製造方法
JP6281468B2 (ja) * 2014-10-30 2018-02-21 トヨタ自動車株式会社 半導体装置とその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040007384A1 (en) * 2002-03-08 2004-01-15 Hitachi, Ltd. Electronic device
EP1760783A2 (en) * 2005-08-31 2007-03-07 Hitachi, Ltd. Semiconductor device and automotive ac generator
US20090243089A1 (en) * 2008-03-31 2009-10-01 Infineon Technologies Ag Module including a rough solder joint
CN101958259A (zh) * 2009-07-13 2011-01-26 Lsi公司 通过添加铜对焊料互连的改善

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111435646A (zh) * 2019-01-11 2020-07-21 丰田自动车株式会社 半导体装置及其制造方法
CN111435646B (zh) * 2019-01-11 2023-09-08 株式会社电装 半导体装置及其制造方法

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