CN105575830A - 半导体装置和制造半导体装置的方法 - Google Patents
半导体装置和制造半导体装置的方法 Download PDFInfo
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- CN105575830A CN105575830A CN201510712706.5A CN201510712706A CN105575830A CN 105575830 A CN105575830 A CN 105575830A CN 201510712706 A CN201510712706 A CN 201510712706A CN 105575830 A CN105575830 A CN 105575830A
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- solder
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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- General Physics & Mathematics (AREA)
Abstract
本发明提供一种制造半导体装置的方法,其包括:将包含至少锡的焊料材料布置在半导体元件和设置有镍层和铜层的接合构件之间,使得焊料材料接触铜层,镍层设置在接合构件的表面上,并且铜层设置在镍层的表面的至少一部分上;以及使用铜层和焊料材料中的锡来熔化以及凝固焊料材料以在镍层的表面上形成Cu6Sn5。本发明还提供一种半导体装置。
Description
技术领域
本发明涉及一种半导体装置和制造半导体装置的方法。本发明尤其涉及一种其中半导体元件的电极接合至接合构件的半导体装置。
背景技术
日本专利申请公开第2007-67158号(JP2007-67158A)公开了一种半导体装置,其中半导体元件接合至接合构件。在JP2007-67158A中,半导体元件通过Sn-Cu焊料(锡和铜的混合合金焊料)接合至接合构件,在所述接合构件上形成镍层。包含在Sn-Cu焊料中的Cu的比例调节为3.0wt%至7.0wt%(重量百分比)。也即,半导体元件通过Sn-3.0至7.0Cu焊料接合至接合构件。JP2007-67158A描述了,当凝固熔化的焊料时,Cu6Sn5化合物形成在镍层的表面上。Cu6Sn5化合物防止镍层中的镍以及Sn-Cu焊料中的Sn之间的相互扩散。
正如在JP2007-67158A中描述的,当使用包含低于0.9wt%的Cu的Sn-Cu焊料时,理论上不形成Cu6Sn5化合物。因此,JP2007-67158A描述了半导体元件通过包含0.9wt%或者更高的Cu的Sn-Cu焊料接合至接合构件。在说明书中,如上所述,更优选地,在Sn-Cu焊料中Cu的比例调节为3.0wt%至7.0wt%。
发明内容
但是,当构成Sn-Cu焊料的Cu的比例增加时,焊料的熔点(或者液相线温度)增加。例如,在Sn-3.0Cu焊料的情形下,液相线温度高于310℃。当使用具有高熔点(液相线温度)的焊料时,有必要改善半导体元件的耐热性以防止半导体元件被破坏。因此,提供了制造半导体装置的方法,该方法能够在实现在接合构件的表面上形成Cu6Sn5化合物的同时将焊料的熔点(或者液相线温度)抑制得低。此外,还提供了半导体装置。
根据本发明的第一方案,提供了制造半导体装置的方法,该方法包括:将包含至少锡的焊料材料布置在半导体元件和设置有镍层以及铜层的接合构件之间,使得焊料材料与铜层接触,镍层设置在接合构件的表面上,并且铜层设置在镍层的表面的至少一部分上;以及使用焊料材料中的锡和铜层来熔化以及凝固焊料材料以在镍层的表面上形成Cu6Sn5。
在本说明书中描述的“焊料材料”指的是在熔化之前的材料,并且当熔化时用来将半导体元件和接合构件彼此接合。另一方面,接合层的经此将半导体元件和接合构件彼此接合的一部分称为“焊料部分”并且区别于焊料材料,所述接合层的该部分是将半导体元件和接合构件彼此接合之后(也即,在焊料材料凝固之后)的材料。“与焊料材料接触的铜”并不限于设置在镍层的表面上的铜层中的铜。“与焊料材料接触的铜”包括除了镍层的表面之外的区域的铜(例如,半导体元件的电极的表面),只要其在布置步骤期间与焊料材料相接触。此外,“Cu6Sn5部分(或者Cu6Sn5)”包括其中部分Cu用Ni取代的化合物。也即,“Cu6Sn5部分(或者Cu6Sn5)”包括(Cu,Ni)6Sn5。例如,当使用添加了Ni的Sn-Cu焊料时,Ni在Cu6Sn5中形成固溶体以形成(Cu,Ni)6Sn5。Cu6Sn5以及(Cu,Ni)6Sn5呈现大致相同的功能。接合构件并不限于直接接合至半导体元件的构件,而是包括接合至与半导体元件接合的构件(第一构件)的构件(第二构件)。也即,在本说明书中描述的接合构件指的是直接或者间接接合至半导体元件的构件。当使用上述方法将第一构件和第二构件彼此接合时,实际上,焊料材料布置于第一构件和第二构件之间。在半导体元件和接合构件之间布置焊料材料的布置步骤包括在接合至半导体元件的第一构件,以及第二构件之间布置焊料材料。
在上述制造方法中,在焊料材料和铜层彼此接触的状态下熔化以及凝固焊料材料。当焊料材料熔化、然后凝固以接合半导体元件至接合构件时,接触焊料材料的铜层可以是用于形成Cu6Sn5部分的Cu成分。因此,即使当包含在焊料材料中的Cu的比例低时,仍能够获得Cu6Sn5部分。通过将包含在焊料材料中的Cu的比例抑制得低,能够降低焊料材料的熔点(或者液相线温度)。Cu6Sn5部分沉积在镍层的表面上。根据上述制造方法,即使当使用理论上不能够形成Cu6Sn5的焊料材料时(具有较低铜含量以及较低熔点或者液相线温度),仍能够在镍层的表面上形成Cu6Sn5部分。也即,能够使用具有低熔点(或者液相线温度)的焊料材料,同时实现在接合构件的表面上形成Cu6Sn5化合物。此外,在上述制造方法中,当半导体元件和接合构件接合至彼此时,能够抑制半导体元件暴露于高温。因此,半导体元件不要求高耐热性。
根据本发明的第二方案,提供了半导体装置,其包括:半导体元件;接合构件,其上设置有镍层;以及接合层,接合构件通过所述接合层接合至半导体元件,其中接合层包括焊料部分和Cu6Sn5部分,焊料部分包含至少锡,Cu6Sn5部分设置在镍层和焊料部分之间,Cu6Sn5部分与镍层的表面的一部分接触并且不与镍层的表面的其它部分接触,以及接合层中包含的铜的比例是2.0wt%或者更高。
根据本发明的第三方案,提供了半导体装置,其包括:半导体元件;接合构件,在该接合构件上上设置有镍层;以及接合层,接合构件通过所述接合层与半导体元件接合,其中接合层包括焊料部分和Cu6Sn5部分,焊料部分包含锡和铜,以及Cu6Sn5部分设置在镍层和焊料部分之间,焊料部分中包含的铜的重量低于焊料部分的重量的0.9wt%。
附图说明
下文将参考附图描述本发明的示例性实施方式的特征、优势以及技术及工业重要性,其中类似标记指代相似元件,并且其中:
图1是示出半导体装置的示意图;
图2是示出由虚线包围的图1的部分的放大视图;
图3是示出镍层和Cu6Sn5部分之间的接合界面的特性的图;
图4是示出制造半导体装置的方法的图;
图5是Cu-Sn二元相图;
图6是示出图5的部分(Sn:80至100)的放大视图;
图7是示出在实施例1的半导体装置中半导体元件和接合构件之间的接合界面的SEM图像;
图8是示出在重复加热实施例1的半导体装置之后半导体元件和接合构件之间的接合界面的SEM图像;
图9是示出在对比实施例1的半导体装置中半导体元件和接合构件之间的接合界面的SEM图像;以及
图10是示出在重复加热对比实施例1的半导体装置之后半导体元件和接合构件之间的接合界面的SEM图像。
具体实施方式
参考图1,将描述半导体装置100。在半导体装置100中,半导体元件6布置于两个金属板2、10之间,且部件通过模制树脂8而形成。金属板2、10对应于半导体装置100的电极板。此外,金属板2、10对应于散热片,散热片消散半导体元件6的热至半导体装置100的外部。每个金属板2、10的一个表面从树脂8的表面露出。在图1中,连接至半导体元件6的端子、焊线等未示出。
接合层4设置在半导体元件6和金属板2之间。更具体来说,半导体元件6的设置在金属板2侧(下文,称为“背面”)的电极6a焊接至金属板2。此外,半导体元件6的设置在金属板10侧(下文,称为“正面”)的电极6b焊接至金属间隔件14的背面。间隔件14的正面焊接至金属板10的背面。也即,半导体元件6通过接合层4接合至金属板2,半导体元件6通过接合层16接合至间隔件14,间隔件14通过接合层12接合至金属板10。可以这样说,金属板10间接接合至半导体元件6。金属板2、10和间隔件14是接合构件的示例。
半导体元件6、金属板2、10、间隔件14、以及接合层4、12、16的表面涂覆有底漆(未示出)。通过使用底漆,改善了树脂8,以及半导体元件6、金属板2、10、间隔件14以及接合层4、12以及16之间的接合特性。使用热固性聚酰亚胺树脂作为底漆,使用环氧基树脂作为树脂8。
图2示意地示出了金属板2和接合层4之间的界面。如图2所示,金属板2包括Cu板2b和Ni层2a。Ni层2a覆盖Cu板2b的表面。Ni层2a的厚度调节为2μm至20μm。接合层4包括焊料部分4a和Cu6Sn5部分4b。Cu6Sn5部分4b将焊料部分4a和Ni层2a彼此分离。Cu6Sn5部分4b防止焊料部分4a和Ni层2a之间的接触。如图3所示,Cu6Sn5部分4b包括:接触部分18a,其接触Ni层2a的表面20;以及非接触部分18b,其不接触Ni层2a的表面20。表面20和非接触部分18b之间的空间是中空的。换句话说,在Cu6Sn5部分4b和Ni层2a之间的空间的部分存在空隙。Cu部分和覆盖Cu部分的表面的Ni膜还设置在电极6a的表面上。因此,电极6a和接合层4之间的界面也具有与金属板2和接合层4之间的界面相同的构造。
参考图4,将描述接合半导体元件6至金属板2的步骤。首先,Ni层2a形成在Cu板2b的表面上。结果,获得其上设置有Ni层2a的金属板2。接下来,Cu层22形成在Ni层2a的表面上的预定位置处。接下来,焊料材料4布置于半导体元件6的背面电极6a和Cu层22之间(布置步骤)。此时,布置焊料材料4以便与Cu层22接触。焊料材料布置在Cu层22的表面的整个区域上。焊料材料4是Sn-0.7Cu焊料,其厚度调节为0.15mm。Cu层22的厚度调节为1.4μm,Cu层22的重量相对于焊料材料4的重量以及Cu层22的重量之和(接合材料的总重量)为1.3wt%。也即,包含在焊料材料4中的铜的重量和Cu层22的重量之和(铜的总重量)相对于接合材料的总重量为2.0wt%。
Cu层可以形成在Ni层2a的表面的整个区域上,焊料材料4可以布置于Cu层的表面上的预定位置处(在Cu层的表面的一部分)。在该情况下,当Cu层的厚度调节为1.4μm时,Cu层的重量大于其中Cu层设置在预定位置处的上述实施例的Cu层的重量。但是,铜的总重量指的是包含在焊料材料4中的铜的重量和在接触焊料材料4的区域中Cu层的重量之和。此外,接合材料的总重量指的是焊料材料4的重量和在接触焊料材料4的区域中Cu层的重量之和。因此,即使当Cu层形成在Ni层2a的表面的整个区域上时,以及当焊料材料4布置于Cu层的表面上的预定位置时,通过调节Sn-0.7Cu焊料(焊料材料)的厚度为0.15mm以及调节Cu层的厚度为1.4μm,可将铜的总重量调节为相对于接合材料的总重量为1.3wt%。也即,在不接触焊料材料4的区域中Cu层的重量不包括在接合材料的总重量和铜的总重量中。
接下来,在230℃下对焊料材料4执行热处理,并且熔化以及凝固焊料材料4(热处理步骤)。当凝固焊料材料4时,Cu层22的Cu与焊料材料4反应以形成Cu6Sn5。结果,如图2所示,Cu6Sn5部分4b沉积在Ni层2a的表面上。在现有技术中,即使当金属板2和半导体元件6通过Sn-0.7Cu焊料彼此接合时,Cu6Sn5也不沉积在Ni层2a的表面上。另一方面,在实施方案中,Cu层22形成在Ni层2a的表面上,在焊料材料4接触Cu层22的状态下熔化以及凝固焊料材料4。Cu层22可以是Cu6Sn5材料。因此,虽然使用具有低的Cu比例的焊料材料(Sn-0.7Cu焊料),但是仍能够在凝固焊料材料期间形成Cu6Sn5部分4b。如上所述,铜的总重量相对于接合材料的总重量为2.0wt%。当铜的总重量相对于接合材料的总重量为2.0wt%时,能够可靠地形成Cu6Sn5部分4b。
在实施方案中,通过接合半导体元件6至金属板2来移除Cu层22的整个区域。因此,如图3所示,获得其中Ni层2a和Cu6Sn5部分4b直接接触彼此的构造。通过移除Cu层22的整个区域,Ni层2a和Cu6Sn5部分4b局部彼此不接触。也即,Cu6Sn5部分4b包括:接触部分18a,其接触Ni层2a;以及非接触部分18b,其不接触Ni层2a。在非接触部分18b中,在Cu6Sn5部分4b和Ni层2a之间形成空隙。但是,空隙由Ni层2a和Cu6Sn5部分4b包围并且不连接至焊料部分4a。因此,防止了焊料部分4a和Ni层2a之间的相互扩散。
如上所述,通过在Ni层2a的表面上提供Cu层22,作为合金包含在焊料材料4中的Cu的比例被抑制为低至0.7wt%。通过抑制包含在焊料材料中的Cu的比例,能够降低焊料材料的熔点(或者液相线温度)。如图5和图6所示,Sn-0.7Cu焊料的熔点是227℃,该熔点低于Sn-2.0Cu焊料的液相线温度(270℃至280℃)。在根据实施方案的方法中,当半导体元件6和金属板2接合至彼此时,无需提供Cu层22,施加至半导体元件6的温度能够降低至低于当使用Sn-2.0Cu焊料用于接合的情形时的温度。因此,利用根据实施方案的方法,能够降低在焊接步骤中施加至半导体元件6的温度。
正如在金属板2中,在金属板10中,Ni电镀在Cu板的表面上。在间隔件14中,Ni电镀在Cu板的两个表面上(正面和背面)。此外,Ni膜形成在电极6b的表面上。电极6b和间隔件14之间的接合部分以及间隔件14和金属板10之间的接合部分具有与半导体元件6和金属板2之间的接合部分大致相同的结构。因此,对半导体元件6和接合层16之间的界面,间隔件14和接合层16之间的界面,间隔件14和接合层12之间的界面,以及金属板10和接合层12之间的界面的描述将由对金属板2和接合层4之间的界面的描述代替。
将描述半导体装置100的有利效果。如上所述,Cu6Sn5部分4b设置在焊料部分4a和Ni层2a之间。因此,Cu6Sn5部分4b起到阻挡层的作用。因此,即使当从半导体元件6产生热时,也能够抑制焊料部分4a的锡和Ni层2a的镍之间的相互扩散。通过提供Cu6Sn5部分4b,能够抑制在半导体元件6和金属板2之间的界面上形成锡和镍的化合物。通过在半导体元件6和金属板2之间的界面上形成锡和镍的化合物,半导体装置被加热以及冷却。因此,Ni层2a的改性进行。当Ni层2a的改性到达Cu板2b时,金属板2可以从半导体元件6剥离。因为Cu6Sn5部分4b存在于焊料部分4a和Ni层2a之间,所以能够防止这种剥离。此外,在半导体装置100中,Cu层22设置在Ni层2a的表面上。结果,可以使用具有低的Cu比例的焊料材料来形成Cu6Sn5部分4b。因此,能够降低在焊接步骤中施加至半导体元件6的温度。
参考图7至图10,将描述实施例1的半导体装置的特性。图7和图8示出了实施例1的半导体装置的检查结果。图9和10示出了对比实施例1的半导体装置的检查结果。图7至图10中每个都示出当半导体元件接合至金属板时焊料部分和金属板之间的接合界面的SEM图像。
在实施例1中,通过使用镍对Cu板的表面进行化学镀而在Cu板的表面上形成具有7.0μm的厚度的Ni层(NiP)作为金属板,通过在Ni层的表面上喷溅来形成具有1.4μm厚度的Cu层。作为焊料材料,使用具有0.15mm的厚度的Sn-0.7Cu焊料。图7示出了在布置焊料材料在半导体元件和金属板之间,加热焊料材料至230℃,以及冷却焊料材料至室温之后,焊料部分4a和Cu板2b之间的接合界面。图8示出了在执行4个周期的热处理之后焊料部分4a和Cu板2b之间的接合界面,在热处理中,将加热图7的焊料部分4a至230℃以及冷却焊料部分4a至室温的步骤设定为一个周期。
在对比实施例1中,通过使用镍对Cu板的表面进行化学镀而在Cu板的表面上形成具有7.0μm的厚度的Ni层(NiP)作为金属板。如在实施例1的情形下一样,使用具有0.15mm的厚度的Sn-0.7Cu焊料作为焊料材料。也即,实施例1与对比实施例1的不同之处在于,Cu层形成在Ni层的表面上。图9示出了在布置焊料材料于半导体元件和金属板之间,加热焊料材料至230℃,以及冷却焊料材料至室温之后焊料部分和Cu板2b之间的接合界面。图10示出了在执行4个周期的热处理之后焊料部分和Cu板2b之间的接合界面,在热处理中,将加热图9的焊料部分4a至230℃以及冷却焊料部分4a至室温的步骤设定为一个周期。
如图7所示,在实施例1中,Cu6Sn5部分4b形成在Ni层2a和焊料部分4a之间。如图8所示,即使当重复执行热处理时,Cu6Sn5部分4b也起到阻挡层的作用以便防止焊料部分中的Sn扩散至Ni层2a。
另一方面,如图9所示,在对比实施例1中,不是Cu6Sn5部分4b而是Ni3Sn4层和Ni3SnP层形成在Ni层2a和焊料部分4a之间。在Ni层的表面上(NiP)对Ni3P进行改性。此外,如图10所示,当重复执行四次热处理时,Ni3P生长,并且Ni层(NiP)的大致整个区域都改性为Ni3P。当Ni3P到达Cu板2b时,Cu板2b可以从焊料部分4a剥离。
在实施例1和对比实施例1中,因为焊料材料相同(Sn-0.7Cu焊料),焊料材料的熔点相同。如图9所示,在对比实施例1中,Cu6Sn5层未形成在Ni层和焊料部分之间。该结果表明:当构成焊料材料的Cu的比例低(0.7wt%)时,不形成Cu6Sn5层。另一方面,在实施例1中,虽然焊料材料与对比实施例1的焊料材料相同,但是Cu6Sn5部分4b形成在Ni层和焊料部分之间。通过在Ni层的表面上形成铜层,Cu6Sn5部分能够形成在Ni层的表面上而无需在半导体元件和金属板之间的接合期间增加温度。
在上述实施方式中,Cu层22的厚度调节为1.4μm,而焊料材料4(Sn-0.7Cu焊料)的厚度调节为0.15mm。结果,铜的总重量被调节成相对于接合材料的总重量为2.0wt%。但是,例如,可以使用Sn焊料(Sn100%)作为焊料材料。当使用Sn焊料时,通过调节Cu层的厚度为2.5μm,铜的总重量能够被调节成相对于接合材料的总重量为2.0wt%。在该情况下,Sn焊料的熔点是232℃,该熔点低于Sn-2.0Cu焊料的液相线温度(270℃至280℃)。铜的总重量相对于接合材料的总重量可以高于2.0wt%。在该情况下,可以增加Cu层的厚度。能够根据焊料材料的厚度、包含在焊料材料中的Cu的比例、以及Cu相对于接合材料的总重量的期望比例来计算Cu层的厚度。
在上述实施方式中,由于不接触Ni层2a的非接触部分18b,在Cu6Sn5部分4b和Ni层2a之间形成空隙。但是,铜可以存在于非接触部分18b和Ni层2a之间。铜可以是在Ni层2a的表面上设置的Cu层22的残余物。
在上述实施方式中,铜层22设置在Ni层2a的表面上,Ni层和铜层进一步设置在半导体元件6的电极6a的表面上。因此,在电极6b和焊料部分4之间的区域(参见图1)中获得其中在Ni层的表面上形成Cu6Sn5的构造。在该情况下,包含在焊料材料中的铜的重量、包含在铜层22中的铜的重量以及包含在电极6a的表面上的铜层中的铜的重量的总和相对于接合材料的总重量(包括在电极6a的表面上的铜层的重量)可以为2wt%或者更高。可以仅在金属板2中的Ni层2a的表面上设置铜层22而无需在电极6a的表面上提供Ni层和铜层。
类似地,在上述实施方案的描述中,在半导体装置中,半导体元件6的每个电极6a、6b、金属板2、10以及间隔件14都包括Cu部分(Cu板)以及覆盖Cu部分的表面的Ni膜。但是,半导体装置可以具有这样的结构:其中,电极6a、6b、金属板2、10以及间隔件14中的至少一个包括Cu部分以及覆盖Cu部分的表面的Ni膜。在半导体装置中,因热引起的接合部分中有缺陷的风险取决于制造步骤期间的加热条件和环境温度、来自半导体元件的发热等而变化。在半导体装置100中,由于在直接接触半导体元件6的部分中的热,缺陷可能发生。也即,在半导体装置100中,缺陷可能发生在金属板2和半导体元件6之间的接合部分以及半导体元件6和间隔件14之间的接合部分中。尤其,缺陷可能发生在半导体元件6和间隔件14之间的接合部分中。公开于本说明书中的涉及接合层(在基本金属中包含单质铜的焊料部分,以及接触镍层的Cu6Sn5部分)的技术可以仅应用至可能发生缺陷的上述部分。
将描述公开于本说明书中的半导体装置以及制造半导体装置的方法的一些技术特性。以下特征具有各自的技术重要性。
半导体装置可以包括:半导体元件;接合构件,Ni层设置在接合构件上;以及接合层,接合构件通过接合层接合。接合层包括焊料部分和Cu6Sn5部分。焊料部分可以包含至少锡。Cu6Sn5部分可以设置在Ni层和焊料部分之间。Cu6Sn5部分的一部分可以接触Ni层的表面,Cu6Sn5部分的其他部分可不接触Ni层的表面。包含在接合层中的Cu的比例可以为2.0wt%或者更高。包含在焊料部分中的铜的重量相对于焊料部分的重量可以低于0.9wt%。
制造在其中半导体元件和接合构件彼此接合的半导体装置的方法包括布置步骤和热处理步骤。在布置步骤中,焊料材料可以布置于半导体元件和接合构件之间。Ni层可以设置在接合构件的表面上,铜层可以设置在Ni层的表面的至少一部分上。焊料材料可以包含至少锡。在布置步骤中,焊料材料可以接触铜层。在热处理步骤中,可以熔化以及凝固焊料材料。在热处理步骤中,由于铜层和在焊料材料中的锡,Cu6Sn5可以形成在Ni层的表面上。包含在焊料材料中的铜的重量和在布置步骤中与所述焊料材料接触的区域中的铜的重量的总和(铜的总重量)相对于焊料材料的重量和在接触焊料材料的区域中的铜的重量的总和(接合材料的总重量)可以为2.0wt%或者更高。
在布置步骤之前可以在接合构件的表面上形成Ni层和铜层。Ni层可以电镀在接合构件的表面上。或者,Ni层可以化学镀在接合构件的表面上。Ni层可以通过喷溅在接合构件的表面上而形成。类似地,铜层可以电镀或者化学镀在Ni层的表面上。铜层可以通过喷溅在Ni层的表面上而形成。
在接合层中焊料部分的材料可以与通过其将半导体元件和接合构件接合至彼此的焊料材料的材料相同。在焊料材料中锡的比例可以为100%(锡焊料)。焊料材料可以是包含铜的Sn-Cu焊料。当焊料材料是Sn-Cu焊料时,构成焊料材料的铜的比例可以为0.3wt%或者更高,优选0.5wt%或者更高。更优选地,焊料材料为Sn-0.7Cu(Cu含量比:0.7%)。正如从图5和图6清楚可见的,在Sn-0.3Cu焊料、Sn-0.5Cu焊料以及Sn-0.7Cu焊料中,在从液相至固相的相变换期间形成了η(eta)相化合物(Cu6Sn5)。包含在Sn-Cu焊料中的铜的比例调节为0.3wt%或者更高。结果,即使当在Ni层上设置的铜层的厚度有变化时,也能够可靠地形成Cu6Sn5部分。通过调节铜的比例为0.5wt%或者更高,能够更可靠地形成Cu6Sn5部分。在Sn-Cu焊料中,Sn-0.7Cu焊料具有最低熔点。从在接合步骤中抑制半导体元件暴露于高温的观点来看,更优选地,焊料材料为Sn-0.7Cu焊料(Cu含量比:0.7%)。此外,“Sn-Cu焊料”是用于包含锡和铜作为主要成分的合金的一般术语,并且除了锡和铜之外可进一步包含例如Ni、P(磷)、Bi(铋)、Sb(锑)或者Ag(银)。
构成焊料材料的铜的比例可以为7.6wt%或者更低,优选地为5.0wt%或者更低,更优选地为4.0wt%或者更低。如图5和图6所示,当Sn-Cu焊料中Cu含量比高于7.6wt%时,在基本金属从液相至固相的相变换期间形成了ε(epsilon)相化合物(Cu3Sn)。另一方面,当Cu含量比为7.6wt%或者更低时,在基本金属从液相至固相的相变换期间形成了η(eta)相化合物(Cu6Sn5)。因此,当铜的总重量相对于接合材料的总重量高于7.6wt%时,不形成Cu6Sn5而是形成Cu3Sn。通过调节铜的总重量的比例为7.6wt%或者更低,能够可靠地形成Cu6Sn5部分。从在Ni层的表面上设置铜层并且可靠地形成Cu6Sn5部分的观点来看,优选地,构成焊料材料的铜的比例低于7.6wt%。
如图6所示,构成焊料材料的铜的比例为5.0wt%的Sn-Cu焊料(Sn-5.0Cu焊料)具有350℃的熔点。在高于350℃的温度下用于半导体元件的元件保护膜可能会劣化。因此,当构成焊料材料的铜的比例高于5.0wt%时,需要采取措施抑制元件保护膜的劣化。通过调节构成焊料材料的铜的比例为5.0wt%或者更低,能够抑制元件保护膜的劣化而无需使用任何特殊措施。
如图6所示,构成焊料材料的铜的比例为4.0wt%的Sn-Cu焊料(Sn-4.0Cu焊料)具有330℃的熔点。取决于其材料,在高于330℃的温度下在半导体元件中使用的电极可能会破裂。因此,当构成焊料材料的铜的比例高于4.0wt%时,需要采取防止电极破裂的措施。例如,需要限制电极的材料。通过调节构成焊料材料的铜的比例为4.0wt%或者更低,能够获得抑制电极破裂的半导体装置而无需采取任何特殊措施。
铜的总重量相对于接合材料的总重量可以为2.0wt%或者更高,更优选地为3.0wt%或者更高。正如从图5和图6清楚可见的,在Sn-2.0Cu焊料中,在从液相至固相的相变换期间形成了η(eta)相化合物(Cu6Sn5)。也即,通过调节铜的总重量为2.0wt%或者更高,Cu6Sn5部分能够可靠地形成在Ni层的表面上。通过调节铜的总重量为3.0wt%或者更高,Cu6Sn5部分能够更稳定地形成在Ni层的表面上。可以根据包含在焊料材料中的Cu的比例来调节铜层的厚度(铜层的重量)。
在上文中,已经详细描述本发明的具体实施例。但是,这些实施例仅是示范性的并且不限制权利要求。权利要求中描述的技术包括各种上述具体实施例的修改以及替换。在本说明书以及附图中描述的技术特征当单独使用或者以其组合使用时呈现了技术重要性,并且不限于在提交申请时在权利要求中描述的组合。在本说明书或者附图中示例的技术同时实现多个目的,并且通过实现众多目的中的一个目的获得技术重要性。
Claims (7)
1.一种制造半导体装置的方法,其特征在于,包括:
将包含至少锡的焊料材料布置在半导体元件与接合构件之间,所述接合构件设置有镍层和铜层,使得所述焊料材料与所述铜层接触,所述镍层设置在所述接合构件的表面上,并且所述铜层设置在所述镍层的表面的至少一部分上;以及
使用所述焊料材料中的锡和所述铜层来熔化以及凝固所述焊料材料以在所述镍层的所述表面上形成Cu6Sn5。
2.根据权利要求1所述的制造半导体装置的方法,其特征在于,
所述焊料材料中包含的铜的重量和与所述焊料材料接触的区域中的铜的重量之和相对于所述焊料材料的重量和与所述焊料材料接触的所述区域中的铜的重量之和为2.0wt%或者更高。
3.根据权利要求1或2所述的制造半导体装置的方法,其特征在于,
所述焊料材料中包含的铜的重量和与所述焊料材料接触的区域中的铜的重量之和相对于所述焊料材料的重量和与所述焊料材料接触的所述区域中的铜的重量之和为7.6wt%或者更低。
4.根据权利要求1至3中任一项所述的制造半导体装置的方法,其特征在于,
所述焊料材料包含铜。
5.根据权利要求4所述的制造半导体装置的方法,其特征在于,
所述焊料材料是包含Sn-0.7Cu作为主要成分的合金。
6.一种半导体装置,其特征在于,包括:
半导体元件;
接合构件,在所述接合构件上设置有镍层;以及
接合层,所述接合构件通过所述接合层与所述半导体元件接合,其中,
所述接合层包括焊料部分和Cu6Sn5部分,所述焊料部分包含至少锡,以及所述Cu6Sn5部分设置在所述镍层与所述焊料部分之间,
所述Cu6Sn5部分与所述镍层的表面的一部分接触且不与所述镍层的所述表面的其它部分接触,并且
所述接合层中包含的铜的比例为2.0wt%或者更高。
7.一种半导体装置,其特征在于,包括:
半导体元件;
接合构件,在所述接合构件上设置有镍层;以及
接合层,所述接合构件通过所述接合层与所述半导体元件接合,其中,
所述接合层包括焊料部分和Cu6Sn5部分,所述焊料部分包含锡和铜,以及所述Cu6Sn5部分设置在所述镍层与所述焊料部分之间,并且
所述焊料部分中包含的铜的重量相对于所述焊料部分的重量低于0.9wt%。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111435646A (zh) * | 2019-01-11 | 2020-07-21 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
CN111916418A (zh) * | 2019-05-09 | 2020-11-10 | 现代自动车株式会社 | 用于双面冷却功率模块的隔离件结构及其制造方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6287759B2 (ja) * | 2014-10-30 | 2018-03-07 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
JP6330786B2 (ja) | 2015-11-16 | 2018-05-30 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP7117747B2 (ja) * | 2016-09-29 | 2022-08-15 | 株式会社クオルテック | 電子部品の製造方法 |
JP6638626B2 (ja) * | 2016-11-21 | 2020-01-29 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP6627726B2 (ja) * | 2016-11-21 | 2020-01-08 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP2018101664A (ja) * | 2016-12-19 | 2018-06-28 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
KR20210120355A (ko) * | 2020-03-26 | 2021-10-07 | 엘지마그나 이파워트레인 주식회사 | 양면 냉각형 파워 모듈 |
JP7428595B2 (ja) * | 2020-06-08 | 2024-02-06 | 日立Astemo株式会社 | 半導体装置、および半導体装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1760783A2 (en) * | 2005-08-31 | 2007-03-07 | Hitachi, Ltd. | Semiconductor device and automotive ac generator |
US20090134501A1 (en) * | 2007-11-26 | 2009-05-28 | Infineon Technologies Ag | Device and method including a soldering process |
US20090243089A1 (en) * | 2008-03-31 | 2009-10-01 | Infineon Technologies Ag | Module including a rough solder joint |
CN101958259A (zh) * | 2009-07-13 | 2011-01-26 | Lsi公司 | 通过添加铜对焊料互连的改善 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
JP4416373B2 (ja) * | 2002-03-08 | 2010-02-17 | 株式会社日立製作所 | 電子機器 |
JP2005340275A (ja) | 2004-05-24 | 2005-12-08 | Denso Corp | 電子部品接合体、その製造方法、およびそれを含む電子装置 |
JP4734134B2 (ja) * | 2006-02-08 | 2011-07-27 | 富士通株式会社 | 半田付け用フラックス及び半田付け用フラックスを用いた実装構造を有する半導体装置 |
CN101432095B (zh) | 2006-04-28 | 2013-01-16 | 株式会社电装 | 泡沫焊锡和电子器件 |
US20100291399A1 (en) | 2006-09-01 | 2010-11-18 | Rikiya Kato | Lid for a functional part and a process for its manufacture |
JP2010179336A (ja) | 2009-02-05 | 2010-08-19 | Toyota Central R&D Labs Inc | 接合体、半導体モジュール、及び接合体の製造方法 |
JP2011044624A (ja) | 2009-08-24 | 2011-03-03 | Hitachi Ltd | 半導体装置および車載用交流発電機 |
JP5517694B2 (ja) | 2010-03-29 | 2014-06-11 | 株式会社 日立パワーデバイス | 半導体装置 |
US8802553B2 (en) * | 2011-02-10 | 2014-08-12 | Infineon Technologies Ag | Method for mounting a semiconductor chip on a carrier |
JP5557788B2 (ja) | 2011-04-07 | 2014-07-23 | 株式会社 日立パワーデバイス | 電子装置の製造方法 |
WO2013133134A1 (ja) * | 2012-03-07 | 2013-09-12 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
JP5677346B2 (ja) * | 2012-03-22 | 2015-02-25 | 株式会社日立製作所 | 半導体素子、半導体装置、半導体装置の製造方法及び接続材料 |
US8814030B2 (en) | 2012-04-17 | 2014-08-26 | Toyota Motor Engineering & Manufacturing North America, Inc. | Improvements of long term bondline reliability of power electronics operating at high temperatures |
JP6061248B2 (ja) | 2013-03-29 | 2017-01-18 | 国立研究開発法人産業技術総合研究所 | 接合方法及び半導体モジュールの製造方法 |
JP2015131340A (ja) * | 2013-12-10 | 2015-07-23 | 住友金属鉱山株式会社 | Au−Sn−Ag系はんだ合金並びにこのAu−Sn−Ag系はんだ合金を用いて封止された電子部品及び電子部品搭載装置 |
JP6287759B2 (ja) | 2014-10-30 | 2018-03-07 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
-
2014
- 2014-10-30 JP JP2014221353A patent/JP6281468B2/ja active Active
-
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- 2015-10-28 TW TW104135423A patent/TWI627686B/zh active
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- 2015-10-28 CN CN201510712706.5A patent/CN105575830B/zh active Active
- 2015-10-29 EP EP15192112.9A patent/EP3021357A1/en not_active Ceased
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1760783A2 (en) * | 2005-08-31 | 2007-03-07 | Hitachi, Ltd. | Semiconductor device and automotive ac generator |
US20090134501A1 (en) * | 2007-11-26 | 2009-05-28 | Infineon Technologies Ag | Device and method including a soldering process |
US20090243089A1 (en) * | 2008-03-31 | 2009-10-01 | Infineon Technologies Ag | Module including a rough solder joint |
CN101958259A (zh) * | 2009-07-13 | 2011-01-26 | Lsi公司 | 通过添加铜对焊料互连的改善 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111435646A (zh) * | 2019-01-11 | 2020-07-21 | 丰田自动车株式会社 | 半导体装置及其制造方法 |
CN111435646B (zh) * | 2019-01-11 | 2023-09-08 | 株式会社电装 | 半导体装置及其制造方法 |
CN111916418A (zh) * | 2019-05-09 | 2020-11-10 | 现代自动车株式会社 | 用于双面冷却功率模块的隔离件结构及其制造方法 |
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CN105575830B (zh) | 2018-10-23 |
BR102015027638A2 (pt) | 2016-06-21 |
US20160126204A1 (en) | 2016-05-05 |
EP3021357A1 (en) | 2016-05-18 |
JP2016092064A (ja) | 2016-05-23 |
KR20160052387A (ko) | 2016-05-12 |
BR102015027638B1 (pt) | 2020-12-01 |
KR101740819B1 (ko) | 2017-05-26 |
US9659892B2 (en) | 2017-05-23 |
JP6281468B2 (ja) | 2018-02-21 |
TW201616587A (zh) | 2016-05-01 |
TWI627686B (zh) | 2018-06-21 |
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