CN105553596B

CN105553596B - A kind of synchronous clock equipment output interface and its type configuration method

Info

Publication number: CN105553596B
Application number: CN201510974293.8A
Authority: CN
Inventors: 黄成�
Original assignee: Datang Telecom Chengdu Information Technology Co Ltd
Current assignee: Datang Telecom Chengdu Information Technology Co Ltd
Priority date: 2015-12-22
Filing date: 2015-12-22
Publication date: 2018-10-30
Anticipated expiration: 2035-12-22
Also published as: CN105553596A

Abstract

The invention discloses a kind of synchronous clock equipment output interfaces, including LIU interface chips, TTL slips to divide chip, electronic switch chip, network transformer and coaxial head；The receiving terminal of LIU interface chips is connected with synchronizing clock signals, and the output end of LIU interface chips is connected to the primary of network transformer, and the secondary of network transformer is connected to spindle nose；TTL slips divide the receiving terminal of chip to be connected with synchronizing clock signals, and the output end that TTL slips divide the output end of chip to be connected to electronic switch chip is connected to the primary of network transformer.Compared with prior art：A kind of board of conventional synchronization clockwork corresponds to a kind of synchronizing clock signals output, need change synchronizing clock signals type that can only replace board after networks are completed, and the present invention is then to pass through software configuration, realize 2048kbit/s signals and the output of 2048kHz signal behaviors, convenient operating maintenance, while also reducing the production of equipment manufacturer, stock, management cost.

Description

A kind of synchronous clock equipment output interface and its type configuration method

Technical field

The invention belongs to Clock Synchronization Technology fields, are related to interface configuration, and especially a kind of synchronous clock equipment output connects Mouth and its type configuration method.

Background technology

China's SNC synchronous network clock equipment output type usually has 1MHz, 5MHz, 10MHz signal and 2048kbit/s signals With 2048kHz signals, wherein most commonly used signal be 2048kbit/s signals and 2048kHz signals.2048kbit/s is one The signal of kind HDB3 codings, 2048kHz is then a clock signal, and G.703 the interface index of two kinds of signals should all meet suggests. The usual way of synchronous clock equipment is to plug different boards, then exports different signals, after networks are completed, if The signal type for needing to change some of which output port, then need to re-replace board, Operation and Maintenance get up it is very inconvenient, together When board type increase, also increase the production of equipment manufacturer, stock, management cost.

Invention content

It is an object of the invention to overcome the above-mentioned prior art, provide a kind of synchronous clock equipment output interface and Its type configuration method.

The purpose of the present invention is achieved through the following technical solutions：

This synchronous clock equipment output interface, including LIU interface chips, TTL slips divide chip, electronic switch chip, Network transformer and coaxial head；The receiving terminal of the LIU interface chips is connected with synchronizing clock signals, LIU interface chips Output end is connected to the primary of network transformer, and the secondary of the network transformer is connected to spindle nose；The TTL slips divide core The receiving terminal of piece is connected with synchronizing clock signals, and the TTL slips divide the output end of chip to be connected to the defeated of electronic switch chip Outlet is connected to the primary of network transformer.

Above-mentioned LIU interface chips are 2048kbit/s.

Above-mentioned synchronizing clock signals are 2048KHz Transistor-Transistor Logic level signals.

Further, above-mentioned electronic switch chip is cmos analog switch.

The present invention also proposes a kind of above-mentioned synchronous clock equipment output interface type configuration method：

So that LIU interface chips is received synchronizing clock signals, generates the primary that differential analog signal is connected to network transformer；Net The secondary of network transformer generates the 2048KHz signals for meeting G.703 standard, connects coaxial head and exports signal；

So that TTL signal slip sub-signal chip is received synchronizing clock signals, generates RS422 level differential signals to electronic cutting Chip is closed, secondary generate of the primary of electronic switch chip output difference signal to network transformer, network transformer meets G.703 the 2048kbit/s signals of standard, connect coaxial head and export signal；

When needing output to meet the 2048KHz signals of G.703 standard, 2048KHz output enable signals are opened, it will 2048kbit/s exports enable signal and closes, and at this moment coaxial head output meets the 2048KHz signals of G.703 standard；

When needing output to meet the 2048kbit/s signals of G.703 standard, 2048kbit/s outputs enable signal is beaten It opens, 2048KHz output enable signals is closed, at this moment coaxial head output meets the 2048kbit/s signals of G.703 standard；

When needing to close output signal, while 2048KHz output enable signals and 2048kbit/s being exported and enabled Signal-off, at this moment coaxial head is without output.

The invention has the advantages that：

The synchronous clock equipment output interface of the present invention is simple in structure easy to implement, and its type configuration method can pass through Software configuration.Compared with prior art：A kind of board of conventional synchronization clockwork corresponds to a kind of synchronizing clock signals output, works as net Network needs change synchronizing clock signals type that can only replace board after the completion of setting up, and the present invention is then by software configuration, in fact Existing 2048kbit/s signals and the output of 2048kHz signal behaviors, convenient operating maintenance, while also reducing the life of equipment manufacturer Production, stock, management cost.

Description of the drawings

Fig. 1 is the structural schematic block diagram of the present invention；

Fig. 2 is the structure diagram of one of which embodiment of the present invention.

Specific implementation mode

The present invention is described in further detail below in conjunction with the accompanying drawings：

Referring to Fig. 1, synchronous clock equipment output interface of the invention, including LIU interface chips, TTL slips divide chip, electricity Sub switch chip, network transformer and coaxial head；The receiving terminal of the LIU interface chips is connected with synchronizing clock signals, LIU The output end of interface chip is connected to the primary of network transformer, and the secondary of the network transformer is connected to spindle nose；It is described TTL slips divide the receiving terminal of chip to be connected with synchronizing clock signals, and the TTL slips divide the output end of chip to be connected to electronic cutting The output end for closing chip is connected to the primary of network transformer.

In highly preferred embodiment of the present invention, LIU interface chips are 2048kbit/s.Synchronizing clock signals are 2048KHz Transistor-Transistor Logic level signal.

Referring to Fig. 2, in the one of which embodiment of the present invention, LIU interface chips, that is, line interface unit LIU, TTL turn Difference chip is differential line driver, and electronic switch chip is cmos analog switch.

The present invention also proposes a kind of synchronous clock equipment output interface type configuration method, specific as follows：

Claims

1. a kind of synchronous clock equipment output interface, which is characterized in that divide chip, electronics including LIU interface chips, TTL slips Switch chip, network transformer and coaxial head；The receiving terminal of the LIU interface chips is connected with synchronizing clock signals, described LIU interface chips are 2048kbit/s, and the synchronizing clock signals are 2048KHz Transistor-Transistor Logic level signals；LIU interface chips it is defeated Outlet is connected to the primary of network transformer, and the secondary of the network transformer is connected to spindle nose；The TTL slips divide chip Receiving terminal be connected with synchronizing clock signals, the TTL slips divide the output that the output end of chip is connected to electronic switch chip End is connected to the primary of network transformer；The electronic switch chip is cmos analog switch.

2. a kind of synchronous clock equipment output interface type configuration method described in claim 1, it is characterised in that：

So that LIU interface chips is received synchronizing clock signals, generates the primary that differential analog signal is connected to network transformer；Network becomes The secondary of depressor generates the 2048KHz signals for meeting G.703 standard, connects coaxial head and exports signal；

So that TTL signal slip sub-signal chip is received synchronizing clock signals, generates RS422 level differential signals to electronic switch core Piece, the primary of electronic switch chip output difference signal to network transformer, G.703 the secondary generation of network transformer meets marks Accurate 2048kbit/s signals, connect coaxial head and export signal；

When needing output to meet the 2048kbit/s signals of G.703 standard, 2048kbit/s output enable signals are opened, it will 2048KHz exports enable signal and closes, and at this moment coaxial head output meets the 2048kbit/s signals of G.703 standard；

Enable signal and 2048kbit/s output enable signals are exported when needing to close output signal, while by 2048KHz It closes, at this moment coaxial head is without output.